CN106601808B - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN106601808B CN106601808B CN201611177956.4A CN201611177956A CN106601808B CN 106601808 B CN106601808 B CN 106601808B CN 201611177956 A CN201611177956 A CN 201611177956A CN 106601808 B CN106601808 B CN 106601808B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 152
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 17
- 229910002704 AlGaN Inorganic materials 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
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- 235000012431 wafers Nutrition 0.000 description 39
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- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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Abstract
The embodiment of the invention discloses a kind of semiconductor devices and preparation method thereof, wherein, semiconductor devices includes: substrate, channel layer on substrate, far from the barrier layer of one side of substrate on channel layer, the interface of barrier layer and channel layer is formed with two-dimensional electron gas, positioned at least one groove structure of barrier layer predetermined position, far from the re-growth layer of channel layer side on barrier layer and groove structure, re-growth layer covers barrier layer and groove structure, the bottom interface of re-growth layer is in contact with the upper surface of channel layer in groove structure, groove structure and the re-growth layer on groove structure constitute groove junction termination structures, far from the source electrode of channel layer side on barrier layer, grid and drain electrode, wherein grid is between source electrode and drain electrode, and it is located at side of the groove junction termination structures far from drain electrode.To sum up, which can guarantee that the field distribution at gate edge is adjusted, and guarantee that the semiconductor devices breakdown voltage distribution on same wafer is uniform.
Description
Technical field
The present embodiments relate to technical field of semiconductors more particularly to a kind of semiconductor devices and preparation method thereof.
Background technique
Nitride semi-conductor material, including GaN, saturated electrons migration rate with higher, high-breakdown-voltage and wide taboo
Bandwidth, just because of these characteristics, high electron mobility transistor (the High Electron Mobility based on GaN
Transistor, HEMT) device attracted the attention of numerous researchers and semiconductor manufacturer.GaN HEMT device is 20 years following
Inherent high speed, efficiently, high-frequency communication and field of power electronics have a very wide range of application prospect.
Pressure voltage generally can only achieve the 20~30% of theoretical value in actual GaN HEMT, this is because close to drain electrode
Gate edge be in drain terminal apply high pressure under will appear electric field concentrate the phenomenon that, so device breakdown is usual in GaN HEMT
The edge in grid close to drain electrode side occurs.Therefore, the voltage endurance capability of device is promoted usually from grid is reduced close to drain electrode
The peak electric field of edge is set about.
In the prior art, the electricity of gate edge can be reduced by the edge grooving of the close drain electrode of grid in barrier layer
Field spike, during forming groove, the prior art generally controls the etching depth of groove by control etch period, but
It is that the recessed of etching is controlled by control etch period due to reaction conditions differences such as the corresponding gas concentrations of wafer different zones
Groove depth be it is highly difficult, therefore it is extremely difficult that the device of different zones, which obtains identical recess etch depth, on wafer
, it is uneven that this has resulted in the semiconductor devices breakdown voltage distribution on same wafer, while between different wafers also not
Preferable breakdown voltage repeatability can be obtained.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of semiconductor devices and preparation method thereof, to solve in the prior art
The semiconductor devices breakdown voltage on uneven, the different wafers of semiconductor devices breakdown voltage distribution on same wafer cannot weigh
Multiple technical problem.
In a first aspect, the embodiment of the invention provides a kind of semiconductor devices, comprising:
Substrate；
Channel layer on the substrate；
Far from the barrier layer of the one side of substrate, the interface of the barrier layer and the channel layer on the channel layer
Place is formed with two-dimensional electron gas；
Positioned at least one groove structure of the barrier layer predetermined position, the bottom of the groove structure terminates at institute
State the interface of barrier layer Yu the channel layer；
Far from the re-growth layer of the channel layer side, the regeneration on the barrier layer and on the groove structure
Long layer covers the barrier layer and the groove structure, the bottom interface of re-growth layer and the channel layer in the groove structure
Upper surface be in contact, the groove structure and re-growth layer on the groove structure constitute groove junction termination structures；
Far from source electrode, grid and the drain electrode of the channel layer side on the barrier layer, wherein the grid is located at
Between the source electrode and the drain electrode, and it is located at the side of the groove junction termination structures far from the drain electrode.
Optionally, the material of the re-growth layer is AlGaN.
Optionally, the bottom of the source electrode, the grid and the drain electrode is directly contacted with the barrier layer, the source
Pole, the drain electrode and the barrier layer form Ohmic contact, and the grid and the barrier layer form Schottky contacts.
Optionally, the bottom of the grid is directly contacted with the re-growth layer, the grid and the re-growth layer shape
At Schottky contacts.
Optionally, the semiconductor devices further includes source metal field plate, and the source metal field plate is described for connecting
Source electrode and the groove junction termination structures, and the joint face of the source metal field plate covers the groove in whole or in part
Junction termination structures and the source electrode.
Optionally, the semiconductor devices further includes dielectric layer, and the dielectric layer covers the re-growth layer, the grid
With the groove junction termination structures, the source metal field plate is connect by the dielectric layer with the groove junction termination structures.
Optionally, medium bridge is formed with below the source metal field plate.
Optionally, the semiconductor devices further includes passivation layer, and the passivation layer is located in the re-growth layer far from institute
The side for stating barrier layer, for being passivated protection to the re-growth layer.
Second aspect, the embodiment of the invention also provides a kind of preparation methods of semiconductor devices, comprising:
One substrate is provided and prepares channel layer over the substrate；
Side on the channel layer far from the substrate prepares barrier layer, the barrier layer and the channel layer interface
Place is formed with two-dimensional electron gas；
At least one groove structure is prepared in the barrier layer predetermined position, the bottom of the groove structure terminates at institute
State the interface of barrier layer Yu the channel layer；
On the barrier layer and the groove structure on far from the channel layer side prepare re-growth layer, it is described again
Grown layer covers the barrier layer and the groove structure, the bottom interface of re-growth layer and institute in the groove junction termination structures
The upper surface for stating channel layer is in contact, and the groove structure and the re-growth layer on the groove structure constitute groove knot end
End structure；
Side on the barrier layer far from the channel layer prepares source electrode, grid and drain electrode, wherein the grid position
Between the source electrode and the drain electrode, and it is located at the side of the groove junction termination structures far from the drain electrode.
Optionally, the side on the barrier layer and on the groove structure far from the channel layer prepares regrowth
Layer, comprising:
It is remote on the barrier layer and on the groove structure by the way of metallorganic chemical vapor deposition
Side from the channel layer prepares re-growth layer.
Optionally, at least one groove structure is prepared in the barrier layer predetermined position, comprising:
By the way of sense coupling or reactive ion etching, in the barrier layer predetermined position
Prepare at least one groove structure.
Optionally, the side on the barrier layer far from the channel layer prepares source electrode, grid and drain electrode, comprising:
Etching and source electrode predeterminated position, grid predeterminated position and the corresponding re-growth layer of predeterminated position that drains, described in exposing
Barrier layer；
Side on the barrier layer far from the channel layer prepares source electrode, grid and drain electrode；
Alternatively,
Etching re-growth layer corresponding with source electrode predeterminated position and drain electrode predeterminated position, exposes the barrier layer；
On the barrier layer far from the channel layer side prepare source electrode and drain electrode, in the re-growth layer with grid
Pole predeterminated position prepares grid at corresponding position.
Semiconductor devices provided in an embodiment of the present invention and preparation method thereof, by being formed in grid close to the side of drain electrode
At least one groove structure, and the bottom that groove structure is arranged ends in the interface of barrier layer and channel layer, it is ensured that
Two-dimensional electron gas under groove structure is depleted, and is formed with re-growth layer in the bottom of groove structure, in groove structure again
The bottom interface of grown layer is in contact with the upper surface of channel layer, and groove structure and re-growth layer thereon constitute groove knot terminal
Structure is adjusted by field distribution of the re-growth layer to gate edge, and the thickness of re-growth layer can be controlled accurately, is protected
Demonstrate,proving the semiconductor devices at the different zones of the same wafer has similar electric field adjusting ability, obtains electricity in a wafer
The uniform semiconductor devices of performance especially breakdown performance, meanwhile, using above-mentioned semiconductor device, it can also be ensured that different wafers
On semiconductor devices have identical electrical property especially breakdown performance, guaranteeing that semiconductor devices on different wafers has can
Repeatability solves half on uneven, the different wafers of semiconductor devices breakdown voltage distribution on same wafer in the prior art
The technical issues of conductor device breakdown voltage cannot repeat.
Detailed description of the invention
In order to more clearly illustrate the technical scheme of the exemplary embodiment of the present invention, below to required in description embodiment
The attached drawing to be used does a simple introduction.Obviously, the attached drawing introduced is present invention a part of the embodiment to be described
Attached drawing, rather than whole attached drawings without creative efforts, may be used also for those of ordinary skill in the art
To obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram for semiconductor devices that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram for another semiconductor devices that the embodiment of the present invention one provides；
Fig. 3 a is the knot for forming five semiconductor devices on a kind of wafer of the offer of the embodiment of the present invention one at different location
Structure schematic diagram；
Fig. 3 b is the offer of the embodiment of the present invention one using semiconductor devices described in the embodiment of the present invention one and existing skill
Profiles versus's schematic diagram of the breakdown voltage of semiconductor devices in art；
Fig. 4 is a kind of flow diagram of the preparation method for semiconductor devices that the embodiment of the present invention one provides；
Fig. 5 is a kind of structural schematic diagram of semiconductor devices provided by Embodiment 2 of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to attached in the embodiment of the present invention
Figure, by specific embodiment, is fully described by technical solution of the present invention.Obviously, described embodiment is of the invention
A part of the embodiment, instead of all the embodiments, based on the embodiment of the present invention, those of ordinary skill in the art are not doing
The every other embodiment obtained under the premise of creative work out, falls within the scope of protection of the present invention.
Embodiment one
Fig. 1 is a kind of structural schematic diagram for semiconductor devices that the embodiment of the present invention one provides, specifically, the present invention is implemented
Example one provides a kind of HEMT device with groove junction termination structures.As shown in Figure 1, the semiconductor devices includes:
Substrate 101；
Channel layer 102 above substrate 101；
Far from the barrier layer 103 of 101 side of substrate, the interface of barrier layer 103 and channel layer 102 on channel layer 102
Place is formed with two-dimensional electron gas (Two-dimensional electron gas, 2DEG)；
Positioned at least one groove structure 104 of 103 predetermined position of barrier layer, the bottom of groove structure 104 is terminated at
The interface of barrier layer 103 and channel layer 102；
Far from the re-growth layer 105 of 102 side of channel layer, re-growth layer on barrier layer 103 and on groove structure 104
105 cover barrier layers 103 and groove structure 104, the bottom interface of re-growth layer 105 and channel layer 102 in groove structure 104
Upper surface is in contact, and groove structure 104 and the re-growth layer 105 on groove structure 104 constitute groove junction termination structures
106；
Source electrode 107, grid 108 and drain electrode 109 on barrier layer 103 far from 102 side of channel layer, wherein grid
108 are located between source electrode 107 and drain electrode 109, and are located at side of the groove junction termination structures 106 far from drain electrode 109.
Illustratively, the material of substrate 101 can be Si, SiC or sapphire, can also be other materials.
Channel layer 102 is located at the top of substrate 101, and the material of channel layer 102 can be GaN or other semiconductor materials,
Such as InAlN, here preferably GaN.
Optionally, nucleating layer and/or buffer layer, substrate 101 can also be formed between channel layer 102 and substrate 101
Top, can independently form nucleating layer or buffer layer, also could be formed with nucleating layer and buffer layer.Preferably, substrate
101 tops are formed with nucleating layer and buffer layer.When being formed with nucleating layer and buffer layer above substrate 101, nucleating layer position
Above substrate 101, buffer layer is located above nucleating layer.Further, the material of nucleating layer and/or buffer layer can be nitridation
Object, is specifically as follows GaN or AlN or other nitride, and nucleating layer and/or buffer layer can be used for matching the material of substrate 101
With epi channels layer 102.
Barrier layer 103 is located at 102 top of channel layer, and the material of barrier layer 103 can be AlGaN or other semiconductor materials
Expect, such as InAlN, here preferably AlGaN.Further, channel layer 102 and barrier layer 103 form heterogeneous semiconductor junction
Structure forms high concentration 2DEG in the interface of channel layer 102 and barrier layer 103.
Positioned at least one groove structure 104 of 103 predetermined position of barrier layer, groove structure 104 runs through barrier layer
103, the bottom of groove structure 104 terminates at the interface of barrier layer 103 Yu channel layer 102, guarantees 104 lower section of groove structure
2DEG part depletion.As shown in Figure 1, Fig. 1 is only illustrated with a groove structure 104, optionally, when semiconductor devices includes
When multiple groove structures 104, the shape of multiple groove structures 104 can be the same or different, and the shape of groove structure 104 can
Think rectangle or trapezoidal, the number of groove and shape is not defined in the embodiment of the present invention.
Re-growth layer 105 is located on barrier layer 103 and on groove structure 104 far from the side of channel layer 102, re-growth layer
105 material can be identical as the material of barrier layer 103, for example, the material of re-growth layer 105 can for AlGaN or other half
Conductor material, such as InAlN, here preferably AlGaN.105 part of re-growth layer is located in groove structure 104, with groove knot
Structure 104 forms groove junction termination structures 106.Since groove structure 104 runs through barrier layer 103, can it is completely depleted below
2DEG, but re-growth layer 105 is formd in groove structure 104, re-growth layer 105 can make to interrupt under groove structure 104
2DEG partially restore again, be distributed in the 2DEG that the interface of channel layer 102 and re-growth layer 105 forms various concentration, tool
Body shows themselves in that under groove junction termination structures 106, channel layer 102 and the 2DEG concentration at re-growth layer 105 are lower, remaining boundary
The 2DEG concentration in face is higher, is redistributed to the 2DEG in semiconductor devices, and the electric field in semiconductor devices is had adjusted
Distribution.
Source electrode 107, grid 108 and drain electrode 109 are also formed on barrier layer 103, specifically, source electrode 107, grid 108
It can be and be respectively formed on barrier layer 103 with drain electrode 109, is i.e. source electrode 107, the bottom of grid 108 and drain electrode 109 and barrier layer
103 directly contact, and source electrode 107, drain electrode 109 and barrier layer 103 form Ohmic contact, and grid 108 and barrier layer 103 form Xiao Te
Base contact, as shown in Figure 1；It can also be that source electrode 107, drain electrode 109 are respectively formed on barrier layer 103, bottom and barrier layer
103 directly contact, and source electrode 107, drain electrode 109 and barrier layer 103 form Ohmic contact, and grid 108 is formed in re-growth layer 105
On, bottom is directly contacted with re-growth layer 105, and grid 108 and re-growth layer 105 form Schottky contacts, as shown in Figure 2.
Optionally, source electrode 107 and drain electrode 109 are located at the edges at two ends position of barrier layer 103, the material of source electrode 107 and drain electrode 109
It can be located between source electrode 107 and drain electrode 109 for one of metals such as Ni, Ti, Al, Au or a variety of combinations, grid 108,
And grid 108 is located at edge side of the groove junction termination structures 106 far from drain electrode 109, in other words groove junction termination structures 106
Positioned at grid 108 close to the edge side of drain electrode 109, the material of grid 108 can be one of metals such as Ni, Pt, Pb, Au
Or a variety of combination.
It is understood that due to existing in grid 108 close to the marginal position of drain electrode 109 in traditional HEMT semiconductor devices
It will appear the phenomenon that electric field is concentrated in the case where 109 application high voltage of drain electrode, therefore, in grid 108 close to the edge of drain electrode 109
Fluted junction termination structures 106 are set, and groove junction termination structures 106 run through barrier layer 103, and in groove junction termination structures
It is formed with re-growth layer 105 in 106, so the not only field distribution at adjustable 108 edge of grid, reduces grid in traditional structure
The electric field spike at pole edge promotes the breakdown voltage of device, and since the thickness of re-growth layer 105 can control, preferably sets
It is identical setting in 105 thickness of re-growth layer in groove junction termination structures 106, it is ensured that under groove junction termination structures 106
It is rectangular at equally distributed 2DEG.
In contrast to re-growth layer 105 is not provided in the prior art, groove junction termination structures are only formed in barrier layer 103
106 the case where, the beneficial effect major embodiment of the embodiment of the present invention guarantee in while improving device electric breakdown strength
Semiconductor device structure can promote the homogeneity of semiconductor devices breakdown voltage in wafer, avoid the etching to barrier layer 103
Rate is unstable or barrier layer 103 is in uneven thickness and caused by 106 bottom residue barrier layer of groove junction termination structures 103 it is thick
Degree has differences in wafer, the homogeneity and repeatability of semiconductor devices electric property is promoted, below mainly from following two
A aspect is illustrated:
On the one hand, the method that the depth of 103 inner groovy junction termination structures 106 of Traditional control barrier layer can use etching,
For nitride-based semiconductor, the wet-etching technology of mature and feasible there is no at present, generally use dry etching nitride-based semiconductor,
Such as inductively coupled plasma (Induction Coupling Plasma, ICP) etches and reactive ion (Reactive
Ion Etching, RIE) dry etch process such as etching, but the reaction condition of dry etch process is complicated, etch rate by
The current strength of application, cavity air pressure, the influence of etching gas concentration distribution, it is difficult to guarantee etch rate in whole wafer
Homogeneity distribution.Groove junction termination structures 106 are formed according to dry etch process such as ICP or RIE, are controlled by etch period
The depth of groove junction termination structures 106 processed can then cause the phenomenon of etching depth unevenness, i.e. groove knot terminal in whole wafer
Thickness being unevenly distributed in wafer of 106 bottom residue barrier layer of structure, and the thickness of remaining barrier layer is to gate edge
Direct influence is distributed in electric field, and the distribution that will cause the breakdown voltage in whole wafer is inconsistent, the property of semiconductor devices
Can not have homogeneity.
On the other hand, the thickness of remaining barrier layer is also related to the thickness of former barrier layer under groove, since barrier layer 103 is
It is deposited after nucleating layer, buffer layer and channel layer 102, the difference of each thickness degree can amplify in this layer, due to 101 temperature of substrate
Fluctuation is spent, it is also uneven distribution in whole wafer that growth atmosphere variation etc., which causes the variation of 103 thickness of barrier layer, this
Even if the etch rate for having resulted in controlling everywhere in wafer is consistent, due to the uneven thickness of former barrier layer, wafer will also result in
Inside the thickness of 106 bottom residue barrier layer of groove junction termination structures is inconsistent everywhere, therefore presents so as to cause electric field strength
The distribution of differentiation out, the distribution that will cause the breakdown voltage in whole wafer is inconsistent, and the performance of semiconductor devices does not have
Homogeneity.
It referring specifically to Fig. 3 a and Fig. 3 b, Fig. 3 a is formed at different location on a kind of wafer of the offer of the embodiment of the present invention one
The structural schematic diagram of five semiconductor devices, Fig. 3 b are the offers of the embodiment of the present invention one using described in the embodiment of the present invention one
The profiles versus of the breakdown voltage of semiconductor devices and semiconductor devices in the prior art schemes, as shown in Figure 3a and Figure 3b shows,
Five semiconductor devices of A, B, C, D, E are formd at the different location of wafer, the semiconductor provided using the embodiment of the present invention one
Five semiconductor devices of A, B, C, D, E of device, breakdown voltage distribution is relatively uniform, the breakdown potential being unable between semiconductor devices
Pressure difference very little, and semiconductor devices in the prior art is used, the breakdown voltage difference between different components is far longer than
The semiconductor devices that the embodiment of the present invention one provides, semiconductor devices provided in an embodiment of the present invention, it is ensured that be located at wafer
Semiconductor devices breakdown voltage distribution at different location is uniform.
Semiconductor device structure provided in an embodiment of the present invention then can be avoided it is above-mentioned because etch rate it is unstable or
Semiconductor devices electric property caused by person's barrier layer 103 is in uneven thickness is uneven, multiple semiconductor devices exist in wafer
The technical issues of breakdown voltage electrical characteristics difference.In semiconductor device structure provided in an embodiment of the present invention, in barrier layer 103
Etching forms groove structure 104, and the bottom of groove structure 104 ends in the interface of barrier layer 103 Yu channel layer 102, because of gesture
It builds 103 and uses different materials from channel layer 102, etch rate selection is easily controlled groove structure 104 than different
The depth of etching terminates at the interface of barrier layer 103 Yu channel layer 102, and the 2DEG under groove structure 104 is complete at this time
Exhaust, groove structure 104 etch after the completion of by the method for regrowth, form re-growth layer 105, groove structure 104 and be located at
Groove junction termination structures 106 are constituted in grown layer 105 on groove structure 104,105 growth thickness of re-growth layer divides in wafer
Cloth is uniform, and thickness can be controlled accurately.With filling of the re-growth layer 105 in groove structure 104, the depth of groove is gradually
Become smaller, can control the thickness of re-growth layer 105, so that the distribution of gate edge electric field can be adjusted.The semiconductor device
For the structure of part not by barrier layer thickness difference everywhere in wafer, crystalline substance is can be obtained in the inconsistent influence of etch rate everywhere in wafer
Groove junction termination structures 106 are to the consistent semiconductor devices of 2DEG regulating power everywhere in circle, thus in wafer at different location
Semiconductor devices there is similar electric field adjusting ability, electrical property is obtained in wafer, and especially breakdown characteristics are uniform partly leads
Body device.
Optionally, semiconductor devices provided in an embodiment of the present invention, can also include passivation layer, and the passivation layer is located at again
Side of the grown layer 105 far from barrier layer 103, for being passivated protection to re-growth layer 102.Optionally, the passivation layer
Current collapse effect can also be reduced.
The embodiment of the present invention also provides a kind of preparation method of semiconductor devices, as shown in figure 4, referring to Fig. 4, the present invention
The preparation method for the semiconductor devices that embodiment provides may comprise steps of:
S410, a substrate is provided and prepares channel layer over the substrate.
Illustratively, the material of substrate 101 can be silicon, silicon carbide or sapphire, can also be other materials.It is optional
, the material of channel layer 102 can be GaN or other semiconductor materials, such as InAlN, here preferably GaN.
S420, the side on the channel layer far from the substrate prepare barrier layer, the barrier layer and the channel
2DEG is formed at bed boundary.
Illustratively, the material of barrier layer 103 can be AlGaN or other semiconductor materials, such as InAlN is excellent here
It is selected as AlGaN.Further, channel layer 102 and barrier layer 103 form semiconductor heterostructure, in channel layer 102 and potential barrier
The interface of layer 103 forms the 2DEG of high concentration.
S430, at least one groove structure is prepared in the barrier layer predetermined position, the bottom of the groove structure is whole
Terminate in the interface of the barrier layer Yu the channel layer.
Illustratively, at least one groove structure 104 is prepared in the predetermined position of barrier layer 103, groove structure 104
Bottom can terminate in the interface of barrier layer 103 Yu channel layer 102, i.e. groove structure 104 runs through barrier layer 103.
Optionally, at least one groove structure 104 is prepared in 103 predetermined position of barrier layer, may include:
By the way of ICP etching or RIE etching, at least one groove knot is prepared in 103 predetermined position of barrier layer
Structure 104.
Optionally, at least one groove structure 104 is prepared in 103 predetermined position of barrier layer, may include:
Photoresist layer is prepared on barrier layer 103；
Photoetching is carried out to the photoresist layer using mask plate, being formed after development includes 104 etch areas of groove structure
Photoresist layer；
The photoresist layer and barrier layer 103 are etched, forms at least one groove structure 104, groove in barrier layer 103
The bottom of structure 104 terminates at the interface of barrier layer 103 Yu channel layer 102.
Optionally, at least one groove structure 104 is prepared in 103 predetermined position of barrier layer, may include:
Mask layer is prepared on barrier layer 103；
Photoresist layer is prepared on the mask layer；
Photoetching is carried out to the photoresist layer using mask plate and is developed, being formed includes 104 etch areas of groove structure
Photoresist layer；
The photoresist layer and mask layer are etched, the mask layer including 104 etch areas of groove structure is formed；
The mask layer and barrier layer 103 are etched, forms at least one groove structure 104, groove knot in barrier layer 103
The bottom of structure 104 terminates at the interface of barrier layer 103 Yu channel layer 102.
S440, the side on the barrier layer and on the groove structure far from the channel layer prepare re-growth layer,
The re-growth layer covers the barrier layer and the groove structure, the bottom interface of re-growth layer and institute in the groove structure
The upper surface for stating channel layer is in contact, and the groove structure and the re-growth layer on the groove structure constitute groove knot end
End structure.
Illustratively, using metallorganic chemical vapor deposition (Metal-organic Chemical Vapor
Deposition, MOCVD) mode, on barrier layer 103 and groove structure 104 far from channel layer 102 side prepare regeneration
Long layer 105, re-growth layer 105 cover barrier layer 103 and groove structure 104, and in groove structure 104 re-growth layer 105 bottom
Portion interface is in contact with the upper surface of channel layer 102, groove structure 104 and 105 structure of re-growth layer on groove structure 104
At groove junction termination structures 106.
Optionally, the thickness of the re-growth layer 105 in groove structure 104 can be identical.
S450, the side on the barrier layer far from the channel layer prepare source electrode, grid and drain electrode, wherein the grid
Pole is located at the side of the groove junction termination structures far from the drain electrode between the source electrode and the drain electrode.
Illustratively, source electrode 107, grid 108 and drain electrode 109 can be prepared respectively on barrier layer 103；It can also be in gesture
Source electrode 107 and drain electrode 109 are prepared in barrier layer 103, and grid 108 is prepared in re-growth layer 105.Source electrode 107, drain 109 material
Matter can be one of metals such as Ni, Ti, Al, Au or a variety of combinations, source electrode 107, drain electrode 109 and the formation of barrier layer 103
Ohmic contact；The material of grid 108 can be one of metals such as Ni, Pt, Pb, Au or a variety of combinations, grid 108 and gesture
Barrier layer 103 or re-growth layer 105 form Schottky contacts.
Optionally, the side on barrier layer 103 far from channel layer 102 prepares source electrode 107, grid 108 and drain electrode 109,
May include:
Etching re-growth layer 105 corresponding with source electrode predeterminated position, grid predeterminated position and drain electrode predeterminated position, exposes gesture
Barrier layer 103；
Side on barrier layer 103 far from channel layer 102 prepares source electrode 107, grid 108 and drain electrode 109.
Alternatively,
Etching re-growth layer 105 corresponding with source electrode predeterminated position and drain electrode predeterminated position, exposes barrier layer 103；
Side on barrier layer 103 far from channel layer 102 prepares source electrode 107 and drain electrode 109, in re-growth layer 105
Grid 108 is prepared at position corresponding with grid predeterminated position.
The preparation method of semiconductor devices provided in an embodiment of the present invention, by running through in the formation of barrier layer predetermined position
The groove structure of barrier layer guarantees to exhaust the 2DEG below groove structure at this time, prepares re-growth layer, groove on the groove structure
The bottom interface of re-growth layer in structure is in contact with the upper surface of channel layer, is adjusted again to the 2DEG below groove structure
Section, groove structure and re-growth layer thereon constitute groove junction termination structures, since the thickness of re-growth layer is controllable, thus right
The distribution of gate edge electric field can be adjusted, and guarantee the structure of the semiconductor devices being prepared not by gesture everywhere in wafer
Barrier layer thickness difference, the inconsistent influence of etch rate everywhere in wafer obtain in wafer groove junction termination structures pair everywhere
The consistent semiconductor devices of 2DEG regulating power, so that the semiconductor devices in wafer at different location has similar electric field tune
Energy saving power obtains the electrical property especially uniform semiconductor devices of breakdown characteristics in wafer.
Embodiment two
Fig. 5 is a kind of structural schematic diagram of semiconductor devices provided by Embodiment 2 of the present invention, specifically, the present invention is implemented
Example two provides a kind of semiconductor devices with Metal field plate, and the Metal field plate can be source metal field plate, be also possible to
Drain metal field plate, the embodiment of the present invention are illustrated by taking source metal field plate as an example.The present embodiment is with above-described embodiment one
Basis improves on the basis of example 1.As described in Figure 5, semiconductor devices provided by Embodiment 2 of the present invention can be with
Include:
Substrate 101；
Channel layer 102 above substrate 101；
Far from the barrier layer 103 of 101 side of substrate, the interface of barrier layer 103 and channel layer 102 on channel layer 102
Place is formed with 2DEG；
Positioned at least one groove structure 104 of 103 predetermined position of barrier layer；
Far from the re-growth layer 105 of 102 side of channel layer on barrier layer 103 and on groove junction termination structures 104, then
Grown layer 105 covers barrier layer 103 and groove structure 104, the bottom interface and channel of re-growth layer 105 in groove structure 104
The upper surface of layer 102 is in contact, and the re-growth layer 105 on groove structure 104 and groove structure 104 constitutes groove junction termination structures
106；
Source electrode 107, grid 108 and drain electrode 109 on barrier layer 103 far from 102 side of channel layer, wherein grid
108 are located between source electrode 107 and drain electrode 109, and are located at side of the groove junction termination structures 106 far from drain electrode 109；
Far from the dielectric layer of 103 side of barrier layer on re-growth layer 105, source electrode 108 and groove junction termination structures 106
110, dielectric layer 110 covers re-growth layer 105, source electrode 108 and groove junction termination structures 106；
The source metal field plate 111 of source electrode 107 and groove junction termination structures 106 is connected, source metal field plate 111 passes through Jie
Matter layer 110 is connect with groove junction termination structures 106, and the joint face of source metal field plate 111 covers groove knot in whole or in part
Terminal structure 106 and source electrode 107.
Illustratively, the material of dielectric layer 011 can be SIN, SIO2、Al2O3One of or a variety of, source metal field
The material of plate 111 can be identical as the material of source electrode 107, can be one of metals such as Ni, Ti, Al, Au or a variety of groups
It closes.Source metal field plate 111 can form Ohmic contact with source electrode 107.
Optionally, the semiconductor devices can also include the medium bridge 112 under source metal field plate 111, source electrode
107 and groove junction termination structures 106 connected by source metal field plate 111 with medium bridge 112.Optionally, medium bridge 112
It can be air bridges or the medium bridge of other media formation, such as SIN, SIO2Or Al2O3One of or a variety of groups
It closes.
Semiconductor devices provided by Embodiment 2 of the present invention, specially a kind of semiconductor device with source metal field plate
Part can not only guarantee the different zones of the same wafer by the way that Metal field plate is arranged at source electrode and groove junction termination structures
The semiconductor devices at place has similar electric field adjusting ability, and it is uniform that electrical property especially breakdown performance is obtained in a wafer
Semiconductor devices, source electrode and gate edge current potential having the same can also be made, the equipotential of field plate itself can be by grid
The power line at edge pulls open, so that the potential gradient of gate edge becomes flat, will reach originally material at gate edge
The electric field strength for puncturing the limit reduces, and peak absorbance is shown up edges of boards edge.
The embodiment of the present invention also provides a kind of preparation method of semiconductor devices with source metal field plate, with embodiment
One provide semiconductor devices preparation method it is identical, only need on the basis of above-mentioned preparation method preparation media layer and source electrode gold
Belong to field plate, which is not described herein again for specific preparation method.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (12)
1. a kind of semiconductor devices characterized by comprising
Substrate；
Channel layer on the substrate；
Far from the barrier layer of the one side of substrate, the interface shape of the barrier layer and the channel layer on the channel layer
At there is two-dimensional electron gas；
Positioned at least one groove structure of the barrier layer predetermined position, the bottom of the groove structure terminates at the gesture
The interface of barrier layer and the channel layer；The groove structure is used for the completely depleted two-dimensional electron gas；
Far from the re-growth layer of the channel layer side, the re-growth layer on the barrier layer and on the groove structure
The barrier layer and the groove structure are covered, the bottom interface of re-growth layer and the channel layer is upper in the groove structure
Surface is in contact, and the groove structure and the re-growth layer on the groove structure constitute groove junction termination structures；It is described
Re-growth layer is for two-dimensional electron gas described in recovered part；
Far from source electrode, grid and the drain electrode of the channel layer side on the barrier layer, wherein the grid is positioned at described
Between source electrode and the drain electrode, and it is located at edge side of the groove junction termination structures far from the drain electrode.
2. semiconductor devices according to claim 1, which is characterized in that the material of the re-growth layer is AlGaN.
3. semiconductor devices according to claim 1, which is characterized in that the source electrode, the grid and the drain electrode
Bottom is directly contacted with the barrier layer, the source electrode, it is described drain electrode with the barrier layer formed Ohmic contact, the grid with
The barrier layer forms Schottky contacts.
4. semiconductor devices according to claim 1, which is characterized in that the bottom of the grid and the re-growth layer are straight
Contact, the grid and the re-growth layer form Schottky contacts.
5. semiconductor devices according to claim 1, which is characterized in that the semiconductor devices further includes source metal field
Plate, the source metal field plate is for connecting the source electrode and the groove junction termination structures, and the source metal field plate
Joint face cover the groove junction termination structures and the source electrode in whole or in part.
6. semiconductor devices according to claim 5, which is characterized in that the semiconductor devices further includes dielectric layer, institute
It states the dielectric layer covering re-growth layer, the grid and the groove junction termination structures, the source metal field plate and passes through institute
Dielectric layer is stated to connect with the groove junction termination structures.
7. semiconductor devices according to claim 6, which is characterized in that be formed with medium below the source metal field plate
Bridge.
8. semiconductor devices according to claim 1-7, which is characterized in that the semiconductor devices further includes blunt
Change layer, the passivation layer is located at the side in the re-growth layer far from the barrier layer, for carrying out to the re-growth layer
Passivation protection.
9. a kind of preparation method of semiconductor devices characterized by comprising
One substrate is provided and prepares channel layer over the substrate；
Side on the channel layer far from the substrate prepares barrier layer, shape at the barrier layer and the channel layer interface
At there is two-dimensional electron gas；
At least one groove structure is prepared in the barrier layer predetermined position, the bottom of the groove structure terminates at the gesture
The interface of barrier layer and the channel layer；The groove structure is used for the completely depleted two-dimensional electron gas；
Side on the barrier layer and on the groove structure far from the channel layer prepares re-growth layer, the regrowth
Layer covers the barrier layer and the groove structure, the bottom interface of re-growth layer and the channel layer in the groove structure
Upper surface is in contact, and the groove structure and the re-growth layer on the groove structure constitute groove junction termination structures；Institute
Re-growth layer is stated for two-dimensional electron gas described in recovered part；
Side on the barrier layer far from the channel layer prepares source electrode, grid and drain electrode, wherein the grid is located at institute
It states between source electrode and the drain electrode, and is located at the side of the groove junction termination structures far from the drain electrode.
10. the preparation method of semiconductor devices according to claim 9, which is characterized in that on the barrier layer and institute
State the side preparation re-growth layer on groove structure far from the channel layer, comprising:
By the way of metallorganic chemical vapor deposition, far from institute on the barrier layer and on the groove structure
State the side preparation re-growth layer of channel layer.
11. the preparation method of semiconductor devices according to claim 9, which is characterized in that preset position in the barrier layer
It sets place and prepares at least one groove structure, comprising:
By the way of sense coupling or reactive ion etching, prepared in the barrier layer predetermined position
At least one groove structure.
12. the preparation method of semiconductor devices according to claim 9, which is characterized in that separate on the barrier layer
The side of the channel layer prepares source electrode, grid and drain electrode, comprising:
Etching re-growth layer corresponding with source electrode predeterminated position, grid predeterminated position and drain electrode predeterminated position, exposes the potential barrier
Layer；
Side on the barrier layer far from the channel layer prepares source electrode, grid and drain electrode；
Alternatively,
Etching re-growth layer corresponding with source electrode predeterminated position and drain electrode predeterminated position, exposes the barrier layer；
Side on the barrier layer far from the channel layer prepares source electrode and drain electrode, pre- with grid in the re-growth layer
If position prepares grid at corresponding position.
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