CN112864241B - Semiconductor device and preparation method thereof - Google Patents

Semiconductor device and preparation method thereof Download PDF

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CN112864241B
CN112864241B CN201911101786.5A CN201911101786A CN112864241B CN 112864241 B CN112864241 B CN 112864241B CN 201911101786 A CN201911101786 A CN 201911101786A CN 112864241 B CN112864241 B CN 112864241B
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subsection
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grid
side wall
substrate
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CN112864241A (en
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赵树峰
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Dynax Semiconductor Inc
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Dynax Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a substrate, a plurality of semiconductor layers, a dielectric layer, a source electrode, a grid electrode and a drain electrode, wherein a first subsection of a grid electrode groove is formed in the semiconductor layers, and a second subsection of the grid electrode groove is formed in the dielectric layer; in the second split part of the grid groove, the first side wall and/or the second side wall are/is provided with at least one step structure; the grid comprises a first grid subsection and a second grid subsection, and the coverage area of the second grid subsection is larger than that of the first grid subsection; the height of the first subsection of the grid is the same as the length from the surface of the ith step to the bottom of the first subsection of the grid groove, and a first gap exists between one side close to the ith sub-side wall and the ith sub-side wall; the gate second portion extends to the ith step surface. In conclusion, the high-frequency characteristic of the semiconductor device can be realized, the short channel effect of the semiconductor device can be inhibited, the resistance of the grid electrode and the parasitic capacitance between the grid electrode and the two-dimensional electron gas can be reduced, and the reliability of the semiconductor device can be improved.

Description

Semiconductor device and preparation method thereof
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The GaN semiconductor device has the advantages of high output power and high working frequency, and is very suitable for application scenes of high frequency and high power, so that the research of GaN high frequency devices is more and more accepted by the industry and becomes one of the hot spots of the research of semiconductor high frequency devices.
In recent years, the application of GaN microwave devices, especially the rapid development of 5G technology, urgently needs the research of strengthening high-frequency and high-power devices, so that the realization of GaN high-frequency device technology has very important significance.
The design of the gate length process window is closely related to the frequency characteristics of a semiconductor device and is one of important process parameters for realizing a high-frequency device, and the smaller the gate length is, the higher the working frequency of the device is. However, how to realize a high-quality small gate length process has many technical bottlenecks. For example, a small gate length will increase the gate resistance, and although the gate resistance can be reduced by a T-gate or gate-cap gate structure, parasitic capacitance will be increased due to the introduction of a gate field plate, and a series of technical problems such as deformation of a fine gate metal strip easily caused by a gate process with a small line width during metal stripping exist.
Therefore, how to simultaneously realize a fine gate process with low parasitic resistance, low parasitic capacitance and high reliability is a problem to be solved urgently at present.
Disclosure of Invention
In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, so as to solve the technical problem that a fine gate process in an existing semiconductor device cannot give consideration to small parasitic resistance, small low parasitic capacitance, and reliable quality, and facilitate improvement of high frequency characteristic application of the semiconductor device in the field of radio frequency microwaves.
In a first aspect, an embodiment of the present invention provides a semiconductor device, including:
a substrate;
the multilayer semiconductor layer is positioned on one side of the substrate, and a first subsection of a grid groove is formed on one side, far away from the substrate, of the multilayer semiconductor layer;
the dielectric layer is positioned on one side, far away from the substrate, of the multilayer semiconductor layer, a grid groove second subsection penetrating through the dielectric layer is formed in the dielectric layer, and the grid groove second subsection and the grid groove first subsection form a grid groove; the second gate trench part comprises a first side wall and a second side wall, the first side wall and/or the second side wall is/are provided with at least one step structure, the at least one step structure comprises an ith step, the ith step comprises an ith sub-side wall, an i +1 th sub-side wall and an ith step surface connecting the ith sub-side wall and the i +1 th sub-side wall, the i +1 th sub-side wall is positioned on one side of the ith sub-side wall, which is far away from the substrate, wherein i is more than or equal to 1, and i is an integer;
the grid electrode is positioned in the grid electrode groove, and the source electrode and the drain electrode are positioned on one side, far away from the substrate, of the multilayer semiconductor layer; the grid electrode comprises a grid electrode first subsection and a grid electrode second subsection which are connected with each other, the grid electrode first subsection fills the grid electrode groove first subsection and is partially positioned in the grid electrode groove second subsection, the grid electrode second subsection is positioned on one side, far away from the substrate, of the grid electrode first subsection and is positioned in the grid electrode groove second subsection, a vertical projection of the grid electrode second subsection in a plane of the substrate covers a vertical projection of the grid electrode first subsection in the plane of the substrate, and the coverage area of the grid electrode second subsection is larger than that of the grid electrode first subsection; the height of the first gate subsection is the same as the length from the surface of the ith step to the bottom of the first gate trench subsection along the first direction, and a first gap exists between one side, close to the ith sub-side wall, of the first gate subsection and the ith sub-side wall along the second direction; along the second direction, the second gate part extends to the surface of the ith step; the first direction is perpendicular to the direction of the source electrode pointing to the drain electrode, and the second direction is perpendicular to the first direction.
Optionally, along the second direction, a second gap exists between one side of the second gate division portion close to the (i + 1) th sub-sidewall and the (i + 1) th sub-sidewall.
Optionally, the first sidewall and/or the second sidewall are formed with a first step structure, the first step structure includes a first sub-sidewall, a second sub-sidewall and a first step surface connecting the first sub-sidewall and the second sub-sidewall, and the second sub-sidewall is located on a side of the first sub-sidewall away from the substrate;
the height of the first gate subsection is the same as the length from the surface of the first step to the bottom of the first gate groove subsection along the first direction, and a first gap exists between one side, close to the first sub-side wall, of the first gate subsection and the first sub-side wall along the second direction;
along the second direction, the second gate division extends to the surface of the first step, and a second gap exists between one side of the second gate division, which is close to the second sub-sidewall, and the second sub-sidewall.
Optionally, the first gate trench portion includes an opening on a side away from the substrate;
along the second direction, the distance between one side of the opening close to the step structure and the first sub-side wall is L1, the extension length of the gate second subsection on the surface of the first step is L2, and the extension length of the first gap is L3; wherein, L1 is more than L2, L1 is more than or equal to L3, L2 is less than 0.1 μm, and L1+ L2 is more than 0.5 μm.
Optionally, along the second direction, the extension length L4 of the second gap satisfies L4 ≦ 0.5 μm.
Optionally, along the first direction, the extension height L5 of the first sub-sidewall satisfies L5>0.1 μm.
Optionally, the multi-layer semiconductor layer includes a barrier layer on a side away from the substrate, the first gate trench partition being located in the barrier layer;
the first gate groove part comprises a third side wall, a fourth side wall and a bottom surface connecting the third side wall and the fourth side wall, and the bottom surface is parallel to the plane of the substrate;
the extension length L6 of the bottom surface along the second direction satisfies L6 ≤ 0.25 μm;
along the first direction, the distance L7 between the bottom surface and the surface of the barrier layer close to the substrate side satisfies L7 ≧ 15 nm.
Optionally, an included angle θ between the third side wall and/or the fourth side wall and the bottom surface satisfies 90 ° ≦ θ ≦ 135 °.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:
providing a substrate;
preparing a multilayer semiconductor layer on one side of the substrate, and preparing a first subsection of a grid groove on one side, far away from the substrate, of the multilayer semiconductor layer;
preparing a dielectric layer on the surface of one side of the multilayer semiconductor layer, which is far away from the substrate, and in the first subsection of the grid groove;
preparing a second gate groove subsection penetrating through the dielectric layer in the dielectric layer, wherein the second gate groove subsection and the first gate groove subsection form a gate groove; the second gate trench part comprises a first side wall and a second side wall, at least one step structure is formed on the first side wall and/or the second side wall, the at least one step structure comprises an ith step, the ith step comprises an ith sub-side wall, an (i + 1) th sub-side wall and an ith step surface connecting the ith sub-side wall and the (i + 1) th sub-side wall, the (i + 1) th sub-side wall is positioned on one side of the ith sub-side wall, which is far away from the substrate, wherein i is more than or equal to 1, and i is an integer;
preparing a grid electrode in the grid electrode groove, and preparing a source electrode and a drain electrode on one side of the multilayer semiconductor layer far away from the substrate, wherein the grid electrode is positioned between the source electrode and the drain electrode; the grid electrode comprises a grid electrode first subsection and a grid electrode second subsection which are connected with each other, the grid electrode first subsection fills the grid electrode groove first subsection and is partially positioned in the grid electrode groove second subsection, the grid electrode second subsection is positioned on one side, away from the substrate, of the grid electrode first subsection and is positioned in the grid electrode groove second subsection, the vertical projection of the grid electrode second subsection in the plane of the substrate covers the vertical projection of the grid electrode first subsection in the plane of the substrate, and the coverage area of the grid electrode second subsection is larger than that of the grid electrode first subsection; the height of the first subsection of the grid electrode is the same as the length from the surface of the ith step to the bottom of the first subsection communicated with the grid electrode along the first direction, and a first gap exists between one side, close to the ith sub-side wall, of the first subsection of the grid electrode and the ith sub-side wall along the second direction; along the second direction, the second gate part extends to the surface of the ith step; the first direction is perpendicular to the direction of the source electrode pointing to the drain electrode, and the second direction is perpendicular to the first direction.
Optionally, the first sidewall and/or the second sidewall are formed with a first step structure, the first step structure includes a first sub-sidewall, a second sub-sidewall and a first step surface connecting the first sub-sidewall and the second sub-sidewall, and the second sub-sidewall is located on a side of the first sub-sidewall away from the substrate;
preparing a second subsection of the gate trench in the dielectric layer, the second subsection penetrating through the dielectric layer, including:
coating a first photoresist on the surface of one side, far away from the substrate, of the dielectric layer, and removing the dielectric layer above and in the first part of the grid groove through a first etching process after exposure and development;
coating a second photoresist on the surface of one side, far away from the substrate, of the dielectric layer, wherein the second photoresist exposes the dielectric layer on the side, close to the source electrode and/or the drain electrode, of the first part of the grid groove;
performing a second etching process on the dielectric layer exposed by the second photoresist, and forming a first initial step structure on one side of the first part of the grid groove close to the source electrode and/or the drain electrode;
coating third photoresist on the surface of one side, far away from the substrate, of the dielectric layer and the surface of one side, far away from the substrate, of the first initial step structure, wherein the third photoresist exposes the first initial step structure of a part, close to the source electrode and/or one side, close to the drain electrode, of the first part of the grid groove;
and carrying out a third etching process on the first initial step structure exposed by the third photoresist to expose the multilayer semiconductor layer on the side of the first part of the grid groove close to the source electrode and/or the drain electrode, and forming a first step structure in the dielectric layer.
According to the semiconductor device and the preparation method thereof provided by the embodiment of the invention, at least one step structure is formed on the first side wall and/or the second side wall in the second subsection of the gate trench, meanwhile, along the first direction, the height of the first subsection of the gate is the same as the length from the surface of the ith step of the step structure to the bottom of the first subsection of the gate trench, and along the second direction, a first gap exists between one side of the first subsection of the gate, which is close to the ith sub-side wall, and the ith sub-side wall; along the second direction, the second gate division extends to the surface of the ith step, so that on one hand, the first gate division can be ensured to have smaller size, and the high-frequency characteristic of the semiconductor device can be realized; on the other hand, the second part of the grid electrode can be ensured to have larger size, which is beneficial to reducing the resistance of the grid electrode, simultaneously enhancing the control capability of the grid electrode of the semiconductor device on a channel region, being beneficial to inhibiting the short channel effect of the semiconductor device and improving the reliability of the device; on the other hand, because the first gap exists between the side, close to the ith sub-side wall, of the first sub-part of the grid electrode and the ith sub-side wall, the parasitic capacitance between the grid electrode and the two-dimensional electron gas can be reduced, and the high-frequency characteristic of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiment of the present invention, a brief introduction will be made to the drawings required for describing the embodiment. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is an enlarged schematic view of a gate trench according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;
FIG. 4 is an enlarged view of another gate trench provided in accordance with an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;
fig. 6 is an enlarged schematic view of another gate trench provided in the embodiment of the present invention;
fig. 7 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;
fig. 8 is an enlarged schematic view of another gate trench provided in the embodiment of the present invention;
fig. 9 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;
fig. 10 is an enlarged schematic view of another gate trench provided in accordance with an embodiment of the present invention;
fig. 11 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 12 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 13 to 21 are schematic structural views of respective steps in the manufacturing method corresponding to fig. 12.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below by way of specific embodiments in conjunction with the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, fig. 2 is an enlarged schematic diagram of a gate trench according to an embodiment of the present invention, specifically, an enlarged schematic diagram of the gate trench in fig. 1, as shown in fig. 1 and fig. 2, the semiconductor device according to an embodiment of the present invention may include:
a substrate 10;
a multilayer semiconductor layer 20 on one side of the substrate 10; a gate groove first division part 31 is formed on one side of the multilayer semiconductor layer 20 away from the substrate 10;
a dielectric layer 40 located on a side of the multilayer semiconductor layer 20 away from the substrate 10, wherein a gate trench second section 32 penetrating through the dielectric layer 40 is formed in the dielectric layer 40, and the gate trench second section 32 and the gate trench first section 31 form a gate trench 30; the gate trench second partition 32 comprises a first side wall 321 and a second side wall 322, at least one step structure 33 is formed on the first side wall 321 and/or the second side wall 322, the at least one step structure 33 comprises an i-th step 33i, the i-th step 33i comprises an i-th sub-side wall 33i1, an i + 1-th sub-side wall 33i2 and an i-th step surface 33i3 connecting the i-th sub-side wall 33i1 and the i + 1-th sub-side wall 33i2, the i + 1-th sub-side 33i2 wall is located on one side of the i-th sub-side wall 33i1 away from the substrate 10, wherein i is greater than or equal to 1, and i is an integer;
a gate electrode 52 located in the gate trench 30, and a source electrode 51 and a drain electrode 53 located on a side of the multilayered semiconductor layer 20 away from the substrate 10, the gate electrode 52 being located between the source electrode 51 and the drain electrode 53; the gate 52 comprises a gate first subsection 521 and a gate second subsection 522 which are connected with each other, the gate first subsection 521 fills the gate trench first subsection 31 and is partially positioned in the gate trench second subsection 32, the gate second subsection 522 is positioned on one side of the gate first subsection 521 away from the substrate 10 and is positioned in the gate trench second subsection 32, a vertical projection of the gate second subsection 522 in the plane of the substrate 10 covers a vertical projection of the gate first subsection 521 in the plane of the substrate 10, and the coverage area of the gate second subsection 522 is larger than that of the gate first subsection 521; along the first direction (Y direction in the figure), the height of the gate first sub-portion 521 is the same as the length of the i-th step surface 33i3 to the bottom of the gate communication first sub-portion 31, and along the second direction (X direction in the figure), a first gap exists between the side of the gate first sub-portion 521 close to the i-th sub-sidewall 33i1 and the i-th sub-sidewall 33i 1; in the second direction, the gate second subsection 522 extends onto the i-th step surface 33i 3; the first direction is perpendicular to the direction from the source 51 to the drain 53, and the second direction is perpendicular to the first direction.
For example, as shown in fig. 1, the first sidewall 321 of the gate trench second partition 32 is close to the source 51, the second sidewall 322 is close to the drain 53, and at least one step structure 33 is formed on the first sidewall 321 and/or the second sidewall 322, and fig. 1 only illustrates that the second sidewall 322 is formed with the step structure 33. As shown in fig. 1, the second sidewall 322 is formed with at least one side step structure 33, the i-th step 33i includes an i-th sub-sidewall 33i1, an i + 1-th sub-sidewall 33i2, and an i-th step surface 33i3 connecting the i-th sub-sidewall 33i1 and the i + 1-th sub-sidewall 33i2, and the i + 1-th sub-sidewall 33i2 wall is located on a side of the i-th sub-sidewall 33i1 away from the substrate 10. In the second direction, a first gap exists between the side of the gate first sub-portion 521 close to the i-th sub-sidewall 33i1 and the i-th sub-sidewall 33i 1; the gate second part 522 extends to the i-th step surface 33i3, and the vertical projection of the gate second part 522 in the plane of the substrate 10 covers the vertical projection of the gate first part 521 in the plane of the substrate 10, and the coverage area of the gate second part 522 is larger than that of the gate first part 521, so that it can be known that in the second direction, the extension length of the gate second part 522 is longer than that of the gate first part 521, and therefore the vertical projection of the gate second part 522 in the plane of the substrate 10 covers the vertical projection of the gate first part 521 in the plane of the substrate 10, and the gate 52 is ensured to have a smaller size on the side close to the substrate 10. Since the size of the gate electrode 52 is closely related to the frequency characteristics of the semiconductor device, the smaller the size of the gate electrode 52, the higher the operating frequency of the semiconductor device. Therefore, the gate 52 is smaller on the side close to the substrate 10, so that the semiconductor device can have a higher operating frequency, which is beneficial to realizing the high-frequency characteristics of the semiconductor device. Furthermore, the side of the gate trench 30 away from the substrate 10 has a larger size, and thus the gate 52 formed in the gate trench 30 has a larger size on the side away from the substrate 10, which is beneficial to reducing the resistance of the gate 52, enhancing the control capability of the gate of the semiconductor device on the channel region, and being beneficial to inhibiting the short channel effect of the semiconductor device and improving the reliability of the device. Further, since the gate 52 is obtained by depositing gate metal on the upper surface of the dielectric layer 40 and in the gate trench 30, the gate metal on the surface of the dielectric layer 40 needs to be stripped after the gate 50 is prepared in the gate trench 30, and the gate trench 30 has a larger opening area on one side of the dielectric layer 40, so that deformation of a gate metal strip caused by stripping the gate metal on the surface of the dielectric layer 40 can be prevented, and the accuracy of the small-size gate preparation process is improved.
Further, along the first direction (Y direction shown in the figure), since the height of the gate first sub-portion 521 is the same as the length from the i-th step surface 33i3 to the bottom of the gate trench first sub-portion 31, and along the second direction (X direction shown in the figure), a first gap exists between the side of the gate first sub-portion 521 close to the i-th sub-sidewall 33i1 and the i-th sub-sidewall 33i1, and along the second direction, the gate second sub-portion 522 extends to the i-th step surface 33i3, a hollow area is formed between the gate second sub-portion 522 and the dielectric layer 40, so that the parasitic capacitance between the gate 52 and the two-dimensional electron gas can be reduced, and the high frequency characteristic of the device can be improved.
Optionally, the material of the substrate 10 may be one or a combination of more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. The multilayer semiconductor layer 20 is located on one side of the substrate 10, and the multilayer semiconductor layer 20 may be specifically a semiconductor material of a III-V compound, and may also be silicon or another semiconductor material, which is not limited in the embodiment of the present invention.
Alternatively, the source electrode 51 and the drain electrode 53 form ohmic contact with the multilayer semiconductor layer 20, and the gate electrode 52 forms schottky contact with the multilayer semiconductor layer 20. Alternatively, the source electrode 51 and the drain electrode 53 may be made of one or a combination of Ni, Ti, Al, Au, and the like, and the gate electrode 52 may be made of one or a combination of Ni, Pt, Pb, Au, and the like.
To sum up, in the semiconductor device provided in the embodiment of the present invention, at least one side step structure is formed on at least one sidewall of the second gate trench partition, a first gap exists between the first gate partition and the sidewall below the step surface, and the second gate partition extends to the step surface, so as to ensure that a vertical projection of the second gate partition on the plane of the substrate covers a vertical projection of the first gate partition on the plane of the substrate, and ensure that the gate has a smaller size on a side close to the substrate, which is beneficial to realizing a high frequency characteristic of the semiconductor device; furthermore, the grid has a larger size on the side far away from the substrate, which is beneficial to reducing the resistance of the grid, simultaneously is beneficial to inhibiting the short channel effect of a semiconductor device and improving the reliability of the device; furthermore, a first gap exists between one side of the first sub-side wall of the grid electrode, which is close to the ith sub-side wall, and the ith sub-side wall, so that the parasitic capacitance between the grid electrode and the two-dimensional electron gas can be further reduced, and the high-frequency characteristic of the device is improved.
Fig. 3 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, and fig. 4 is an enlarged schematic diagram of another gate trench according to an embodiment of the present invention, specifically, an enlarged schematic diagram of the gate trench in fig. 3, as shown in fig. 3 and fig. 4, in the semiconductor device according to an embodiment of the present invention, a second gap exists between the gate second partition 522 and the sub-sidewall 33i2 near the (i + 1) th sub-sidewall along the second direction (X direction shown in the figures). Therefore, the grid electrode 52 is not contacted with the dielectric layer 40, the parasitic capacitance between the grid electrode 52 and the two-dimensional electron gas can be further reduced, and the high-frequency characteristic of the device is improved.
Fig. 5 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, fig. 6 is an enlarged schematic diagram of another gate trench according to an embodiment of the present invention, and in particular, an enlarged schematic diagram of the gate trench in fig. 5, as shown in fig. 5 and 6, fig. 5 and 6 illustrate an example where a two-step structure is formed on the second sidewall 322, as shown in fig. 6, a first-step structure 331 and a second-step structure 332 are formed on the second sidewall 322, where the first-step structure 331 may include a first-step surface 3313, and the second-step structure 312 may include a first sub-sidewall 3321, a second sub-sidewall 3322, and a second-step surface 3323 connecting the first sub-sidewall 3321 and the second sub-sidewall 3322. In the first direction, the height of the first gate subsection 521 may be the same as the length from the first step surface 3313 to the bottom of the first subsection of the gate trench, or the same as the length from the second step surface 3323 to the bottom of the first subsection of the gate trench, and fig. 6 illustrates the height of the first gate subsection 521 as the same as the length from the second step surface 3323 to the bottom of the first subsection of the gate trench. With continued reference to fig. 6, along the first direction, the height of the gate first sub-portion 521 is the same as the length from the second step surface 3323 to the bottom of the gate trench first sub-portion, and along the second direction (X direction as shown in the figure), a first gap exists between the side of the gate first sub-portion 521 close to the first sub-sidewall 3321 and the first sub-sidewall 3321; in the second direction, the gate second subsection 522 extends onto the second level-difference surface 3323; the first direction is perpendicular to the direction from the source 51 to the drain 53, and the second direction is perpendicular to the first direction. Therefore, the vertical projection of the second grid part on the plane of the substrate can be ensured to cover the vertical projection of the first grid part on the plane of the substrate, and the grid is ensured to have smaller size on one side close to the substrate, so that the high-frequency characteristic of the semiconductor device is favorably realized; furthermore, the grid has a larger size on the side far away from the substrate, which is beneficial to reducing the resistance of the grid, simultaneously is beneficial to inhibiting the short channel effect of a semiconductor device and improving the reliability of the device; furthermore, a first gap exists between one side of the first sub-part of the grid electrode, which is close to the ith sub-side wall, and the ith sub-side wall, so that the parasitic capacitance between the grid electrode and the two-dimensional electron gas can be further reduced, and the high-frequency characteristic of the device is improved.
Fig. 7 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, fig. 8 is an enlarged schematic diagram of another gate trench according to an embodiment of the present invention, and specifically, fig. 7 and 8 illustrate that at least one step structure is formed on each of the first sidewall 321 and the second sidewall 322, as shown in fig. 7 and 8, an i-th step structure 33i is formed on each of the first sidewall 321 and the second sidewall 322, and a first gap exists between a side of the first gate sub-portion 521 close to the i-th sub-sidewall 33i1 and the i-th sub-sidewall 33i 1; the gate second subsection 522 extends onto the i-th step surface 33i 3. Therefore, the vertical projection of the second grid part on the plane of the substrate can be ensured to cover the vertical projection of the first grid part on the plane of the substrate, and the grid is ensured to have smaller size on one side close to the substrate, so that the high-frequency characteristic of the semiconductor device is favorably realized; furthermore, the grid has a larger size on the side far away from the substrate, which is beneficial to reducing the resistance of the grid, simultaneously is beneficial to inhibiting the short channel effect of a semiconductor device and improving the reliability of the device; furthermore, a first gap exists between one side of the first sub-part of the grid electrode, which is close to the ith sub-side wall, and the ith sub-side wall, so that the parasitic capacitance between the grid electrode and the two-dimensional electron gas can be further reduced, and the high-frequency characteristic of the device is improved.
In summary, the above embodiments have described the step structure formed on the different sides of the second portion of the gate trench and the specific arrangement manner of the step structure, and it can be understood that, in the embodiments of the present invention, it is not limited to which side of the second portion of the gate trench the step structure is formed and which step structure includes several steps, but only needs to ensure that at least one step structure is formed on at least one side wall of the second portion of the gate trench, that the height of the first portion of the gate is the same as the length from the surface of the ith step to the bottom of the first portion of the gate trench, that a first gap exists between one side of the first portion of the gate close to the step structure and the sub-sidewall below the surface of the ith step, that the second portion of the gate extends to the surface of the ith step, that the vertical projection of the second portion of the gate on the plane of the substrate covers the vertical projection of the first portion of the gate on the plane of the substrate, and that the coverage area of the second portion of the gate is larger than that of the first portion of the gate The coverage area is only required, the high-frequency characteristic of the semiconductor device is ensured to be good, meanwhile, the grid electrode is low in resistance, and the parasitic capacitance between the grid electrode and the two-dimensional electron gas is only required.
On the basis of the above-mentioned embodiment, in order to ensure that the step structure is simply configured, the first sidewall 321 and/or the second sidewall 322 may be configured to have a first step structure, as shown in fig. 1 to 4. At this time, the first step structure 331 includes a first sub-sidewall 3311, a second sub-sidewall 3312, and a first step surface 3313 connecting the first sub-sidewall 3311 and the second sub-sidewall 3312, wherein the second sub-sidewall 3312 is located on a side of the first sub-sidewall 3311 away from the substrate 10; along the first direction, the height of the gate first sub-portion 521 is the same as the length from the first step-surface 3313 to the bottom of the gate trench first sub-portion, and along the second direction (as shown in the X direction), a first gap exists between the side of the gate first sub-portion 521 close to the first sub-sidewall 3311 and the first sub-sidewall 3311; along the second direction, the gate second portion 522 extends to the first step surface 3313, and a second gap exists between a side of the gate second portion 522 close to the second sub-sidewall 3312 and the second sub-sidewall 3312. Therefore, the technical effects of good high-frequency characteristics, low resistance of the grid electrode and low parasitic capacitance between the grid electrode and the two-dimensional electron gas of the semiconductor device can be realized under the conditions of simple structure and simple preparation process of the semiconductor device.
Optionally, fig. 9 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, and fig. 10 is a schematic structural diagram of another gate trench provided by an embodiment of the present invention, specifically, a schematic structural diagram of a gate trench in the semiconductor device shown in fig. 9, and with reference to fig. 4 and fig. 10, the first gate trench partition 31 includes a third sidewall 311, a fourth sidewall 312, and a bottom surface 313 connecting the third sidewall 311 and the fourth sidewall 312, wherein an included angle θ between the third sidewall 311 and/or the fourth sidewall 312 and the bottom surface 313 satisfies 90 ° ≦ θ ≦ 135 °.
Specifically, fig. 4 illustrates an example in which the included angles between the third and fourth sidewalls 311 and 312 and the bottom surface 313 are all 90 °, and fig. 10 illustrates an example in which the included angle between the third sidewall 311 and the bottom surface 313 is 90 °, and the included angle θ between the fourth sidewall 312 and the bottom surface 313 satisfies 90 ° < θ ≦ 135 °. Illustratively, when the included angle between the third sidewall 311 and/or the fourth sidewall 312 and the bottom surface 313 is larger, the resistance of the gate 52 is smaller, but the parasitic capacitance between the gate 52 and the two-dimensional electron gas is larger; when the angle between the third sidewall 311 and/or the fourth sidewall 312 and the bottom surface 313 is small, the parasitic capacitance between the gate electrode 52 and the two-dimensional electron gas is small, but the resistance of the gate electrode 52 is large. Therefore, considering the resistance and the parasitic capacitance together, it is necessary to set the included angle between the third sidewall 311 and/or the fourth sidewall 312 and the bottom surface 313 reasonably to ensure the good electrical characteristics of the semiconductor device. Specifically, according to practical situations, the included angle between the third sidewall 311 and/or the fourth sidewall 312 and the bottom surface 313 may be set to any angle value between 90 ° and 135 °, for example, 90 °, 100 °, 115 °, 120 °, or 135 °, and the specific angle value is not limited in the embodiment of the present invention.
Optionally, as shown with continued reference to fig. 4 and 10, the gate trench first section 31 may further include an opening 314 at a side away from the substrate 10; along the second direction (X direction as shown in the figure), the distance between the side of the opening 314 close to the step structure and the first sub-sidewall 3311 is L1, the extension length of the gate second portion on the first-level step surface 3313 is L2, and the extension length of the first gap is L3; wherein, L1 is more than L2, L1 is more than or equal to L3, L2 is less than 0.1 μm, and L1+ L2 is more than 0.5 μm.
For example, embodiments of the present invention only need to provide that the gate second subsection 522 extends to the first level step surface 3313, and the extension length L2 of the gate second subsection 522 on the first level step surface 3313 may be small, such as L2<0.1 μm. Further, in order to ensure that the gate second part 522 has a strong capability of adjusting the parasitic capacitance, a distance L1 between the side of the opening 314 close to the step structure and the first sub-sidewall 3311 may be set to be larger, for example, L1+ L2>0.5 μm. The extension length L2 of the gate second portion 522 on the first-level step surface 3313 and the distance L1 between the side of the opening 314 close to the step structure and the first sub-sidewall 3311 are not specifically limited in the embodiments of the present invention, and the above parameters may be set according to specific product requirements.
Further, as shown in fig. 4, when the included angles between the third side wall 311 and the bottom surface 313 and the fourth side wall 312 are both 90 °, the distance L1 between the side of the opening 314 close to the step structure and the first sub-side wall 3311 and the extension length L3 of the first gap satisfy L1 ═ L3; as shown in fig. 10, when the included angle between the third sidewall 311 and/or the fourth sidewall 312 and the bottom surface 313 is greater than 90 °, the distance L1 between the side of the opening 314 close to the step structure and the first sub-sidewall 3311 and the extension length L3 of the first gap satisfy L1.> L3, and the distance between the side of the opening 314 close to the step structure and the first sub-sidewall 3311 and the extension length of the first gap are determined according to the included angle between the third sidewall 311 and the fourth sidewall 312 and the bottom surface 313.
Optionally, with continued reference to fig. 4, along the second direction, an extension length L4 of a second gap between a side of the gate second portion 522 close to the second sub-sidewall 3313 and the second sub-sidewall 3313 satisfies L4 ≦ 0.5 μm. In the embodiment of the present invention, only the second gate subsection 522 is required to be arranged without contacting the dielectric layer 40, so as to ensure that the parasitic capacitance between the gate 52 and the two-dimensional electron gas can be further reduced. Considering the process manufacturing precision, the extension length L4 of the second gap between the side of the gate second sub-portion 522 close to the second sub-sidewall 3313 and the second sub-sidewall 3313 may be set to satisfy L4 ≤ 0.5 μm, and the specific value may be set according to actual product requirements, which is not limited in the embodiment of the present invention.
Alternatively, with continued reference to fig. 4, the extension height L5 of the first sub-sidewall 3311 in the first direction (Y direction as shown in the figure) perpendicular to the substrate 10 satisfies L5>0.1 μm. For example, the extension length of the first sub-sidewall 3311 along the first direction may be understood as the distance between the gate second sub-portion 522 and the multi-layer semiconductor layer 20, and a reasonable extension length of the first sub-sidewall 3311 along the first direction may ensure a reasonable parasitic capacitance between the gate second sub-portion 522 and the multi-layer semiconductor layer 20. In consideration of the process preparation precision, the extension height L5 of the first sub-sidewall 3311 along the first direction may be set to satisfy L5>0.1 μm, and specific values may be set according to actual product requirements, which is not limited in the embodiment of the present invention.
Optionally, with continued reference to fig. 4, the multilayer semiconductor layer 20 includes a barrier layer 204 on a side away from the substrate 10, the gate trench first sub-portion 31 being located in the barrier layer 204; the gate trench first portion 31 includes a third sidewall 311, a fourth sidewall 312, and a bottom surface 313 connecting the third sidewall 311 and the fourth sidewall 312, the bottom surface 313 is parallel to the plane of the substrate 10; along the second direction (X direction as shown in the figure), the extension length L6 of the bottom surface 313 satisfies L6 ≦ 0.25 μm; in a first direction (Y direction as shown in the figure), a distance L7 between the bottom surface 313 and the surface of the barrier layer 204 on the side close to the substrate 10 satisfies L7 ≧ 15nm, the first direction being perpendicular to the substrate 10.
Illustratively, the extension length of the bottom surface 313, i.e., the extension length of the gate 52 on the side close to the substrate 10, and the extension length L6 of the bottom surface 313 is set to satisfy L6 ≦ 0.25 μm, which is advantageous for realizing the high frequency characteristics of the semiconductor device. Preferably, when the extension length L6 of the bottom surface 311 satisfies L6 ≦ 0.2 μm, the extension length of the gate electrode 52 on the side close to the substrate 10 can be secured to be small, and the high frequency characteristics of the semiconductor device can be sufficiently exhibited. Furthermore, the distance L7 between the bottom surface 313 and the surface of the barrier layer 204 close to the substrate 10 satisfies L7 equal to or greater than 15nm, so that when the channel of the semiconductor device is in an on state, the semiconductor device can obtain high-frequency characteristics, and meanwhile, sufficient two-dimensional electron gas is provided below the gate trench 30, thereby ensuring the low on resistance of the semiconductor device.
Alternatively, and with continued reference to fig. 1, 3, 5, 7, and 9, embodiments of the invention provide a multilayer semiconductor layer 20 that may include a nucleation layer 201 on a substrate 10; a buffer layer 202 located on a side of the nucleation layer 201 remote from the substrate 10; a channel layer 203 on a side of the buffer layer 202 away from the nucleation layer 201; a barrier layer 204 on a side of the channel layer 203 remote from the buffer layer 202.
Illustratively, the material of the nucleation layer 201 and the buffer layer 202 may be nitride, specifically, GaN or AlN or other nitride, and may also be silicon or other semiconductor material. The nucleation layer 201 and the buffer layer 202 may be used to match the material of the substrate 10 and the epitaxial channel layer 203. The material of the channel layer 203 may be GaN or InAlN, or may be silicon or other semiconductor material. The barrier layer 204 is located above the channel layer 203, and the material of the barrier layer 204 may be a material including a gallium-based compound semiconductor material or a nitrogen-based compound semiconductor material, such as InxAlyGazN1-x-y-z, where x is greater than or equal to 0 and less than or equal to 1, y is greater than or equal to 0 and less than or equal to 1, and z is greater than or equal to 0 and less than or equal to 1. Optionally, the channel layer 203 and the barrier layer 204 form a semiconductor heterojunction structure, and a high-concentration two-dimensional electron gas is formed at an interface between the channel layer 203 and the barrier layer 204; optionally, the material of the barrier layer 204 may also be silicon or other semiconductor material. Therefore, the multilayer semiconductor layer 20 provided in the embodiment of the present invention may be a semiconductor material of a III-V compound, or may be silicon or another semiconductor material, which is not limited in the embodiment of the present invention.
It should be appreciated that embodiments of the present invention improve the reliability of semiconductor devices from the perspective of semiconductor device gate trench structure design. The semiconductor device includes, but is not limited to: a High power gallium nitride High Electron Mobility Transistor (HEMT) operating in a High voltage and High current environment, a Silicon-On-Insulator (SOI) structure Transistor, a gallium arsenide (GaAs) based Transistor, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), a Metal-Insulator-Semiconductor Field Effect Transistor (Metal-Insulator-Semiconductor Transistor, MISFET), a Double Heterojunction Field Effect Transistor (dhjunction), a Junction-Field-Effect Transistor (JFET), a Metal-Semiconductor Field Effect Transistor (Metal-Semiconductor-Insulator-Semiconductor Field Effect Transistor, JFET), a Metal-Semiconductor Field Effect Transistor (Metal-Semiconductor-Insulator-Semiconductor Field Effect Transistor, Metal-Semiconductor Field Effect Transistor, Heterojunction Field Effect Transistor, JFET), MISHFET for short) or other field effect transistors.
Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, as shown in fig. 7, the method for manufacturing a semiconductor device according to the embodiment of the present invention may include:
and S110, providing a substrate.
Illustratively, the material of the substrate may be Si, SiC or sapphire, but may also be other materials suitable for growing semiconductor materials. The substrate can be prepared by atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.
And S120, preparing a multilayer semiconductor layer on one side of the substrate, and preparing a first subsection of a grid groove on one side, far away from the substrate, of the multilayer semiconductor layer.
Illustratively, the multilayer semiconductor layer is located on one side of the substrate, and the multilayer semiconductor layer may be specifically a semiconductor material of a III-V compound, and may also be silicon or another semiconductor material, which is not limited in this embodiment of the present invention.
Illustratively, the first subsection of the gate trench is formed in a gate designated area on a side of the second semiconductor layer away from the substrate by an etching method.
S130, preparing dielectric layers on the surface of one side, away from the substrate, of the multilayer semiconductor layer and in the first subsection of the grid groove.
Specifically, the first subsection of the grid groove is formed in the multilayer semiconductor layer, the dielectric layer is prepared on the surface of one side, away from the substrate, of the multilayer semiconductor layer and in the first subsection of the grid groove, and the dielectric layer covers one side, away from the substrate, of the multilayer semiconductor layer and the bottom face, located in the multilayer semiconductor layer, of the first subsection of the grid groove.
S140, preparing a second part of the grid groove penetrating through the dielectric layer in the dielectric layer.
And preparing a second part of the grid groove penetrating through the dielectric layer in the dielectric layer by adopting an etching method, wherein the second part of the grid groove and the first part of the grid groove form the grid groove. The second gate trench division comprises a first side wall and a second side wall, the first side wall and/or the second side wall are/is provided with at least one step structure, the at least one step structure comprises an ith step, the ith step comprises an ith sub-side wall, an (i + 1) th sub-side wall and an ith step surface connected with the ith sub-side wall and the (i + 1) th sub-side wall, the (i + 1) th sub-side wall is located on one side, far away from the substrate, of the ith sub-side wall, wherein i is more than or equal to 1, and i is an integer.
S150, preparing a grid electrode in the grid electrode groove, and preparing a source electrode and a drain electrode on one side, far away from the substrate, of the multilayer semiconductor layer, wherein the grid electrode is located between the source electrode and the drain electrode.
Illustratively, the gate comprises a first gate subsection and a second gate subsection which are connected with each other, the first gate subsection fills the first gate subsection and is partially positioned in the second gate subsection, the second gate subsection is positioned on one side of the first gate subsection away from the substrate and is positioned in the second gate subsection, the vertical projection of the second gate subsection in the plane of the substrate covers the vertical projection of the first gate subsection in the plane of the substrate, and the coverage area of the second gate subsection is larger than that of the first gate subsection; along the first direction, the height of the first subsection of the grid electrode is the same as the length from the surface of the ith step to the bottom of the first subsection of the grid electrode groove, and along the second direction, a first gap exists between one side, close to the ith sub-side wall, of the first subsection of the grid electrode and the ith sub-side wall; along the second direction, the second gate part extends to the surface of the ith step; the first direction is perpendicular to the direction of the source electrode pointing to the drain electrode, and the second direction is perpendicular to the first direction. Therefore, in the second direction, the extension length of the second part of the grid is longer than that of the first part of the grid, the grid is enabled to have a smaller size on one side close to the substrate, the grid in the grid groove is enabled to have a larger size on one side far away from the substrate, the semiconductor device is enabled to have a higher working frequency, the high-frequency characteristic of the semiconductor device is facilitated to be realized, meanwhile, the resistance of the grid is facilitated to be reduced, meanwhile, the control capability of the grid of the semiconductor device on a channel region is enhanced, the short channel effect of the semiconductor device is facilitated to be inhibited, and the reliability of the device is improved. Furthermore, because the height of the first gate subsection is the same as the length from the surface of the ith step to the bottom of the first gate trench subsection, and along the second direction (such as the X direction shown in the figure), a first gap exists between one side of the first gate subsection close to the ith sub-sidewall and the ith sub-sidewall, and along the second direction, the second gate subsection extends to the surface of the ith step, a hollow-out area is formed between the second gate subsection and the dielectric layer, so that the parasitic capacitance between the gate and the two-dimensional electron gas can be reduced, and the high-frequency characteristic of the device can be improved.
Fig. 12 is a schematic flow chart illustrating a method for manufacturing another semiconductor device according to an embodiment of the present invention, and fig. 13 to 21 are process flow charts illustrating steps of the method for manufacturing the semiconductor device according to fig. 12, which are provided in detail below by taking as an example that the first sidewall and/or the second sidewall of the second subsection of the gate trench is formed with the first step structure in the actual manufacturing process of the semiconductor device.
S210, providing a substrate.
As shown in fig. 13, the material of the substrate 10 may be Si, SiC or sapphire, and may be other materials suitable for growing semiconductor materials.
S220, preparing a multilayer semiconductor layer on one side of the substrate, and preparing a first subsection of a grid groove on one side, far away from the substrate, of the multilayer semiconductor layer.
As shown in fig. 14, a multilayer semiconductor layer 20 is prepared on the substrate 10 side, and a gate trench first subsection 31 is prepared by etching the multilayer semiconductor layer 20 on the side of the multilayer semiconductor layer away from the substrate.
S230, preparing dielectric layers on the surface of one side, away from the substrate, of the multilayer semiconductor layer and in the first subsection of the grid groove.
As shown in fig. 15, a dielectric layer 40 is formed on the surface of the multilayer semiconductor layer 20 on the side away from the substrate 10 and within the gate trench first section 31.
And S240, coating a first photoresist on the surface of one side, far away from the substrate, of the dielectric layer, and removing the dielectric layer located above the first branch part of the grid groove and in the first branch part of the grid groove through a first etching process after exposure and development.
As shown in fig. 16, a first photoresist 51 is coated on a side of the dielectric layer 40 away from the substrate 10, and the dielectric layer 40 above the gate trench first partition 31 and in the gate trench first partition 31 is removed by a first etching process after exposure and development.
And S250, coating a second photoresist on the surface of one side, far away from the substrate, of the dielectric layer, wherein the second photoresist exposes the dielectric layer on the side, close to the source electrode and/or the drain electrode, of the first part of the grid groove.
As shown in fig. 17, a second photoresist 52 is coated on a surface of the dielectric layer 40 on a side away from the substrate 10, and the second photoresist 52 exposes a portion of the dielectric layer 40 on a side of the first gate trench portion 31 close to the source and/or drain. Fig. 17 illustrates an example of the second photoresist 52 exposing a portion of the dielectric layer 40 on the drain side of the first gate trench subsection 31.
S260, performing a second etching process on the dielectric layer exposed by the second photoresist, and forming a first initial step structure on the first part of the grid groove close to the source electrode and/or the drain electrode.
As shown in fig. 18, a second etching process is performed on the exposed dielectric layer 40 of the second photoresist 52, and a first preliminary step structure 34 is formed on the drain side of the first gate trench subsection 31, wherein the first preliminary step structure 34 is located between the surface of the dielectric layer 40 on the side close to the substrate 10 and the surface of the dielectric layer 40 on the side far from the substrate 10.
And S270, coating third photoresist on the surface of one side, far away from the substrate, of the dielectric layer and the surface of one side, far away from the substrate, of the first initial step structure, wherein the third photoresist exposes the first initial step structure of the first part, close to the source electrode and/or the drain electrode, of the first part of the grid groove.
As shown in fig. 19, a third photoresist 53 is coated on a surface of the dielectric layer 10 on a side away from the substrate 10 and a surface of the first preliminary step structure 34 on a side away from the substrate 10, and the third photoresist 53 exposes a portion of the first preliminary step structure 34 on a side of the first gate trench partition 31 close to the drain.
And S280, performing a third etching process on the first initial step structure exposed by the third photoresist to expose the multilayer semiconductor layer on the side, close to the source electrode and/or the drain electrode, of the first part of the gate trench, and forming a first step structure in the dielectric layer.
As shown in fig. 20, a third etching process is performed on the exposed first preliminary step structure 34 of the third photoresist 53 to expose the multilayer semiconductor layer 20 at the side of the first gate trench subsection 31 close to the drain, and a first step structure 331 is formed in the dielectric layer 40.
S290, preparing a grid electrode in the grid electrode groove, and preparing a source electrode and a drain electrode on one side of the multilayer semiconductor layer far away from the substrate, wherein the grid electrode is positioned between the source electrode and the drain electrode.
As shown in fig. 21, a gate electrode 52 is formed in the gate trench 30, and a source electrode 51 and a drain electrode 53 are formed on the side of the multilayered semiconductor layer 20 away from the substrate 10, the gate electrode 52 being located between the source electrode 51 and the drain electrode 53.
To sum up, in the method for manufacturing a semiconductor device provided by the embodiment of the present invention, at least one side step structure is formed on at least one sidewall of the second gate trench partition, a first gap exists between the first gate partition and the sidewall below the step surface, and the second gate partition extends to the step surface, so that it is ensured that a vertical projection of the second gate partition on the plane of the substrate covers a vertical projection of the first gate partition on the plane of the substrate, and it is ensured that the gate has a smaller size on a side close to the substrate, which is beneficial to realizing high-frequency characteristics of the semiconductor device; furthermore, the grid has a larger size on the side far away from the substrate, which is beneficial to reducing the resistance of the grid, simultaneously is beneficial to inhibiting the short channel effect of a semiconductor device and improving the reliability of the device; furthermore, a first gap exists between one side of the first sub-part of the grid electrode, which is close to the ith sub-side wall, and the ith sub-side wall, so that the parasitic capacitance between the grid electrode and the two-dimensional electron gas can be further reduced, and the high-frequency characteristic of the device is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
the multilayer semiconductor layer is positioned on one side of the substrate, and a first subsection of a grid groove is formed on one side, far away from the substrate, of the multilayer semiconductor layer;
the dielectric layer is positioned on one side, far away from the substrate, of the multilayer semiconductor layer, a grid groove second subsection penetrating through the dielectric layer is formed in the dielectric layer, and the grid groove second subsection and the grid groove first subsection form a grid groove; the second gate trench part comprises a first side wall and a second side wall, at least one step structure is formed on the first side wall and/or the second side wall, the at least one step structure comprises an ith step, the ith step comprises an ith sub-side wall, an (i + 1) th sub-side wall and an ith step surface connecting the ith sub-side wall and the (i + 1) th sub-side wall, the (i + 1) th sub-side wall is positioned on one side of the ith sub-side wall, which is far away from the substrate, wherein i is more than or equal to 1, and i is an integer;
the grid electrode is positioned in the grid electrode groove, and the source electrode and the drain electrode are positioned on one side, far away from the substrate, of the multilayer semiconductor layer; the grid comprises a grid first subsection and a grid second subsection which are connected with each other, the grid first subsection fills the grid groove first subsection and is partially positioned in the grid groove second subsection, the grid second subsection is positioned on one side, away from the substrate, of the grid first subsection and is positioned in the grid groove second subsection, the vertical projection of the grid second subsection in the plane of the substrate covers the vertical projection of the grid first subsection in the plane of the substrate, and the coverage area of the grid second subsection is larger than that of the grid first subsection; the height of the first gate subsection is the same as the length from the surface of the ith step to the bottom of the first gate trench subsection along the first direction, and a first gap exists between one side, close to the ith sub-side wall, of the first gate subsection and the ith sub-side wall along the second direction; along the second direction, the second gate part extends to the surface of the ith step; the first direction is perpendicular to the direction of the source electrode pointing to the drain electrode, and the second direction is perpendicular to the first direction.
2. The semiconductor device according to claim 1, wherein a second gap exists between a side of the gate second partition close to the (i + 1) th sub-sidewall and the (i + 1) th sub-sidewall along the second direction.
3. The semiconductor device according to claim 2, wherein the first sidewall and/or the second sidewall are formed with a first-level step structure including a first sub-sidewall, a second sub-sidewall, and a first-level step surface connecting the first sub-sidewall and the second sub-sidewall, the second sub-sidewall being located on a side of the first sub-sidewall away from the substrate;
along the first direction, the height of the first part of the gate and the surface of the first step to the gate trench
The bottom parts of the first subsections are the same in length, and a first gap exists between one side, close to the first sub-side wall, of the first subsection of the grid electrode and the first sub-side wall along the second direction;
along the second direction, the second gate division extends to the surface of the first step, and a second gap exists between one side of the second gate division, which is close to the second sub-sidewall, and the second sub-sidewall.
4. The semiconductor device of claim 3, wherein the gate trench first section comprises an opening on a side away from the substrate;
along the second direction, the distance between one side of the opening close to the step structure and the first sub-side wall is L1, the extension length of the gate second subsection on the first-stage step surface is L2, and the extension length of the first gap is L3; wherein, L1 is more than L2, L1 is more than or equal to L3, L2 is less than 0.1 μm, and L1+ L2 is more than 0.5 μm.
5. The semiconductor device according to claim 3, wherein an extension length L4 of the second gap satisfies L4 ≦ 0.5 μm in the second direction.
6. The semiconductor device according to claim 3, wherein along the first direction, an extension height L5 of the first sub-sidewall satisfies L5>0.1 μm.
7. The semiconductor device of claim 1, wherein the multilayer semiconductor layer comprises a barrier layer on a side remote from the substrate, the gate trench first partition being located in the barrier layer;
the first gate groove part comprises a third side wall, a fourth side wall and a bottom surface connecting the third side wall and the fourth side wall, and the bottom surface is parallel to the plane of the substrate;
the extension length L6 of the bottom surface along the second direction satisfies L6 ≤ 0.25 μm;
along the first direction, the distance L7 between the bottom surface and the surface of the barrier layer close to the substrate side satisfies L7 ≧ 15 nm.
8. The semiconductor device according to claim 7, wherein an angle θ between the third side wall and/or the fourth side wall and the bottom surface satisfies 90 ° ≦ θ ≦ 135 °.
9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, comprising:
providing a substrate;
preparing a multilayer semiconductor layer on one side of the substrate, and preparing a first subsection of a grid groove on one side, far away from the substrate, of the multilayer semiconductor layer;
preparing a dielectric layer on the surface of one side of the multilayer semiconductor layer, which is far away from the substrate, and in the first subsection of the grid groove;
preparing a second subsection of a grid groove penetrating through the dielectric layer in the dielectric layer, wherein the second subsection of the grid groove and the first subsection of the grid groove form a grid groove; the second gate trench part comprises a first side wall and a second side wall, the first side wall and/or the second side wall is/are provided with at least one step structure, the at least one step structure comprises an ith step, the ith step comprises an ith sub-side wall, an i +1 th sub-side wall and an ith step surface connecting the ith sub-side wall and the i +1 th sub-side wall, the i +1 th sub-side wall is positioned on one side of the ith sub-side wall, which is far away from the substrate, wherein i is more than or equal to 1, and i is an integer;
preparing a grid electrode in the grid electrode groove, and preparing a source electrode and a drain electrode on one side of the multilayer semiconductor layer far away from the substrate, wherein the grid electrode is positioned between the source electrode and the drain electrode; the grid electrode comprises a grid electrode first subsection and a grid electrode second subsection which are connected with each other, the grid electrode first subsection fills the grid electrode groove first subsection and is partially positioned in the grid electrode groove second subsection, the grid electrode second subsection is positioned on one side, far away from the substrate, of the grid electrode first subsection and is positioned in the grid electrode groove second subsection, a vertical projection of the grid electrode second subsection in a plane of the substrate covers a vertical projection of the grid electrode first subsection in the plane of the substrate, and the coverage area of the grid electrode second subsection is larger than that of the grid electrode first subsection; the height of the first gate subsection is the same as the length from the surface of the ith step to the bottom of the first gate trench subsection along the first direction, and a first gap exists between one side, close to the ith sub-side wall, of the first gate subsection and the ith sub-side wall along the second direction; along the second direction, the second gate part extends to the surface of the ith step; the first direction is perpendicular to the direction in which the source points to the drain, and the second direction is perpendicular to the first direction.
10. The method according to claim 9, wherein the first side wall and/or the second side wall is formed with a first step structure comprising a first sub-side wall, a second sub-side wall, and a first step surface connecting the first sub-side wall and the second sub-side wall, the second sub-side wall being located on a side of the first sub-side wall remote from the substrate;
preparing a second subsection of the gate trench in the dielectric layer, the second subsection penetrating through the dielectric layer, comprising:
coating a first photoresist on the surface of one side, far away from the substrate, of the dielectric layer, and removing the dielectric layer above and in the first part of the grid groove through a first etching process after exposure and development;
coating a second photoresist on the surface of one side, far away from the substrate, of the dielectric layer, wherein the second photoresist exposes a part of the dielectric layer, close to the source electrode and/or the drain electrode, of the first part of the grid groove;
performing a second etching process on the dielectric layer exposed by the second photoresist, and forming a first initial step structure on the first part of the gate trench close to one side of the source electrode and/or the drain electrode;
coating third photoresist on the surface of one side, far away from the substrate, of the dielectric layer and the surface of one side, far away from the substrate, of the first initial step structure, wherein the third photoresist exposes a part of the first initial step structure, close to the source electrode and/or the drain electrode, of the first part of the grid groove;
and carrying out a third etching process on the first initial step structure exposed by the third photoresist to expose the multilayer semiconductor layer at the side of the first part of the grid groove close to the source electrode and/or the drain electrode, and forming a first step structure in the dielectric layer.
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CN1960002A (en) * 2005-11-03 2007-05-09 韩国电子通信研究院 Field effect transistor and method for manufacturing the same
CN106601808A (en) * 2016-12-19 2017-04-26 苏州捷芯威半导体有限公司 Semiconductor device and preparation method thereof

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