CN106298882A - HEMT devices and manufacture method thereof - Google Patents
HEMT devices and manufacture method thereof Download PDFInfo
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- CN106298882A CN106298882A CN201610632720.9A CN201610632720A CN106298882A CN 106298882 A CN106298882 A CN 106298882A CN 201610632720 A CN201610632720 A CN 201610632720A CN 106298882 A CN106298882 A CN 106298882A
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- 239000010410 layer Substances 0.000 description 190
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 21
- 229910002601 GaN Inorganic materials 0.000 description 20
- 230000004888 barrier function Effects 0.000 description 17
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
A kind of HEMT devices, relate to technical field of semiconductors, the first medium layer of this device is positioned at grid and source electrode, on semiconductor layer between drain electrode, on first source field plate first medium layer between grid and drain electrode, second dielectric layer is positioned at grid, on first source field plate and first medium layer, second source field plate is positioned at grid, in second dielectric layer on first source field plate, first source field plate and the second source field plate weaken the region highfield between grid and drain electrode near grid, first medium layer and second dielectric layer are at long-time stress, it is not susceptible to dielectric layer under high voltage stress lost efficacy.This device can weaken the highfield existed between grid and drain electrode near area of grid, can reduce again the probability that the dielectric layer between grid and source field plate occurs to lose efficacy.The present invention also provides for the manufacture method of a kind of HEMT devices, and technological process is simple, and the device reliability prepared is high.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of HEMT devices and
Manufacture method.
Background technology
The dielectric breakdown field of third generation semiconductor gallium nitride (GaN) is significantly larger than first generation semiconductor silicon (Si) or second
For the dielectric breakdown field of Semiconductor GaAs (GaAs), its value is up to 3MV/cm, makes this electronic device can bear the highest electricity
Pressure.Meanwhile, gallium nitride can form hetero-junctions knot with other gallium compounds quasiconductors (such as, III nitride semiconductor)
Structure.Owing to III nitride semiconductor has strong piezoelectricity and spontaneous polarization effect, it is attached at the interface of hetero-junctions
Closely, electron concentration the highest two-dimensional electron gas (2DEG) raceway groove can be formed, and this heterojunction structure also can effectively reduce
Ionized impurity scattering, therefore the electron mobility in raceway groove is greatly promoted.The GaN made on the basis of this heterojunction structure
HEMT can turn on high electric current in altofrequency, and has the lowest conducting resistance.Above-mentioned characteristic makes GaN HEMT be particularly well-suited to
Manufacture high-frequency high-power radio-frequency devices and the switching device of the pressure big electric current of height.
Generally in GaN HEMT, between grid and drain electrode, bear higher voltage, cause between grid and drain electrode close
There is highfield in the region of grid, highfield herein causes the current collapse effect of this electronic device.Current collapse effect table
It is now: electric current density is much smaller than electric current density during device stable state in high frequency.Occur that current collapse effect makes device performance move back
Changing, output power density, power added efficiency etc. reduce, and seriously constrain the device application when high-frequency and high-voltage is high-power.Right
For gallium, it often to work under hyperfrequency and high voltage environment, therefore imitates current collapse
The control answered requires more strict, and the source field plate techniques of employing is the means weakening the highfield that drain electrode exists near area of grid
One of.
Use Conventional source field plate techniques process after HEMT 002 cross section structure as it is shown in figure 1,
HEMT 002 includes: substrate 210, the semiconductor layer 220 being positioned on substrate, is positioned on semiconductor layer 220
Source electrode 231, drain electrode 233 and T-shaped grid 232, be positioned at the dielectric layer 010 on T-shaped grid 232, semiconductor layer 220, and be positioned at
On dielectric layer 010, and it is positioned at the source field plate 020 above T-shaped grid 232.Wherein, source field plate 020 at active area outer and source electrode 231
It is electrically connected, i.e. source field plate 020 and source electrode 231 isoelectric level；Semiconductor layer 220 includes the cushion set gradually from the bottom to top
221, channel layer 222 and barrier layer 223.Source field plate 020 can weaken between T-shaped grid 232 and drain electrode 233 near T-shaped grid
The highfield peak value that the region of 232 exists, reaches to suppress current collapse, improves output power density and the mesh of power added efficiency
's.
But, in the HEMT 002 after the process of above-mentioned use conventional source field plate techniques, dielectric layer 010
Lateral edges at T-shaped grid 232 forms step 030, and the dielectric layer 010 of step 030 (step 030 sidewall) in the y-direction is at material
Thickness, quality of materials aspect are all not as good as the dielectric layer 010 of (step 030 plane) in the x-direction.HEMT 002
When working under long-time stress, high voltage stress, between T-shaped grid 232 and source field plate 020, there is long high electric field,
Dielectric layer 010 on step 030 sidewall was easily lost efficacy, thus causes between T-shaped grid 232 and source field plate 020 short
Road, and then reduce the reliability of HEMT 002.
In view of the HEMT of above-mentioned use Conventional source field plate techniques, exist because the dielectric layer between grid and source field plate lost efficacy
And cause the problem that device reliability reduces, it is necessary to HEMT and the manufacture method thereof of a kind of high reliability are provided.
Summary of the invention
It is an object of the invention to provide a kind of HEMT devices, it can weaken grid and drain electrode
Between the highfield that exists near area of grid, the probability that dielectric layer between grid and source field plate occurs to lose efficacy can be reduced again, from
And improve the reliability of device.
Another object of the present invention is to provide the manufacture method of a kind of HEMT devices, manufacturing process
Flow process is simple, and the device reliability prepared is high.
Embodiments of the invention are achieved in that
A kind of HEMT devices, comprising:
Substrate；
Semiconductor layer, is positioned on substrate；
Grid, source electrode and drain electrode, be positioned on semiconductor layer, and grid is between source electrode and drain electrode；
First medium layer, on the semiconductor layer between grid and source electrode, grid and drain electrode；
First source field plate, on the first medium layer between grid and drain electrode；
Second dielectric layer, is positioned on first medium layer, and covers grid, the first source field plate；And
Second source field plate, is positioned in second dielectric layer, and is positioned at grid, the top of the first source field plate, wherein, and source electrode,
One source field plate and the second source field plate isoelectric level.
In preferred embodiment of the present invention, above-mentioned second source field plate is also located on source electrode, and the second source field plate is with source electrode even
Connect.
In preferred embodiment of the present invention, above-mentioned second dielectric layer is provided with through hole to expose the first source field plate, the second source
Field plate is connected by through hole and the first source field plate.
In preferred embodiment of the present invention, between above-mentioned grid and the first source field plate, there is also air dielectric.
In preferred embodiment of the present invention, the minimum distance between above-mentioned grid and the first source field plate is more than at least 2 times
The thickness of second dielectric layer.
In preferred embodiment of the present invention, the thickness of above-mentioned second dielectric layer is more than 200nm, grid and the first source field plate
Between minimum distance more than 400nm.
A kind of manufacture method of HEMT devices, including:
Substrate is formed semiconductor layer；
Form first medium layer on the semiconductor layer；
First medium layer is formed source electrode and drain electrode；
Forming grid, the first source field plate between source electrode and drain electrode, the first source field plate is between grid and drain electrode；
First medium layer is formed second dielectric layer and covers grid and the first source field plate；And
Forming the second source field plate in second dielectric layer, the second source field plate is positioned at grid, the top of the first source field plate, and makes
Obtain source electrode, the first source field plate and the second source field plate isoelectric level.
In preferred embodiment of the present invention, above-mentioned first source field plate and grid are formed in same step.
In preferred embodiment of the present invention, after forming second dielectric layer, before forming the second source field plate, first it is being positioned at
Second dielectric layer on first source field plate opens hole, then forms the second source field plate, and makes the second source field plate through through hole and first
Source field plate connects.
In preferred embodiment of the present invention, when forming the second source field plate, make the second source field plate extend on source electrode with source
Pole connects.
The embodiment of the present invention provides the benefit that: the first medium layer of the embodiment of the present invention is positioned at grid and source electrode, drain electrode
Between semiconductor layer on, on first source field plate first medium layer between grid and drain electrode, second dielectric layer is positioned at the
On one dielectric layer, and covering grid and the first source field plate, the second source field plate is positioned in second dielectric layer, and is positioned at grid and first
Above the field plate of source, the first source field plate and the second source field plate with the use of, reach to weaken the district near grid between grid and drain electrode
The effect of territory highfield, and first medium layer and second dielectric layer are not susceptible to be situated between under long-time stress, high voltage stress
The phenomenon that matter layer lost efficacy.Therefore, the embodiment of the present invention can weaken the forceful electric power existed between grid and drain electrode near area of grid
, the probability that the dielectric layer between grid and source field plate occurs to lose efficacy can be reduced again, thus improve the reliability of device；And it is high
The manufacturing approach craft flow process of electron mobility transistor components is simple, and the device reliability prepared is high.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below by embodiment required use attached
Figure is briefly described, it will be appreciated that the following drawings illustrate only certain embodiments of the present invention, and it is right to be therefore not construed as
The restriction of scope, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to according to this
A little accompanying drawings obtain other relevant accompanying drawings.
Fig. 1 is the structural representation of a kind of HEMT；
A kind of HEMT devices that Fig. 2 A-2G provides for first embodiment of the invention is in the fabrication process
Structural representation；
The structural representation of a kind of HEMT devices that Fig. 3 provides for second embodiment of the invention；
The structural representation of a kind of HEMT devices that Fig. 4 provides for third embodiment of the invention；
The structural representation of a kind of HEMT devices that Fig. 5 provides for fourth embodiment of the invention.
In figure:
002-HEMT, 210-substrate, 220-semiconductor layer, 221-cushion, 222-channel layer,
223-barrier layer, 231-source electrode, 232-T type grid, 233-drains, 010-dielectric layer, 020-source field plate, 030-step；
100,200,300,400-HEMT devices；110-substrate, 120-semiconductor layer, 121-buffers
Layer, 122-channel layer, 123-barrier layer, 131-source electrode, 132-grid, 133-drains, and 141-first medium layer, 142-second is situated between
Matter layer, 143-air dielectric, 151-the first source field plate, 152,252,352,452-the second source field plate, 160-grid groove, 170-lead to
Hole.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Generally implement with the present invention illustrated described in accompanying drawing herein
The assembly of example can be arranged with various different configurations and design.
Therefore, detailed description to the embodiments of the invention provided in the accompanying drawings is not intended to limit claimed below
The scope of the present invention, but be merely representative of the selected embodiment of the present invention.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under not making creative work premise, broadly falls into the model of present invention protection
Enclose.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.
In describing the invention, it should be noted that term " on ", D score, " interior ", the orientation of the instruction such as " outward " or position
Relation of putting is for based on orientation shown in the drawings or position relationship, or the orientation usually put when this invention product uses or position
Put relation, be for only for ease of the description present invention and simplify description rather than instruction or imply that the device of indication or element are necessary
There is specific orientation, with specific azimuth configuration and operation, be therefore not considered as limiting the invention.
In describing the invention, in addition it is also necessary to explanation, unless otherwise clearly defined and limited, term " arrange ",
" connect " and should be interpreted broadly, connect for example, it may be fixing, it is also possible to be to removably connect, or be integrally connected；Can be
It is mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, can be two
The connection of element internal.For the ordinary skill in the art, can understand that above-mentioned term is in the present invention with concrete condition
In concrete meaning.
First embodiment
With reference to shown in Fig. 2, the present embodiment provides a kind of HEMT devices 100, comprising: substrate 110,
Semiconductor layer 120, grid 132, source electrode 131, drain electrode 133, first medium layer the 141, first source field plate 151, second dielectric layer
142, the second source field plate 152, wherein, source electrode the 131, first source field plate 151 and the second source field plate 152 isoelectric level.Semiconductor layer 120
It is positioned on substrate 110, is particularly located at the upper surface of substrate 110；Grid 132, source electrode 131 and drain electrode 133 are positioned at semiconductor layer 120
On, grid 132 is between source electrode 131 and drain electrode 133.In the present embodiment, source electrode 131, drain electrode 133 are respectively positioned on semiconductor layer
The upper surface of 120, and contact with semiconductor layer 120, the bottom of grid 132 embeds in semiconductor layer 120.First medium layer 141
On semiconductor layer 120 between grid 132 and source electrode 131, grid 132 and drain electrode 133, it is particularly located at this semiconductor layer
The upper surface of 120.On the first source field plate 151 first medium layer 141 between grid 132 and drain electrode 133, it is particularly located at the
The upper surface of one dielectric layer 141.Second dielectric layer 142 is positioned on first medium layer 141, and covers grid 132 and the first field, source
Plate 151.Second source field plate 152 is positioned in second dielectric layer 142, is particularly located at the upper surface of this second dielectric layer 142, and is positioned at
The top of grid the 132, first source field plate 151.In the present embodiment, the second source field plate 152 also lies along the upper table of source electrode 131
Face, and contact electrical connection with source electrode 131.Additionally, the first source field plate 151 electrically connects outside active area with source electrode 131, to realize source
Pole the 131, first source field plate 151 and the second source field plate 152 isoelectric level.Grid 132 is T-shaped grid, grid 132 and the first source field plate
Air dielectric 143 is there is also between 151.
Wherein, the material of substrate 110 can be sapphire, carborundum, silicon, Lithium metaniobate, silicon-on-insulator, gallium nitride, nitrogen
Change aluminum or the material of any other applicable growing gallium nitride well known to those skilled in the art.In the present embodiment, substrate 110
Material be sapphire.
Semiconductor layer 120 starts to include successively from the upper surface of substrate 110: be positioned at the cushion of the upper surface of substrate 110
121, the channel layer 122 being positioned at the upper surface of cushion 121 and the barrier layer 123 of the upper surface being positioned at channel layer 122.
Wherein, cushion 121 plays the effect of bonding next other semiconductor layers of growth, specifically at the bottom of adhesive lining
110 and channel layer 122, substrate 110 can be protected again will not to be invaded by some metal ions.In the present embodiment, cushion 121 is
Gallium nitride layer (Al) GaN that aluminum content is controlled.Channel layer 122 is for providing the raceway groove of carrier moving.Channel layer 122 can be non-
One or more in GaN, AlxGa1-xN, InxAl1-xN or AlN of doping GaN, N-shaped doping or the doping of N-shaped local, 0 ＜ x
＜ 1.Barrier layer 123 is for supplying carrier in channel layer 122, and plays the effect of potential barrier, stops the load in channel layer 122
Stream subflow is to barrier layer 123.Barrier layer 123 is one or more in AlxGa1-xN, InxAl1-xN or AlN, 0 ＜ x ＜ 1.
Channel layer 122 forms heterojunction structure together with barrier layer 123 above, and the energy gap of channel layer 122 is less than potential barrier
The energy gap of layer 123, produces at the interface of barrier layer 123 and channel layer 122 and can bend by band, and being formed in interface can only two dimension
The carrier layer that the carrier of movement is formed, i.e. two-dimensional electron gas (2DEG).Source electrode 131, drain electrode 133 all with semiconductor layer 120
In 2DEG formed electrical connection.
First medium layer 141, second dielectric layer 142 can be the crystalline materials of deposition in growth or technical process, as
GaN or AlN etc., it is also possible to be the amorphous material of deposition in growth or technical process, such as SiN etc., in the present embodiment,
First medium layer 141 is amorphous material SiN.First medium layer 141 both can be passivated device surface, reduces or eliminates common
The current collapse effect of GaN HEMT, can assist again formation grid 132.
Barrier layer 123 surface electric field distribution in semiconductor layer 120 can be adjusted by the first source field plate 151, and then
Improve the breakdown voltage of device.Minimum distance between grid 132 and the first source field plate 151 (is grid 132 near drain electrode
One lateral edges of 133 and the first source field plate 151 distance between a lateral edges of grid 132) need to more than at least 2 times the
The thickness of second medium layer 142.In the present embodiment, the minimum distance between grid 132 and the first source field plate 151 more than 2 times the
The thickness of second medium layer 142, the thickness of second dielectric layer 142 is more than 200nm, between grid 132 and the first source field plate 151
Closely more than 400nm, can avoid the second dielectric layer 142 between grid 132 and the first source field plate 151 not because it is of poor quality,
Thickness is thin and loses efficacy.Meanwhile, thickness of dielectric layers (the first medium layer 141 and second between grid 132 and the first source field plate 151
The superposition thickness of dielectric layer 142) twice of single-layer medium layer thickness that is about in common GaN HEMT, and grid 132 and first
Certain thickness air dielectric 143, the therefore grid 132 in the present embodiment and the first source field plate is there is also between source field plate 151
Dielectric layer between 151 is not susceptible to the phenomenon lost efficacy under long-time stress, high voltage stress.And, the first source field plate 151
Material identical with the material of grid 132, it is simple in same step formed, it is to avoid increase the complexity of whole technological process.
Second source field plate 152 can weaken the highfield existed between grid 132 and drain electrode 133 near the region of grid 132,
And then improve the breakdown voltage of the present embodiment HEMT devices 100.And, grid 132 and the second source field plate
Dielectric layer between 152, identical with the dielectric layer between grid 132 and the first source field plate 151, there is also first medium layer 141,
Second dielectric layer 142 and air dielectric 143, this dielectric film quality is good, thickness is big, therefore the grid 132 in the present embodiment and the
Between two source field plates 152, dielectric layer is not susceptible to the phenomenon that dielectric layer lost efficacy under long-time stress, high voltage stress.
Therefore, the first source field plate 151 and the second source field plate 152 with the use of, can reach weakening grid 132 and drain electrode 133
Between near the effect of region highfield of grid 132.Meanwhile, dielectric layer between grid 132 and the first source field plate 151, grid
What 132 and second dielectric layers between source field plate 152 were not susceptible under long-time stress, high voltage stress that dielectric layer lost efficacy shows
As.
With reference to shown in Fig. 2 A to Fig. 2 G, the present embodiment provides the manufacture method of HEMT devices 100, bag
Include following steps:
S1: provide substrate 110, on a substrate 110 formed semiconductor layer 120, specifically substrate 110 upper surface successively
Form cushion 121, channel layer 122, barrier layer 123, as shown in Figure 2 A.
Wherein, the material of substrate 110 can be sapphire, carborundum, silicon, Lithium metaniobate, silicon-on-insulator, gallium nitride, nitrogen
Change aluminum or the material of any other applicable growing gallium nitride well known to those skilled in the art.The deposition process of substrate 110
Including chemical gaseous phase deposition (Chemical Vapor Deposition, CVD), vapour phase epitaxy (Vapor Phase Epitaxy,
VPE), metallo-organic compound chemical gaseous phase deposition (Metal-organic Chemical Vapor Deposition,
MOCVD), low-pressure chemical vapour deposition technique (Low Pressure Chemical Vapor Deposition, LPCVD), etc.
Gas ions strengthens chemical vapour deposition technique (Plasma Enhanced Chemical Vapor Deposition, PECVD), arteries and veins
Impulse light deposition (Pulsed Laser Deposition, PLD), atomic layer epitaxy, molecular beam epitaxy (Molecular Beam
Epitaxy, MBE), sputter, evaporation etc..In the present embodiment, the material of substrate 110 is sapphire.
Cushion 121 is gallium nitride layer (Al) GaN that aluminum content is controlled, plays at the bottom of adhesive lining 110 and the work of channel layer 122
With, substrate 110 can be protected again will not to be invaded by some metal ions；The GaN of the most involuntary doping of channel layer 122, ditch
Channel layer 122 provides the raceway groove of carrier moving.The AlGaN of the most involuntary doping of barrier layer 123, barrier layer 123 plays gesture
The effect built, stops that the carrier in channel layer 122 flows to barrier layer 123.Channel layer 122 and barrier layer 123 above
Forming heterojunction structure together, the energy gap of channel layer 122 is less than the energy gap of barrier layer 123, at barrier layer 123 and ditch
The interface of channel layer 122 produce can band bending, formed in interface can only the carrier layer that formed of the carrier of two-dimensional movement, i.e. two
Dimensional electron gas (2DEG).
The upper surface of S2: on semiconductor layer 120, specifically semiconductor layer 120 forms first medium layer 141, such as Fig. 2 B
Shown in.
First medium layer 141 can be formed by various ways, such as metallo-organic compound chemical gaseous phase deposition (Metal-
Organic Chemical Vapor Deposition, MOCVD), plasma enhanced chemical vapor deposition method (Plasma
Enhanced Chemical Vapor Deposition, PECVD), ald (Atomic layer deposition,
ALD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE) and thermally grown etc., but it is not limited to this method, the present embodiment
In, use MOCVD to form first medium layer 141.
First medium layer 141 can be the crystalline material of deposition in growth or technical process, such as GaN or AlN etc., it is possible to
To be the amorphous material of deposition in growth or technical process, such as SiN etc., in the present embodiment, first medium layer 141 is non-
Crystalline material SiN.
S3: form source electrode 131 and drain electrode 133 on first medium layer 141, and source electrode 131, drain electrode 133 are all and quasiconductors
2DEG in layer 120 forms electrical connection, as shown in Figure 2 C.
The mode that source electrode 131, drain electrode 133 electrically connect with the 2DEG formation in semiconductor layer 120 can use but not limit to
Formed in the following manner: a. high annealing；B. ion implanting；C. heavy doping.Source electrode 131 and drain electrode is formed carrying out high annealing
When 133, source electrode 131 with drain electrode 133 electrode metal all contact with semiconductor layer 120, thus realize source electrode 131, drain 133 and
2DEG in semiconductor layer 120 forms electrical connection.When carrying out ion implanting or heavy doping forms source electrode 131 and drain electrode 133, source
Pole 131 and drain electrode 133 are made up of ion implanting part or heavy doping part and electrode thereon, ion implanting part or heavy doping
Part is formed with the 2DEG in semiconductor layer 120 and electrically connects.
In the present embodiment, using high-temperature annealing process to form source electrode 131, drain electrode 133, source electrode 131, drain electrode 133 are all with half
Conductor layer 120 contacts, and detailed process is: first deposit multiple layer metal, modal situation for deposit Ti/Al/Ni/Au (from lower to
On) 4 layers of metal, then carry out rapid thermal annealing (RTA) technique, form ohm property.The meaning of RTA technique is: on the one hand exist
Semiconductor layer 120 (metal semiconductor interface) forms low resistance nitride, on the other hand makes 4 layers of intermetallic phase counterdiffusion, sends out
Raw solid phase interface reaction, forms the intermetallic alloy of a series of low resistance, low work function and Heat stability is good, is source electrode 131
With drain electrode 133.
S4: formed by etching technics first medium layer 141 between source 131 and drain 133 and be used for being subsequently formed
The grid groove 160 of grid 132, as shown in Figure 2 D.
Etching technics is wet-etching technology or dry etch process, uses wet-etching technology or dry etching work
When first medium layer 141 is performed etching by skill, different etching depths can be by controlling etching technics time, etching technics speed
Realize.When the etching depth of grid groove 160 exceedes the thickness of first medium layer 141, grid groove 160 passes first medium layer 141,
Extending in half dielectric layer, the grid 132 and the semiconductor layer 120 that are subsequently formed form Schottky contacts；Etching when grid groove 160
When the degree of depth is not less than the thickness of first medium layer 141, grid groove 160 is only located in first medium layer 141, the grid being subsequently formed
132 form metal (grid 132)-insulating barrier (first medium layer 141)-semiconductor structure (semiconductor layer with semiconductor layer 120
120).In the present embodiment, the etching depth of grid groove 160 exceedes the thickness of first medium layer 141, and grid groove 160 is through first medium
Layer 141, extends in barrier layer 123, and the grid 132 and the semiconductor layer 120 that are subsequently formed form Schottky contacts.
S5: in same step process, deposits metal in grid exposure area and the first field plate exposure area, source simultaneously, with same
Time form grid 132 and the first source field plate 151, as shown in Figure 2 E.The specifically metal at deposit grid forms the same of grid 132
Time, deposit the first source field plate 151 that the metal of the first source field plate 151 is formed.This formation grid in same step process flow process
132 and first technique of source field plate 151, compared with the field plate techniques of existing source, the formation of the first source field plate 151 only needs at grid
Pole level reticle increases an exposure area (the first field plate exposure area, source) between grid 132 and drain electrode 133,
Other techniques, reticle quantity will not be increased, thus without the complexity increasing whole technological process.
Ni/Au metal system is the metal that the Schottky gate of current HEMT is the most frequently used, the present embodiment
In, the metal of grid 132 is Ni/Au metal system, the edge of close drain electrode 133 sides, grid exposure area and the first source field plate
Exposure area distance between the edge of side, grid exposure area is more than 400nm, the grid 132 i.e. formed and formation
Minimum distance between first source field plate 151 is more than 400nm.
S6: form second dielectric layer 142 on first medium layer 141, and cover grid the 132, first source field plate 151 and the
One dielectric layer 141, as shown in Figure 2 F.
Second dielectric layer 142 can be formed by various ways, such as MOCVD, and PECVD, ALD, MBE and thermally grown etc., but not office
It is limited to this method.Second dielectric layer 142 can be the crystalline material of deposition in growth or technical process, such as GaN or AlN etc., also
Can be the amorphous material of deposition in growth or technical process, such as SiN etc., in the present embodiment, use PECVD technique,
Forming second dielectric layer 142 with amorphous material SiN, the thickness of second dielectric layer 142 is more than 200nm.
S7: in second dielectric layer 142, the specifically upper surface of second dielectric layer 142 form the second source field plate 152, the
Two field, source 152 plates are positioned at the top of grid the 132, first source field plate 151, and the second source field plate 152 also lies along the upper of source electrode 131
Surface is connected (the i.e. second source field plate 152 and source electrode 131 isoelectric level) with source electrode 131, meanwhile, is formed outside device active region
The electrical connection (the i.e. first source field plate 151 and source electrode 131 isoelectric level) of the first source field plate 151 and source electrode 131, to ensure to realize source electrode
131, the first source field plate 151 and the second source field plate 152 isoelectric level, as shown in Figure 2 G.
Second embodiment
Refer to Fig. 3, the present embodiment provides a kind of HEMT devices 200, and it carries with first embodiment
The structure of the HEMT devices 100 of confession is roughly the same, and the second source field plate 152 contacts with source electrode 131 and (is electrically connected
Connect), the difference of the two is: in the present embodiment, and the second dielectric layer 142 on the first source field plate 151 is provided with through hole 170, second
What source field plate 252 was positioned on the first source field plate 151 partially pass through through hole 170 contacts with the first source field plate 151, the i.e. second source field plate
252 electrically connect with the first source field plate 151, to realize source electrode the 131, first source field plate 151 and the second source field plate 152 isoelectric level.
The first source field plate in the first source field plate 151 in the present embodiment and the second source field plate 252 and the first embodiment
151, the second source field plate 152 serves the same role, and weakening, the region of close grid 132 between grid 132 and drain electrode 133 is strong
While electric field, the dielectric layer between grid 132 and source field plate (first source field plate the 151, second source field plate 152) for a long time should
The phenomenon that dielectric layer lost efficacy it is not susceptible under power, high voltage stress.Compared to the high electron mobility crystal in first embodiment
Tube device 100, the HEMT devices 200 of the present embodiment decreases the metal layout outside active area, specifically
First source field plate 151 and the source electrode 131 electrical connection outside active area, therefore structural integrity is strong.
The manufacture method of the HEMT devices 200 of the present embodiment and the manufacturer in the first embodiment
Method is roughly the same, does not repeats them here.Wherein, first second dielectric layer 142 is deposited on whole device, i.e. second dielectric layer
142 cover source electrode 131, drain electrode 133, grid 132 and the first source field plate 151, in order to make source electrode 131 and drain electrode 133 formation metal
Interconnection, needs perforate to etch away the second dielectric layer 142 covered in source electrode 131, drain electrode 133.The manufacture method of the present embodiment with
The difference of the manufacture method in the first embodiment is, the HEMT devices 200 of the present embodiment
In manufacture method, after forming second dielectric layer 142, before forming the second source field plate 252, also want first be positioned at the first source field plate
Second dielectric layer 142 on 151 opens hole 170, then forms the second source field plate 252, and makes the second source field plate 252 through through hole
170 electrically connect with the first source field plate 151.And the hole opening technology of the second dielectric layer 142 on the first source field plate 151 can with
The perforate etching technics of the second dielectric layer 142 in source electrode 131, drain electrode 133 synchronously completes.With existing source field plate techniques phase
Ratio, will not increase the complexity of whole technological process.
3rd embodiment
Refer to Fig. 4, the present embodiment provides a kind of HEMT devices 300, and it carries with first embodiment
The structure of the HEMT devices 100 of confession is roughly the same, and the first source field plate 151 and source electrode 131 are outside active area
Electrical connection, the difference of the two is: in the present embodiment, and the second source field plate 352 is only located on grid the 132, first source field plate 151
In second dielectric layer 142, and electrically connect outside the second source field plate 352 and active area, to realize source electrode the 131, first source field plate 151 and
Second source field plate 352 isoelectric level.
First source field plate 151 and the second source field plate 352 of the present embodiment are weakening grid 132 and are draining close between 133
While the region highfield of grid 132, HEMT is difficult to again lose efficacy.And compared with first embodiment, shorten the second source field plate
The length of 352, can play the effect reducing gate-source capacitance Cgs, thus increase the frequency characteristic of HEMT.
The manufacture method of the HEMT devices 300 of the present embodiment and the manufacturer in the first embodiment
Method is roughly the same, does not repeats them here.Difference is: the second field plate exposure area, source in the present embodiment need to foreshorten to grid
Above in the of 132.
4th embodiment
Refer to Fig. 5, the present embodiment provides a kind of HEMT devices 400, and it carries with the 3rd embodiment
The structure of the HEMT devices 300 of confession is roughly the same, and the second source field plate 452 and source electrode 131 are outside active area
Electrical connection, the difference of the two is: in the present embodiment, and the second dielectric layer 142 on the first source field plate 151 is provided with through hole 170, the
What two source field plates 452 were positioned on the first source field plate 151 partially pass through through hole 170 contacts with the first source field plate 151, the i.e. second field, source
Plate 452 electrically connects with the first source field plate 151, to realize the electricity such as source electrode the 131, first source field plate 151 and the second source field plate 452 formation
Position.
The manufacture method of the HEMT devices 400 of the present embodiment and the manufacturer in the 3rd embodiment
Method is roughly the same, does not repeats them here.Difference is: in the manufacture method of the HEMT device of the present embodiment,
Before forming the second source field plate 452, first open hole 170 in the second dielectric layer 142 being positioned on the first source field plate 151, then formed
Second source field plate 452, the second source field plate 452 electrically connects through through hole 170 with the first source field plate 151.With existing source field plate skill
Art is compared, and will not increase the complexity of whole technological process.
In sum, the HEMT devices of the present invention can weaken between grid and drain electrode near grid
The highfield that region exists, can reduce again the probability that the dielectric layer between grid and source field plate occurs to lose efficacy, thus improve device
Reliability；And the manufacturing approach craft flow process of HEMT devices is simple, the device reliability prepared is high.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, that is made any repaiies
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (10)
1. a HEMT devices, it is characterised in that comprising:
Substrate；
Semiconductor layer, is positioned on described substrate；
Grid, source electrode and drain electrode, be positioned on described semiconductor layer, and described grid is between described source electrode and described drain electrode；
First medium layer, on the described semiconductor layer between described grid and described source electrode, described grid and described drain electrode；
First source field plate, on the described first medium layer between described grid and described drain electrode；
Second dielectric layer, is positioned on described first medium layer, and covers described grid, described first source field plate；And
Second source field plate, is positioned in described second dielectric layer, and is positioned at described grid, the top of described first source field plate, wherein,
Described source electrode, described first source field plate and described second source field plate isoelectric level.
HEMT devices the most according to claim 1, it is characterised in that described second source field plate also position
On described source electrode, described second source field plate is connected with described source electrode.
HEMT devices the most according to claim 1 and 2, it is characterised in that described second dielectric layer
Being provided with through hole to expose described first source field plate, described second source field plate is connected with described first source field plate by described through hole.
HEMT devices the most according to claim 1, it is characterised in that described grid and described first
Air dielectric is there is also between the field plate of source.
HEMT devices the most according to claim 1, it is characterised in that described grid and described first
The thickness of the described second dielectric layer more than at least 2 times of the minimum distance between the field plate of source.
HEMT devices the most according to claim 5, it is characterised in that the institute of described second dielectric layer
State thickness and be more than 400nm more than 200nm, the described minimum distance between described grid and described first source field plate.
7. the manufacture method of a HEMT devices as claimed in claim 1, it is characterised in that including:
Substrate is formed semiconductor layer；
Described semiconductor layer is formed first medium layer；
Described first medium layer is formed source electrode and drain electrode；
Between described source electrode and described drain electrode formed grid, the first source field plate, described first source field plate be positioned at described grid and
Between described drain electrode；
Described first medium layer is formed second dielectric layer and covers described grid and described first source field plate；And
Forming the second source field plate in described second dielectric layer, described second source field plate is positioned at described grid, described first field, source
The top of plate, and make described source electrode, described first source field plate and described second source field plate isoelectric level.
The manufacture method of HEMT devices the most according to claim 7, it is characterised in that described first
Source field plate and described grid are formed in same step.
The manufacture method of HEMT devices the most according to claim 7, it is characterised in that formed described
After second dielectric layer, before forming described second source field plate, first at the described second medium being positioned on described first source field plate
Layer opens hole, then forms described second source field plate, and makes described second source field plate through described through hole and described first source field plate
Connect.
The manufacture method of HEMT devices the most according to claim 7, it is characterised in that form institute
When stating the second source field plate, described second source field plate is made to extend to be connected with described source electrode on described source electrode.
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Effective date of registration: 20200731 Address after: Room 802, 8 / F, North building, complex building, No. 1699, South Zuchongzhi Road, Yushan Town, Kunshan City, Suzhou City, Jiangsu Province Patentee after: Kunshan Industrial Research Institute Third Generation Semiconductor Research Institute Co., Ltd Address before: 215300, 18, Feng Feng Road, hi tech Zone, Kunshan, Jiangsu, Suzhou Patentee before: Suzhou Nexun High Energy Semiconductor Co.,Ltd. |