JP2003109972A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2003109972A
JP2003109972A JP2001302678A JP2001302678A JP2003109972A JP 2003109972 A JP2003109972 A JP 2003109972A JP 2001302678 A JP2001302678 A JP 2001302678A JP 2001302678 A JP2001302678 A JP 2001302678A JP 2003109972 A JP2003109972 A JP 2003109972A
Authority
JP
Japan
Prior art keywords
active layer
recess
thickness
gate electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001302678A
Other languages
Japanese (ja)
Inventor
Hisao Kawasaki
久夫 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001302678A priority Critical patent/JP2003109972A/en
Publication of JP2003109972A publication Critical patent/JP2003109972A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents a drop in breakdown strength between a gate electrode and a drain electrode. SOLUTION: The semiconductor device is provided with a semiconductor substrate 11 on which an active layer 12 is formed, an ohmic contact source electrode S formed on the active layer 12, a ohmic contact drain electrode D formed on the active layer, and a Schottky junction gate electrode G installed inside a recess 13 formed by digging the active layer. A groove 14 in a prescribed depth is formed on the active layer between the recess 13 and the drain electrode D.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は超高周波動作に適す
る半導体装置たとえば電界効果型トランジスタの高耐圧
化に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage of a semiconductor device suitable for ultrahigh frequency operation, for example, a field effect transistor.

【0002】[0002]

【従来の技術】従来の半導体装置について、超高周波信
号の増幅素子などに使用される電界効果型トランジスタ
を例にとり図4を参照して説明する。
2. Description of the Related Art A conventional semiconductor device will be described with reference to FIG. 4 by taking a field effect transistor used as an amplifying element for an ultra high frequency signal as an example.

【0003】半導体基板41上に能動層42が形成さ
れ、能動層32上にオーム性接触のソース電極Sおよび
ドレイン電極Dが形成されている。また、ソース電極S
とドレイン電極Dとの間に位置する能動層32上に、能
動層32の一部を掘り込んたリセス33が設けられ、リ
セス33内にショットキ接合のゲート電極Gが形成され
ている。
An active layer 42 is formed on a semiconductor substrate 41, and an ohmic contact source electrode S and a drain electrode D are formed on the active layer 32. In addition, the source electrode S
A recess 33, which is formed by cutting a part of the active layer 32, is provided on the active layer 32 located between the drain electrode D and the drain electrode D, and a Schottky junction gate electrode G is formed in the recess 33.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置たと
えば電界効果型トランジスタは高性能化が要求され、ソ
ース抵抗の低減などが求められている。ソース抵抗を低
減する方法として、たとえばソース電極とゲート電極と
の間隔を小さくする方法や能動層の厚さを厚くする方
法、能動層を高濃度にドーピングする方法などがある。
Conventional semiconductor devices, such as field effect transistors, are required to have higher performance and lower source resistance. Examples of methods for reducing the source resistance include a method of reducing the distance between the source electrode and the gate electrode, a method of increasing the thickness of the active layer, and a method of doping the active layer with a high concentration.

【0005】しかし、能動層を厚くする構造あるいは能
動層を高濃度化する構造は、ゲート電極とドレイン電極
間の耐圧が低下するという問題がある。
However, the structure of thickening the active layer or the structure of increasing the concentration of the active layer has a problem that the breakdown voltage between the gate electrode and the drain electrode is lowered.

【0006】本発明は、上記した欠点を解決し、ゲート
電極とドレイン電極間の耐圧の低下を防止した半導体装
置を提供することを目的とする。
It is an object of the present invention to solve the above-mentioned drawbacks and to provide a semiconductor device in which the breakdown voltage between the gate electrode and the drain electrode is prevented from lowering.

【0007】[0007]

【課題を解決するための手段】本発明は、能動層が形成
された半導体基板と、前記能動層上に設けられたオーム
性接触のソース電極と、前記能動層上に設けられたオー
ム性接触のドレイン電極と、前記能動層を掘り込んだリ
セス内に設けられたショットキ接合のゲート電極とを具
備した半導体装置において、前記リセスと前記ドレイン
電極との間の能動層上に所定深さの溝を設けたことを特
徴とする。
According to the present invention, there is provided a semiconductor substrate having an active layer formed thereon, an ohmic contact source electrode provided on the active layer, and an ohmic contact provided on the active layer. A drain electrode and a gate electrode of a Schottky junction provided in a recess in which the active layer is dug, a trench having a predetermined depth on the active layer between the recess and the drain electrode. Is provided.

【0008】[0008]

【発明の実施の形態】本発明の実施の形態について図1
を参照して説明する。符号11はGaAsなどの半導体
基板で、半導体基板11上に能動層12が設けられてい
る。また、能動層12上に、オーム性接触のソース電極
Sおよびドレイン電極Dが所定の間隔で設けられてい
る。ソース電極Sおよびドレイン電極D間に位置する能
動層12上に、能動層12の一部を所定深さに掘り込ん
で形成したリセス13が設けられ、リセス13内にショ
ットキ接合のゲート電極Gが設けられている。また、ゲ
ート電極Gが設けられたリセス13とドレイン電極Dと
の間の能動層12上の一部に所定深さの溝14が形成さ
れている。
BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 shows an embodiment of the present invention.
Will be described with reference to. Reference numeral 11 is a semiconductor substrate such as GaAs, and an active layer 12 is provided on the semiconductor substrate 11. Further, a source electrode S and a drain electrode D, which are in ohmic contact, are provided on the active layer 12 at predetermined intervals. On the active layer 12 located between the source electrode S and the drain electrode D, a recess 13 formed by digging a part of the active layer 12 to a predetermined depth is provided, and a Schottky junction gate electrode G is formed in the recess 13. It is provided. Further, a groove 14 having a predetermined depth is formed in a part of the active layer 12 between the recess 13 provided with the gate electrode G and the drain electrode D.

【0009】上記の構成において、リセス13の外側に
位置する能動層12の厚さをt、また、溝14部分の下
方に位置する能動層12の厚さをt1、ゲート電極Gの
下方に位置する能動層12の厚さをt2とした場合に、
それぞれの厚さt、t1、t2は、t>t1>t2の関
係に設定されている。
In the above structure, the thickness of the active layer 12 located outside the recess 13 is t, the thickness of the active layer 12 located below the groove 14 is t1, and the thickness of the active layer 12 is located below the gate electrode G. When the thickness of the active layer 12 is t2,
The respective thicknesses t, t1, t2 are set to satisfy the relation of t>t1> t2.

【0010】この場合、溝14部分の下方に位置する能
動層12の厚さt1を、ゲート電極Gの下方に位置する
能動層12の厚さt2よりも大きくしているため、溝1
4の部分でドレイン電流が制限されるようなことがな
く、溝14を設けても大電力化に支障となるようなこと
がない。
In this case, the thickness t1 of the active layer 12 located below the groove 14 is made larger than the thickness t2 of the active layer 12 located below the gate electrode G.
The drain current is not limited at the portion 4 and even if the groove 14 is provided, it does not hinder an increase in power.

【0011】上記した構成によれば溝14の部分で電界
が緩和される。その結果、ソース抵抗を増加させること
なく、ゲート電極Gとドレイン電極D間の耐圧を向上さ
せた半導体装置たとえば電界効果型トランジスタが実現
できる。
According to the above structure, the electric field is relaxed in the groove 14. As a result, it is possible to realize a semiconductor device such as a field effect transistor in which the breakdown voltage between the gate electrode G and the drain electrode D is improved without increasing the source resistance.

【0012】次に、本発明の実施の形態について図2を
参照して説明する。図2は図1に対応する部分には同じ
符号を付し重複する説明を一部省略する。
Next, an embodiment of the present invention will be described with reference to FIG. In FIG. 2, portions corresponding to those in FIG.

【0013】この実施形態の場合、ソース電極Sおよび
ドレイン電極D間に位置する能動層12の広い範囲を掘
り込んだ第1リセス21を形成している。また、第1リ
セス21内の能動層12の一部をさらに掘り込んだ第2
リセス22を形成し、第2リセス22内にショットキ接
合のゲート電極Gが設けられている。そして、第1リセ
ス21内で、ゲート電極Gが設けられた第2リセス22
とドレイン電極Dとの間に所定深さの溝23が形成され
ている。
In this embodiment, the first recess 21 is formed by engraving a wide area of the active layer 12 located between the source electrode S and the drain electrode D. In addition, the active layer 12 in the first recess 21 is partially dug into a second
The recess 22 is formed, and the Schottky junction gate electrode G is provided in the second recess 22. Then, in the first recess 21, the second recess 22 provided with the gate electrode G is formed.
A groove 23 having a predetermined depth is formed between the drain electrode D and the drain electrode D.

【0014】上記の構成において、第1リセス21の外
側に位置する能動層12の厚さをt、また、第2リセス
22内の溝23が設けられていない部分の能動層12の
厚さをt0、溝23部分の下方に位置する能動層12の
厚さをt1、ゲート電極Gの下方に位置する能動層12
の厚さをt2とした場合に、それぞれの厚さt、t0、
t1、t2は、t>t0>t1>t2のの関係に設定さ
れている。
In the above structure, the thickness of the active layer 12 located outside the first recess 21 is t, and the thickness of the active layer 12 in the portion of the second recess 22 where the groove 23 is not provided. t0, the thickness of the active layer 12 located below the groove 23 is t1, and the active layer 12 located below the gate electrode G.
When the thickness of each is t2, the respective thicknesses t, t0,
t1 and t2 are set to satisfy the relationship of t>t0>t1> t2.

【0015】この場合も、溝23部分の下方に位置する
能動層12の厚さt1を、ゲート電極Gの下方に位置す
る能動層12の厚さt2よりも大きくしているため、溝
23の部分でドレイン電流が制限されるようなことがな
く、溝14を設けても大電力化に支障となるようなこと
がない。
Also in this case, since the thickness t1 of the active layer 12 located below the groove 23 is made larger than the thickness t2 of the active layer 12 located below the gate electrode G, the groove 23 of the groove 23 is formed. The drain current is not limited at the portion, and the provision of the groove 14 does not hinder the increase in power consumption.

【0016】上記した構成によれば溝23の部分で電界
が緩和され、ソース抵抗を増加させることなく、ゲート
電極Gとドレイン電極D間の耐圧を向上できる。
According to the above structure, the electric field is relaxed in the groove 23, and the breakdown voltage between the gate electrode G and the drain electrode D can be improved without increasing the source resistance.

【0017】次に、本発明の実施の形態について図3を
参照して説明する。図3は図2に対応する部分には同じ
符号を付し重複する説明を一部省略する。
Next, an embodiment of the present invention will be described with reference to FIG. In FIG. 3, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and overlapping description will be partially omitted.

【0018】この実施形態では、第1リセス21内の能
動層12上に形成する溝23を、第1リセス21のドレ
イン電極Dの端部21aと溝23のドレイン電極Dの端
部23aが一致する位置に設けている。この場合も、溝
23の部分で電界が緩和され、ソース抵抗を増加させる
ことなく、ゲート電極Gとドレイン電極D間の耐圧が向
上する。
In this embodiment, the end portion 21a of the drain electrode D of the first recess 21 and the end portion 23a of the drain electrode D of the groove 23 coincide with the groove 23 formed on the active layer 12 in the first recess 21. It is provided at the position where Also in this case, the electric field is relaxed in the groove 23, and the breakdown voltage between the gate electrode G and the drain electrode D is improved without increasing the source resistance.

【0019】上記の各実施形態では、能動層が単層構造
の場合で説明している。しかし、本発明は、能動層が単
層構造の場合に限らず、HEMTあるいはHFETなど
のような多層構造についても適用できる。
In each of the above embodiments, the case where the active layer has a single layer structure has been described. However, the present invention is not limited to the case where the active layer has a single layer structure, but can be applied to a multilayer structure such as HEMT or HFET.

【0020】[0020]

【発明の効果】本発明によれば、ゲート電極とドレイン
電極間の耐圧の低下を防止した半導体装置を実現でき
る。
According to the present invention, it is possible to realize a semiconductor device in which the breakdown voltage between the gate electrode and the drain electrode is prevented from decreasing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態を説明するための断面図であ
る。
FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention.

【図2】本発明の他の実施形態を説明するための断面図
である。
FIG. 2 is a sectional view for explaining another embodiment of the present invention.

【図3】本発明の他の実施形態を説明するための断面図
である。
FIG. 3 is a sectional view for explaining another embodiment of the present invention.

【図4】従来例を説明するための断面図である。FIG. 4 is a cross-sectional view for explaining a conventional example.

【符号の説明】[Explanation of symbols]

11…半導体基板 12…能動層 13…リセス 14…溝 S…ソース電極 D…ドレイン電極 G…ゲート電極 t…リセスの外側で溝の形成されていない領域の能動層
の厚さ t1…溝の下方に位置する能動層の厚さ t2…ゲート電極の下方に位置する前記能動層の厚さ
11 ... Semiconductor substrate 12 ... Active layer 13 ... Recess 14 ... Groove S ... Source electrode D ... Drain electrode G ... Gate electrode t ... Active layer thickness t1 outside region of the recess ... Thickness t2 of the active layer located at the bottom of the active layer located below the gate electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 能動層が形成された半導体基板と、前記
能動層上に設けられたオーム性接触のソース電極と、前
記能動層上に設けられたオーム性接触のドレイン電極
と、前記能動層を掘り込んだリセス内に設けられたショ
ットキ接合のゲート電極とを具備した半導体装置におい
て、前記リセスと前記ドレイン電極との間の能動層上に
所定深さの溝を設けたことを特徴とする半導体装置。
1. A semiconductor substrate having an active layer formed thereon, an ohmic contact source electrode provided on the active layer, an ohmic contact drain electrode provided on the active layer, and the active layer. In a semiconductor device having a Schottky junction gate electrode provided in a recessed portion, a groove having a predetermined depth is provided on an active layer between the recess and the drain electrode. Semiconductor device.
【請求項2】 溝の下方に位置する能動層の厚さをt
1、ゲート電極の下方に位置する前記能動層の厚さをt
2、リセスの外側で溝の形成されていない領域の前記能
動層の厚さをtとした場合に、t>t1>t2の関係が
ある請求項1記載の半導体装置。
2. The thickness of the active layer located below the trench is t
1. The thickness of the active layer located below the gate electrode is t
2. The semiconductor device according to claim 1, wherein there is a relationship of t>t1> t2, where t is a thickness of the active layer in a region where no groove is formed outside the recess.
【請求項3】 能動層が形成された半導体基板と、前記
能動層上に設けられたオーム性接触のソース電極と、前
記能動層上に設けられたオーム性接触のドレイン電極
と、前記ソース電極および前記ドレイン電極間の前記能
動層を掘り込んだ第1リセスと、この第1リセス内の前
記能動層を掘り込んだ第2リセス内に設けられたショッ
トキ接合のゲート電極とを具備した半導体装置におい
て、前記ゲート電極と前記ドレイン電極との間に位置す
る前記第1リセス内の能動層上に所定深さの溝を設けた
ことを特徴とする半導体装置。
3. A semiconductor substrate having an active layer formed thereon, an ohmic contact source electrode provided on the active layer, an ohmic contact drain electrode provided on the active layer, and the source electrode. And a semiconductor device having a first recess in which the active layer is dug between the drain electrodes, and a Schottky junction gate electrode provided in a second recess in which the active layer is dug in the first recess. The semiconductor device according to claim 1, wherein a groove having a predetermined depth is provided on the active layer in the first recess located between the gate electrode and the drain electrode.
【請求項4】 溝の下方に位置する前記能動層の厚さを
t1、ゲート電極の下方に位置する前記能動層の厚さを
t2、前記第1リセスの外側に位置する前記能動層の厚
さをt、前記第1リセス内で前記溝の形成されていない
領域の前記能動層の厚さをt0とした場合に、t>t0
>t1>t2の関係がある請求項3記載の半導体装置。
4. The thickness of the active layer located below the trench is t1, the thickness of the active layer located below the gate electrode is t2, and the thickness of the active layer located outside the first recess. Where t is t, and t is the thickness of the active layer in the region where the groove is not formed in the first recess, t> t0
The semiconductor device according to claim 3, wherein there is a relationship of>t1> t2.
JP2001302678A 2001-09-28 2001-09-28 Semiconductor device Pending JP2003109972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001302678A JP2003109972A (en) 2001-09-28 2001-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001302678A JP2003109972A (en) 2001-09-28 2001-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003109972A true JP2003109972A (en) 2003-04-11

Family

ID=19122877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001302678A Pending JP2003109972A (en) 2001-09-28 2001-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003109972A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007068018A2 (en) * 2005-12-13 2007-06-21 B2 Electronic Gmbh Arrangement comprising at least one electronic component
CN106601808A (en) * 2016-12-19 2017-04-26 苏州捷芯威半导体有限公司 Semiconductor device and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007068018A2 (en) * 2005-12-13 2007-06-21 B2 Electronic Gmbh Arrangement comprising at least one electronic component
WO2007068018A3 (en) * 2005-12-13 2007-08-09 B2 Electronic Gmbh Arrangement comprising at least one electronic component
US7999373B2 (en) 2005-12-13 2011-08-16 B2 Electronic Gmbh Arrangement having at least one electronic component
CN106601808A (en) * 2016-12-19 2017-04-26 苏州捷芯威半导体有限公司 Semiconductor device and preparation method thereof

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