JPH04229662A - Vertical-type transistor and its manufacture - Google Patents

Abstract

PURPOSE:To enhance the breakdown strength of the title transistor at a corner in a trench and to lower the ON resistance of the title transistor by a method wherein a gate insulating film is formed to be thick at the bottom face of the trench and at one part on the side face continued to the bottom face. CONSTITUTION:At a vertical-type MOS transistor, a first impurity region 3 is formed on the surface of a semiconductor substrate 1, and a second impurity region 7 whose conductivity type is opposite to that of the region is formed at the lower part of the first impurity region 3. A trench 23 is formed so as to be deeper than the bottom part of at least the second impurity region 7 by passing the first and second impurity regions 3, 7 from the surface of the semiconductor substrate 1; a gate electrode 11 is formed at the inside of the trench 23 via a gate insulating film 9. The gate insulating film 9 is formed to be thick at the bottom face of the trench 23 and at one part on the side face continued to the bottom face. Thereby, the sufficient breakdown strength of the title transistor can be obtained, and the ON resistance of the title transistor can be lowered.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a vertical MOS transistor and a method for manufacturing the same, and more particularly to a vertical MOS transistor and a method for manufacturing the same that can lower on-resistance and increase breakdown voltage at the corner of a gate electrode. be.

0002

2. Description of the Related Art Vertical MOS transistors are one of the promising devices in the future because they have high driving ability, occupy a small area on a substrate, and are easy to achieve a high degree of integration. FIG. 12 shows an example of a conventional vertical MOS transistor. This is described in Japanese Patent Application Laid-open No. 1-192174.

This conventional vertical MOS transistor has n
a drain region 103 made of an n- type impurity semiconductor formed by epitaxial growth on a + type semiconductor substrate 101; a channel region 105 made of a P type impurity semiconductor provided in the drain region 103;
A source region 107 made of an n+ type impurity semiconductor formed above the channel region 105, the source region 107, the channel region 105, and the drain region 1.
A gate electrode 117 is provided in a trench 123 formed through the trench 03 with a gate insulating film 109 interposed therebetween, and a source electrode 119 is provided on the gate electrode 117 with an insulating film 121 interposed therebetween. .

The gate insulating film 109 in the trench 123 is thick at the bottom of the trench 123 .

The vertical MOS transistor having the above structure is advantageous for increasing the cell density, that is, the degree of integration, and reducing the on-resistance. Here, the gate insulating film is thick at the bottom of the trench 123, but this is due to the relationship between the depth of the trench, on-resistance, and breakdown voltage. That is, as the trench depth increases, the on-resistance decreases, but the breakdown voltage decreases. Therefore, if the trench is deepened to lower the on-resistance, the withstand voltage will drop, and in order to improve the lowered withstand voltage to a predetermined value (for example, a value that guarantees a 60V system), the gate insulating film 129 at the bottom of the trench is It is made thicker.

This conventional method for manufacturing a vertical MOS transistor is carried out as shown in FIG. First, a source region 107, a channel region 105 and a drain region 10
An oxide film 1 is formed on the surface of the trench 123 formed through the oxide film 1.
25 and a nitride film 127 are formed, and the nitride film 127 is removed leaving only the side surfaces of the trench 123 (FIG. 13A). Next, the entire oxide film is thermally oxidized to thicken the oxide film at the bottom of the trench 123, and a thick gate insulating film 1 is formed on the bottom of the trench 123.
29 (LOCOS) is obtained (FIG. 13B). Thereafter, polysilicon is buried to form a gate electrode 117, and necessary wiring such as a source electrode 119 is provided (FIG. 13C). The configuration of the vertical MOS transistor described above has a thick gate oxide film 129 on the bottom surface of the trench 123 to improve the withstand voltage as described above, so that it is possible to prevent the electric field from concentrating on a part of the gate electrode. It's advantageous. That is, if the gate insulating film is thin even at the bottom, as can be seen from the isoelectric interface shown in FIG. 14, the electric field will be concentrated at the corners of the gate electrode 117, that is, the corners of the trench 123, and the withstand voltage will decrease. The conventional example shown in FIG. 12 is designed to prevent the above-mentioned electric field concentration at the corners of the trench, but it has the following drawbacks.

[0007]

That is, as shown in an enlarged view in FIG. 17, in the process of thickening the oxide film on the bottom surface of trench 123 by thermal oxidation (FIG. 13B), trench 1
The oxide film 131 at the corner of the trench 123 has a bird's peak structure, but at this time, the nitride film 127 on the side surface of the trench 123 is pushed up, stress is applied to the oxide film 131 at the trench corner, causing a transition, and electricity is generated at the corner. There was a problem in that target passes were more likely to occur and the withstand voltage was lowered. That is, the trench 12
The problem of electric field concentration at the corner of No. 3 still remains.

Furthermore, in the conventional technique, the nitride film 127 must be formed only on the side surfaces of the trench, and in the case of the manufacturing method of the cited example, this is done by removing the film formed on the horizontal surface by RIE. Although only the film is to be left behind, this method is extremely difficult in practice. I mean,
The selectivity of RIE is not very high, and the trench sides are not exactly vertical, so the nitride film on the trench sides would also be etched unless special measures were taken. Therefore, the yield in manufacturing the MOS transistor is lowered, and the reliability of the completed MOS transistor is lowered.

[0009]Furthermore, there is a problem that the method cannot be applied to a V-shaped trench having an inclined side surface because the nitride film on the side surface of the trench is completely etched.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a vertical MOS transistor that can obtain sufficient breakdown voltage and reduce on-resistance, and a method for manufacturing the same. That's true.

Another object of the present invention is to provide a vertical MOS that can prevent concentration of electric fields at the corners of trenches.
Still another object of the present invention, which is to provide a transistor and a method for manufacturing the same, is to provide a manufacturing method that can manufacture a highly reliable vertical MOS transistor with high yield.

0012

[Means for Solving the Problems] In order to achieve the above object, the first feature of the present invention is to provide a vertical MOS transistor including a semiconductor substrate and a first impurity region provided on the surface of the semiconductor substrate. a second impurity region formed below the first impurity region and having a conductivity type opposite to the first impurity region;
a trench formed deeper than at least the bottom of the second impurity region, and a gate electrode formed inside the trench with a gate insulating film interposed therebetween; The film is thicker at the bottom of the trench and part of the side surfaces continuous thereto.

A second feature of the present invention is that, in a vertical MOS transistor, a semiconductor substrate, a first impurity region provided on the surface of the semiconductor substrate, a first impurity region formed below the first impurity region, a second impurity region having an opposite conductivity type;
and at least the second impurity region.
a trench formed deeper than the bottom of the impurity region;
A first gate electrode formed at the bottom of the trench with a first gate insulating film interposed therebetween;
a second gate electrode formed on the gate electrode with a second gate insulating film interposed therebetween, and at least the first gate insulating film is thicker than the second gate insulating film. It is that you are.

A third feature of the present invention is that, in a vertical MOS transistor, a semiconductor substrate, a first impurity region provided on the surface of the semiconductor substrate, a first impurity region formed below the first impurity region, a second impurity region having an opposite conductivity type;
and at least the second impurity region.
a trench formed deeper than the bottom of the impurity region;
A floating gate electrode is formed at the bottom of the trench with a first gate insulating film interposed therebetween, a floating gate electrode is formed at the top of the floating gate electrode with a capacitance insulating film interposed therebetween, and a second impurity region is formed in the first and second impurity regions. and a main gate electrode adjacent to each other with two gate insulating films interposed therebetween,
The first gate insulating film is thicker than the second gate insulating film.

A fourth feature of the present invention is a method for manufacturing a vertical MOS transistor, which includes a first impurity region on the surface of a semiconductor substrate, and an opposite impurity region located below the first impurity region. forming a second impurity region having a conductivity type, and extending from the surface of the semiconductor substrate through the first and second impurity regions to be deeper than at least the bottom of the second impurity region. A step of forming a trench, and a step of forming a gate electrode in the trench via a gate insulating film so that the gate insulating film becomes thick on the bottom surface of the trench and a part of the side surfaces continuous thereto. be.

A fifth feature of the present invention is a method for manufacturing a vertical MOS transistor, which includes a first impurity region on the surface of a semiconductor substrate, and an opposite impurity region located below the first impurity region. forming a second impurity region having a conductivity type, and extending from the surface of the semiconductor substrate through the first and second impurity regions to be deeper than at least the bottom of the second impurity region. forming a trench, and forming a relatively thick first insulating film in the trench;
A conductive material is buried in the trench in which the first insulating film is formed, and in the trench, the conductive material is placed above a predetermined first position of the buried conductive material and in the first insulating film. forming a relatively thick first gate insulating film and a first gate electrode by removing a portion above a predetermined second position; A second insulating film thinner than the relatively thick first gate insulating film is formed on the upper side of the trench, and a conductive material is formed on the top of the second insulating film, thereby forming a relatively thin second gate insulating film.
forming a gate insulating film and a second gate electrode.

[0017]

[Function] As mentioned above, since the gate insulating film is thicker at the bottom of the trench and part of the side surfaces continuous with it, the withstand voltage particularly at the corners of the trench is significantly improved, and the depth of the trench is reduced. Even if the on-resistance is lowered by increasing the depth, the problem of electric field concentration can be prevented, and punch-through and the like can also be prevented.

[0018] This is especially true for 60V type power MOs.
This is effective when applied to S low voltage products.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a sectional view of an embodiment of a vertical MOS transistor according to the present invention. This transistor is n+
type single crystal silicon substrate 1, a drain region 3 made of an n-type impurity semiconductor epitaxially grown on this semiconductor substrate, and a drain region 3 made of a p-type impurity semiconductor provided in this impurity semiconductor region 3 in the depth direction. The thickness is 1.
A channel region 5 of 5 microns and an n+ type impurity semiconductor formed above the channel region 5 has a thickness of 0.5 microns in the depth direction.
A source region 7 of 5 microns, a trench 23 formed through these, and a relatively thick first gate insulating film 9 formed inside the trench 23 so as to extend to the upper part of the source region 7. A capacitance insulating film 13 is formed between the first floating gate electrode 11 and the side wall of the trench 23 and about the upper half of the floating gate electrode 11 and the channel region. 5 and a relatively thin second gate insulating film 1 in the source region 7.
5 and an adjacent main gate electrode, that is, a second gate electrode 17. Here, the thickness of the first gate insulating film 9 is 0.5 to 1.5 microns, for example, 0.8 microns, and the thickness of the second gate insulating film 15 is much thinner than this, 300 to 1000 angstroms. For example, 500 angstroms is selected. Generally, it is preferable that the first gate insulating film 9 is thicker than the second gate insulating film 15 by at least 10 times or 2000 angstroms or more. Further, here, the upper end of the first gate insulating film 9 is located inside the drain region 3 and extends a predetermined distance X upward from the lower end of the first gate electrode 11.
It is in the same position. In this case, the predetermined distance X is 3μ
m.

A source electrode 19 is connected to the source region 7 and a gate control electrode 21 is connected to the main gate electrode 17. By applying a positive control voltage to the gate electrode 17, the channel is controlled. Formed source electrode 19
and the substrate 1 are electrically connected. FIG. 2 schematically shows an equivalent circuit diagram of this transistor.

The floating gate electrode 11 has capacitors C1 and C between the gate electrode 17 and the substrate 1, respectively.
Connected via 2. The capacitor C1 and the capacitor C2 are connected to the first gate insulating film 9 and the second gate insulating film 9, respectively.
Since the gate insulating film 15 is formed across the gate insulating film 15, these thicknesses are reflected so that C1 <<C2. Therefore, the potential of the floating gate electrode 11 has a value close to the potential of the main gate potential 17, which still contributes to the formation of a channel in driving this transistor.

In this embodiment, since the first gate insulating film 9 is thick at the bottom of the trench 23 and a portion of the side surfaces continuous thereto, the withstand voltage at the trench corners is significantly improved.

Next, the manufacturing process of this transistor will be explained with reference to FIGS. 3A to 5C.

First, as shown in FIG. 3A, an n - type silicon semiconductor layer 3 is epitaxially grown on the surface of an n + type single crystal silicon semiconductor substrate 1 . Within this layer 3,
Using normal diffusion technology, p+ type semiconductor region 5 and n+
A type semiconductor region 7 is formed. The thickness in the depth direction is 0.
．． 5 microns and 1.5 microns. A trench 23 penetrating these two regions 5 and 7 and reaching a part of the semiconductor layer 3 is formed to a width of 2 microns and a depth of 3.0 microns using anisotropic etching such as RIE (FIG. 3B). . Next, as shown in FIG. 3C, including the inside of the trench 23,
Thick (approximately 8000 angstroms) due to thermal oxidation
A silicon oxide film 25 is formed. Next, polysilicon 27 is buried inside the trench 23 by the LP/CVD method, and the upper part thereof is removed by etching back, leaving only the upper end of the source region 7 (FIG. 4A). As a result, the first gate electrode, that is, the floating gate electrode 11 is formed.

Next, the upper portion of the silicon oxide film 25 is removed, leaving a portion below a predetermined position inside the drain region 3 (FIG. 4B). As a result, a relatively thick first gate insulating film 9 (approximately 8000 angstroms) is formed. This is done by wet etching using ammonium fluoride.

Next, the inner surface of the trench 23 including the exposed portion of the polysilicon 11 and the surface of the source region 7 are thermally oxidized to form a thin silicon oxide film 29 (about 500 angstroms) (FIG. 4C). . As a result, the capacitance insulating film 13 and the thin second gate insulating film 1
5 (approximately 500 angstroms) is formed.

A polysilicon film 31 with a thickness of 5000 angstroms is formed on the entire surface including the inside of the trench 23 by LP/CVD, and the surface is thermally oxidized to form a silicon oxide film 33 of 0.1
micron formation (Fig. 5A). A polysilicon film 35 of 1 micron is again formed thereon (FIG. 5B) and removed by etching except for the portion inside the trench. At this time, due to the presence of the silicon oxide film 33, the polysilicon film 31 remains as it is. This silicon oxide film 33 is patterned by conventional photolithography, and using this as a mask, the polysilicon film 31 is patterned (FIG. 5C). As a result, the second gate electrode 17 is formed. Thereafter, a gate control electrode 21 and a source electrode 19 are formed using a conventional method to complete a transistor (FIG. 1).

It should be noted that the above description has been made regarding the preferred embodiment, and it goes without saying that those skilled in the art can easily change or add some parts according to the corresponding examples. For example, in the case of the first embodiment described above,
A capacitance was formed between the first gate electrode 11 and the second gate electrode 17, but after manufacturing, the capacitance was formed between the first gate electrode 11 and the second gate electrode 17.
It is also possible to electrically connect the gate electrode and the second gate electrode. That is, this can be achieved by providing a contact electrode on the first gate electrode and connecting the second gate electrode and the contact electrode with a metal wiring.

In the manufacturing process shown in FIGS. 3B to 4B, the depth of the trench 23, the position of the upper end of the polysilicon 27, that is, the first gate electrode 11, and the position of the upper end of the first gate insulating film 9 are also determined. can be changed in various ways depending on the case. That is, as shown in the schematic diagrams of FIGS. 6 and 7, the depth of the trench may be such that it penetrates the n- type drain region 3 and reaches the n+ type silicon substrate 1. As a condition for the modified examples of FIGS. 6 and 7, the position of the upper end of the first gate insulating film 9 is
The value shall be greater than 1 micron from the top of the . In the case of this modification, consider a structure in which the gate oxide film thickness of the UMOSFET is partially changed in order to reduce the RA product (on-resistance) and improve the withstand voltage. Then, using the second gate oxide film and trench depth as parameters, the Vds breakdown voltage, RA product, and Cgs (gate-drain) capacitance are determined. The parameter range is that the second gate oxide film thickness is 2000 angstroms,
The trench depth is 10.5 um when the thickness is 3000 angstroms and 4000 angstroms. Further, the trench depths are set to 8 um, 10 um, and 12 um using the second gate oxide film thickness obtained from the Vds breakdown voltage of 80 V. 9 to 12 show the results of an experimental comparison of the on-resistance and breakdown voltage between the modified example shown in FIGS. 6 and 7 and the schematic device structure of the conventional vertical MOS transistor shown in FIG. 8 under the above conditions. Shown below.

As another example, as shown in FIG. 13, the first embodiment is modified to lower the upper end of the first gate electrode 11 and further lower the upper end of the first gate insulating film 9. It can also be configured to raise the position.

Further, the manufacturing method shown in FIGS. 3A to 5C can be applied to a transistor having a V-type trench as is.

[0032]

As described above, according to the present invention, since the gate insulating film has a structure in which it is thicker at the bottom surface of the trench and a part of the side surfaces continuous thereto, the withstand voltage particularly at the corners of the trench is significantly increased. Even if the on-resistance is lowered by increasing the depth of the trench, the problem of electric field concentration can be prevented, and punch-through and the like can also be prevented.

This is especially true for 60V type power MOs.
This is effective when applied to S low voltage products.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an embodiment of a vertical MOS transistor according to the present invention.

FIG. 2 is an equivalent circuit diagram of the vertical MOS transistor shown in FIG. 1.

3 is a manufacturing process diagram of the vertical MOS transistor shown in FIG. 1. FIG.

4 is a manufacturing process diagram of the vertical MOS transistor shown in FIG. 1. FIG.

5 is a manufacturing process diagram of the vertical MOS transistor shown in FIG. 1. FIG.

FIG. 6 is a schematic configuration diagram of a modification of the embodiment shown in FIG. 1;

FIG. 7 is a schematic configuration diagram of a modification of the embodiment shown in FIG. 1;

FIG. 8 is a schematic configuration diagram of a conventional vertical MOS transistor.

9 is a diagram showing experimental comparison results between the modified example shown in FIGS. 6 and 7 and the conventional example shown in FIG. 8. FIG.

10 is a diagram showing experimental comparison results between the modified example shown in FIGS. 6 and 7 and the conventional example shown in FIG. 8. FIG.

11 is a diagram showing experimental comparison results between the modified example shown in FIGS. 6 and 7 and the conventional example shown in FIG. 8. FIG.

12 is a diagram showing experimental comparison results between the modified example shown in FIGS. 6 and 7 and the conventional example shown in FIG. 8. FIG.

FIG. 13 is a configuration diagram of still another modification of the embodiment shown in FIG. 1;

FIG. 14 is a cross-sectional view of a conventional vertical MOS transistor.

15 is a diagram showing a manufacturing process of the conventional vertical MOS transistor shown in FIG. 14. FIG.

16 is a diagram illustrating concentration of electric fields at trench corners of the conventional vertical MOS transistor shown in FIG. 14. FIG.

17 is a diagram illustrating problems in the manufacturing process of the conventional vertical MOS transistor shown in FIG. 15. FIG.

[Explanation of symbols]

1 Silicon substrate 3 Drain region 5 Channel area 7 Source area 9 First gate insulating film 11 Floating gate electrode 15 Second gate insulating film 17 Second gate electrode 19 Source electrode 21 Gate control electrode

Claims (19)

[Claims] 1. A vertical MOS transistor comprising a semiconductor substrate, a first impurity region provided on a surface of the semiconductor substrate, and a second impurity region formed below the first impurity region. , a trench formed from a surface of the semiconductor substrate through at least the first impurity region, and a gate electrode formed inside the trench with a gate insulating film interposed therebetween, the gate insulating film being A vertical MOS transistor characterized in that the bottom surface of the trench and a part of the side surfaces continuous with the bottom surface are thick. 2. The vertical MOS transistor according to claim 1, wherein the second impurity region has a conductivity type opposite to that of the first impurity region. 3. The trench is connected to the first and second trenches.
3. The vertical MOS transistor according to claim 2, wherein the vertical MOS transistor is formed deeper than the bottom of the second impurity region so as to penetrate through the impurity region. 4. The vertical MOS transistor according to claim 3, wherein the trench is formed to a depth that reaches the semiconductor substrate. 5. A vertical MOS transistor comprising: a semiconductor substrate; a first impurity region provided on a surface of the semiconductor substrate; and a first impurity region formed below the first impurity region;
a second impurity region having a conductivity type opposite to that of the first impurity region; and at least a bottom portion of the second impurity region extending from the surface of the semiconductor substrate through the first and second impurity regions. a first gate electrode formed at the bottom of the trench with a first gate insulating film interposed therebetween, and a second gate formed above the first gate electrode in the trench. a second gate electrode formed through an insulating film, and at least the first gate insulating film is thicker than the second gate insulating film. transistor. 6. The vertical MOS transistor according to claim 5, wherein the trench is formed to a depth that reaches the semiconductor substrate. 7. The vertical MOS transistor according to claim 5, wherein a capacitance insulating film is formed between the first gate electrode and the second gate electrode. 8. The vertical MOS transistor according to claim 5, wherein the first gate electrode and the second gate electrode are electrically connected. 9. A vertical MOS transistor comprising: a semiconductor substrate; a first impurity region provided on a surface of the semiconductor substrate; and a semiconductor substrate formed below the first impurity region;
a second impurity region having an opposite conductivity type; and a second impurity region formed from the surface of the semiconductor substrate through the first and second impurity regions to be deeper than at least the bottom of the second impurity region. a floating gate electrode formed on the bottom of the trench with a first gate insulating film interposed therebetween, and a capacitance insulating film formed on the upper part of the floating gate electrode with a capacitance insulating film interposed therebetween; a main gate electrode adjacent to the impurity region with a second gate insulating film in between, the first gate insulating film being thicker than the second gate insulating film; type MOS transistor. 10. The vertical MOS transistor according to claim 9, wherein the trench is formed to a depth that reaches the semiconductor substrate. 11. The vertical MOS transistor according to claim 9, wherein the first gate electrode and the second gate electrode are electrically connected. 12. A method for manufacturing a vertical MOS transistor, comprising: a first impurity region on the surface of a semiconductor substrate; a second impurity region located below the first impurity region and having an opposite conductivity type; forming a trench extending from the surface of the semiconductor substrate through the first and second impurity regions to be deeper than at least the bottom of the second impurity region; a step of forming a gate electrode in the trench via a gate insulating film so that the gate insulating film is thick on the bottom surface of the trench and a part of the side surfaces continuous thereto; A method for manufacturing a MOS transistor. 13. The method of manufacturing a vertical MOS transistor according to claim 12, wherein the trench is formed to a depth that reaches the semiconductor substrate. 14. A method for manufacturing a vertical MOS transistor, comprising: a first impurity region on a surface of a semiconductor substrate; a second impurity region located below the first impurity region and having a conductivity type opposite to the first impurity region; forming a trench extending from the surface of the semiconductor substrate through the first and second impurity regions to be deeper than at least the bottom of the second impurity region; A relatively thick first insulating film is formed in the trench, a conductive material is buried in the trench in which the first insulating film is formed, and the buried conductive material is predetermined in the trench. forming a relatively thick first gate insulating film and a first gate electrode by removing a portion of the first insulating film above the predetermined first position and above a predetermined second position of the first insulating film; forming a second insulating film thinner than the relatively thick first gate insulating film on the first gate electrode in the trench and on the upper side of the trench; 1. A method for manufacturing a vertical MOS transistor, comprising the step of forming a relatively thin second gate insulating film and a second gate electrode by forming a conductive material thereon. 15. The vertical MOS transistor of claim 14, wherein the first predetermined position of the buried conductive material substantially coincides with the top surface of the first impurity region. manufacturing method. 16. A predetermined second position of the first insulating film is located between a lower end position of the second impurity region and a position a predetermined distance above the lower end of the first gate electrode. 16. The method for manufacturing a vertical MOS transistor according to claim 15, wherein the vertical MOS transistor is between. 17. The method of manufacturing a vertical MOS transistor according to claim 15, wherein the trench is formed to a depth that reaches the semiconductor substrate. 18. The method of manufacturing a vertical MOS transistor according to claim 15, wherein a capacitance insulating film is formed between the first gate electrode and the second gate electrode. 19. The method for manufacturing a vertical MOS transistor according to claim 15, wherein the first gate electrode and the second gate electrode are electrically connected.