JPS60167373A - Manufacture of insulated gate field-effect transistor - Google Patents
Manufacture of insulated gate field-effect transistorInfo
- Publication number
- JPS60167373A JPS60167373A JP2316584A JP2316584A JPS60167373A JP S60167373 A JPS60167373 A JP S60167373A JP 2316584 A JP2316584 A JP 2316584A JP 2316584 A JP2316584 A JP 2316584A JP S60167373 A JPS60167373 A JP S60167373A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- concentration
- gate
- poly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000004904 shortening Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000010894 electron beam technology Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
、不発明は絶縁ゲート電界効果トランジスタ（以下、Ｍ
ＯＳＦＥＴ を記す）の製造方法に関するものである。[Detailed Description of the Invention] The field of industrial application and non-invention is insulated gate field effect transistors (hereinafter referred to as M
The present invention relates to a manufacturing method of OSFET.
従来例の構成とその問題点
従来、縦型ＭＯ３ＦＥＴ Ｋは、ゲート電極材料として
多結晶シリコン膜に不純物拡散を行ない、シート抵抗値
を３０Ω／口（厚さ２０．５μｍ ）にして用いている
。しかしながら、今日のＬＳＩ技術においては、高密度
化の要求が厳しく、これにともなって多結晶シリコン膜
の幅の短縮化が要求されるようになってきた。この短縮
化に伴って、多結晶シリコン膜の抵抗値が増大しＭＯＳ
ＦＥＴ の性能低下を生じせしめるという問題点がある
。Conventional Structure and Problems Conventionally, the vertical MO3FET K has been used by diffusing impurities into a polycrystalline silicon film as a gate electrode material to have a sheet resistance value of 30 Ω/hole (thickness 20.5 μm). However, in today's LSI technology, there is a strict requirement for higher density, and along with this, there has been a demand for a reduction in the width of the polycrystalline silicon film. Along with this shortening, the resistance value of the polycrystalline silicon film increases and the MOS
There is a problem in that the performance of the FET is degraded.
発明の目的
本発明は、上記欠点に鑑みＭＯＳＦＥＴの多結晶シリコ
ン膜ゲートのシート抵抗全太幅に低減させ、短縮化によ
っても抵抗値を増大せしめることのない、絶縁ゲート電
界効果トランジスタの製造方法を提供するものである。Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing an insulated gate field effect transistor in which the sheet resistance of a polycrystalline silicon film gate of a MOSFET is reduced to the full width, and the resistance value does not increase due to the shortening. This is what we provide.
発明の構成
この目的を達成するために、本発明の絶縁ゲート電界効
果トランジスタの製造方法は、多結晶シリコン膜を溶融
、再結晶化すること′に％徴とじている。DESCRIPTION OF THE INVENTION To achieve this object, the method of manufacturing an insulated gate field effect transistor of the present invention involves melting and recrystallizing a polycrystalline silicon film.
実施例の説明
以下に、不発明の一実施例について同図全参照しながら
説明する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第１図は不発明の一実施例によって作成したＭＯＳＦＥ
Ｔ の構造断面図を模式的に示したものである。このＭ
ＯＳＦＥＴは縦型構造を有しておシ、先ず、比抵抗１０
ｍΩ、ｃｆｎＯ高濃度ｎ形基板１１上に比抵抗１０ｍ、
の低濃度ｎ形層１２全厚さ１０μｍエピタキシャル成長
させる。次に、チャネル領域となるＰ膨拡散層１３とソ
ース領域となる高濃度ｎ影領域１４全それぞれボロン及
び砒素のイオン注入により形成する。Ｐ膨拡散層１３の
拡散長は２．５μｍ表面不純物濃度は３×１０ｍ であ
り、また高濃度ｎ形層１４の拡散長と表面不純物濃度は
それぞれ０．４μｍ 、Ｉ Ｘ１０２１ｃｍ″であった
。次に、反応性イオンエツチング法を用いて、Ｐ膨拡散
層１３を貫通するようにエツチングして、矩形状のゲー
ト領域を形成する。この後、厚さ１０００へのゲート酸
化膜１５を形成し、リンをドープしだポリ・シリコン層
全蒸着により形成し、図のようにゲート電極１６として
パターン形成を行う。次に電子ビームによシポリシリコ
ン層を溶融、再結晶化を行なう。この結果、ポリシリコ
ン層のグレインサイズは極めて犬きくなシ、抵抗率が約
／０
に減少する。この後、通常の層間絶縁膜１７を８０００
への厚きに形成し、コレタクト部を開孔しアルミ電極１
８を形成し、高濃度ｎ形層１４をソース、高濃度ｎ形基
板１１全ドレインとする縦型ＭＯ８ＦＥＴ を作製した
。Figure 1 shows a MOSFE made according to an embodiment of the invention.
This is a schematic cross-sectional view of the structure of T. This M
The OSFET has a vertical structure and has a specific resistance of 10.
mΩ, specific resistance 10m on the cfnO high concentration n-type substrate 11,
The low concentration n-type layer 12 is epitaxially grown to a total thickness of 10 μm. Next, the P diffusion layer 13, which will become a channel region, and the high concentration n shadow region 14, which will become a source region, are all formed by ion implantation of boron and arsenic, respectively. The diffusion length of the P-swelled diffusion layer 13 was 2.5 μm and the surface impurity concentration was 3×10 m, and the diffusion length and surface impurity concentration of the high concentration n-type layer 14 were 0.4 μm and I×1021 cm, respectively.Next Next, a rectangular gate region is formed by etching through the P expansion diffusion layer 13 using a reactive ion etching method.After this, a gate oxide film 15 is formed to a thickness of 1000 mm. A polysilicon layer doped with phosphorus is formed by full evaporation and patterned as a gate electrode 16 as shown in the figure.The polysilicon layer is then melted and recrystallized using an electron beam.As a result, The grain size of the polysilicon layer is extremely small, and the resistivity is reduced to about /0.After this, a normal interlayer insulating film 17 is
Aluminum electrode 1
A vertical MO8FET was fabricated using the highly doped n-type layer 14 as the source and the highly doped n-type substrate 11 as the entire drain.
発明の効果
以上に述べたように不発明は、ポリシリコンを溶融、再
結晶化してゲート電極形成することにより、ゲート抵抗
が従来より著しく減少し、高速性、高周波特性が優れた
絶縁ゲート電界トランジスタを作成することができる。Effects of the Invention As stated above, the insulated gate field transistor has excellent high speed and high frequency characteristics, with gate resistance significantly reduced compared to conventional ones by melting and recrystallizing polysilicon to form the gate electrode. can be created.
従って、不発明の応用は縦型ＭＯ８ＦＥＴ のみならず
ＬＳＩにも拡大出来、そのゲート抵抗の低減、すなわち
、高速化に多いに貢献し、その工業的価値は極めて大き
い。Therefore, the application of the invention can be extended not only to vertical MO8FETs but also to LSIs, greatly contributing to the reduction of gate resistance, that is, to speeding up, and its industrial value is extremely large.
図は本発明の一実施例における絶縁ゲート電界効果トラ
ンジスタの構造断面図を模式的に示したものである。
１１・・・・・高濃度ｎ形基板、１２ ・・・低濃度ｎ
形エピタキシャル層、１３′・・・・・Ｐ膨拡散層、１
４・・高濃度ｎ膨拡散層、１６・・・・・ゲート酸化膜
、１６・・・・・・溶融・再結晶化ポリシリコン層、１
７パ・パ層間絶縁膜、１８・°°・・・アルミ電極。The figure schematically shows a cross-sectional view of the structure of an insulated gate field effect transistor according to an embodiment of the present invention. 11...High concentration n-type substrate, 12...Low concentration n-type substrate
type epitaxial layer, 13'... P swelling diffusion layer, 1
4... High concentration n expansion diffusion layer, 16... Gate oxide film, 16... Melted/recrystallized polysilicon layer, 1
7 Pa-pa interlayer insulating film, 18.°°...aluminum electrode.
Claims (1)
型の半導体層を形成する工程と、前記反対導電型の半導
電体層の内側に前記−導型の半導体層を形成する工程と
、前記−導電型の半導体層の表面より前記反対導電型の
半導体層を貫通する深さの凹部を形成する工程と、前記
凹部の側面に酸化膜を形成する工程と、１ｉｉＪ記酸化
膜の表面に導電性多結晶シリコン膜を形成する工程と、
前記導電性多結晶シリコン膜を溶融、再結晶化してゲー
ト電極を形成する工程とを含むこと全特徴とする絶縁ゲ
ート電界効果トランジスタの製造方法。forming a semiconductor layer of a conductivity type opposite to the -conductivity type on a silicon substrate of one conductivity type; forming a semiconductor layer of the -conductivity type inside the semiconductor layer of the opposite conductivity type; , forming a recess with a depth penetrating the semiconductor layer of the opposite conductivity type from the surface of the semiconductor layer of the - conductivity type; forming an oxide film on the side surface of the recess; 1iiJ the surface of the oxide film; forming a conductive polycrystalline silicon film on the
A method for manufacturing an insulated gate field effect transistor, comprising the step of melting and recrystallizing the conductive polycrystalline silicon film to form a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2316584A JPS60167373A (en) | 1984-02-09 | 1984-02-09 | Manufacture of insulated gate field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2316584A JPS60167373A (en) | 1984-02-09 | 1984-02-09 | Manufacture of insulated gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60167373A true JPS60167373A (en) | 1985-08-30 |
Family
ID=12103002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2316584A Pending JPS60167373A (en) | 1984-02-09 | 1984-02-09 | Manufacture of insulated gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60167373A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273773A (en) * | 1985-09-24 | 1987-04-04 | ソシエテ プ−ル レチユ−ド エ ラ フアブリカシヨン デ シルキユイ アンテグレ スペシオ−− ウ−．エフ．セ−．イ−．エス． | Semiconductor power element with control circuit |
| JPH04229662A (en) * | 1990-06-13 | 1992-08-19 | Toshiba Corp | Vertical-type transistor and its manufacture |
| JPH07142709A (en) * | 1993-06-22 | 1995-06-02 | Nec Corp | Vertical mosfet |
-
1984
- 1984-02-09 JP JP2316584A patent/JPS60167373A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273773A (en) * | 1985-09-24 | 1987-04-04 | ソシエテ プ−ル レチユ−ド エ ラ フアブリカシヨン デ シルキユイ アンテグレ スペシオ−− ウ−．エフ．セ−．イ−．エス． | Semiconductor power element with control circuit |
| JPH04229662A (en) * | 1990-06-13 | 1992-08-19 | Toshiba Corp | Vertical-type transistor and its manufacture |
| JPH07142709A (en) * | 1993-06-22 | 1995-06-02 | Nec Corp | Vertical mosfet |
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