CN106571390B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN106571390B
CN106571390B CN201510658749.XA CN201510658749A CN106571390B CN 106571390 B CN106571390 B CN 106571390B CN 201510658749 A CN201510658749 A CN 201510658749A CN 106571390 B CN106571390 B CN 106571390B
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CN106571390A (zh
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肖德元
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Zing Semiconductor Corp
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Abstract

本发明揭示了一种半导体结构及其形成方法。所述半导体结构的形成方法，包括提供具有虚设栅极的衬底；在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘；去除所述虚设栅极，并在所述虚设栅极处形成包括有栅氧化层的栅极结构，所述氘进入所述栅氧化层中。由此获得的半导体结构，由于使得氘进入栅氧化层中，从而在栅氧化层的界面处形成了稳定的共价键，有效改善了悬空键存在的问题；此外，能够提高器件在面对热载流子效应时的恢复能力，降低了热载流子效应对器件性能的影响。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
背景技术
目前，半导体制造技术已经得到了快速的发展。如图1-6示出了现有技术中的一种常见的MOS形成过程。包括：
如图1所示，在衬底上1形成栅极结构2；
如图2-图4所述，在衬底1上沉积保护层3，覆盖所述栅极结构2；进行反应离子刻蚀，去除部分保护层3，且使得保护层3位于栅极结构2两侧处产生倾斜；进一步去除保护层3位于衬底1上的部分，形成栅极侧墙4；
如图5所示，在衬底1上栅极2两侧外延生成源漏极5，并进行原位掺杂；
如图6所示，进行退火工艺，使得掺杂离子进入衬底1中，形成扩散层6。
但是，包括但不限于经由上述步骤形成的半导体结构，其内部会形成悬空键(dangling bonds)，这些悬空键主要发生在表面或层间界面，从而会产生孔洞，错位、以及引入其他杂志等不良状况。
此外，在目前的MOS制造过程中，出现的另一个问题是热载流子效应对器件性能的影响。特别关注在较小尺寸的器件中，当其在较高的电压下使用时，沟道(channel)的载流子由于具备了足够的能量，从而会进入绝缘层中，从而影响了器件的性能。
发明内容
本发明的目的在于，提供一种半导体结构及其形成方法，降低甚至解决悬挂键和热载流子效应所产生的问题。
为解决上述技术问题，本发明提供一种半导体结构的形成方法，包括：
提供具有虚设栅极的衬底；
在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘；
去除所述虚设栅极，并在所述虚设栅极处形成包括有栅氧化层的栅极结构，所述氘进入所述栅氧化层中。
可选的，对于所述的半导体结构的形成方法，在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘这一步骤包括：
刻蚀所述衬底位于虚设栅极两侧的区域形成沟槽；
利用均匀气相外延沉积工艺在所述沟槽中形成掺杂有氘的源漏区域。
可选的，对于所述的半导体结构的形成方法，所述沟槽为Σ状沟槽或U状沟槽，所述源漏区域包括硅锗外延层或者硅碳外延层，所述氘掺杂于所述硅锗外延层或者硅碳外延层中。
可选的，对于所述的半导体结构的形成方法，所述均匀气相外延沉积工艺包括利用第一源气及第二源气形成所述掺杂有氘的源漏区域。
可选的，对于所述的半导体结构的形成方法，所述第一源气占据的体积比为50％-90％。
可选的，对于所述的半导体结构的形成方法，所述第一源气为氘气，或者是氘气和氢气的混合气体，在所述混合气体中，氘气占据的体积比为2％-98％。
可选的，对于所述的半导体结构的形成方法，所述第二源气包括SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4、Si(CH3)4、GeH4,C3H8、CH4中的至少一种或组合。
可选的，对于所述的半导体结构的形成方法，所述均匀气相外延沉积工艺的温度为800℃-1100℃，持续时间为10-2000分钟。
相应的，本发明还提供一种由如上所述的半导体结构的形成方法获得的半导体结构，包括：
衬底；
形成于所述衬底上的栅极结构，所述栅极结构包括栅氧化层，所述栅氧化层中掺杂有氘；
形成于所述衬底中栅极结构两侧的源漏区域，所述源漏区域掺杂有氘。
与现有技术相比，本发明提供的半导体结构的形成方法，包括提供具有虚设栅极的衬底；在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘；去除所述虚设栅极，并在所述虚设栅极处形成包括有栅氧化层的栅极结构，所述氘进入所述栅氧化层中。由此获得的半导体结构，由于使得氘进入栅氧化层中，从而在栅氧化层的界面处形成了稳定的共价键，有效改善了悬空键存在的问题；此外，由于形成了共价键，能够显著提高器件在面对热载流子效应时的恢复能力，也就降低了热载流子效应对器件性能的影响。
附图说明
图1-图6为现有技术中的半导体结构在形成过程中的结构示意图；
图7为本发明的半导体结构的形成方法的流程图；
图8-11为本发明的半导体结构在形成过程中的结构示意图。
具体实施方式
下面将结合示意图对本发明的半导体结构及其形成方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明的核心思想是，提供一种半导体结构及其形成方法。该方法包括：提供具有虚设栅极的衬底；在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘；去除所述虚设栅极，并在所述虚设栅极处形成包括有栅氧化层的栅极结构，所述氘进入所述栅氧化层中。由此在栅氧化层中引入氘，提高了器件的性能。
下面，请参考图7-图11，对本发明的半导体结构及其形成方法进行详细说明。其中图7为本发明的半导体结构的形成方法的流程图；图8-11为本发明的半导体结构在形成过程中的结构示意图。
请参考图7，并结合图8，所述半导体结构的形成方法，包括：
首先，执行步骤S101，提供具有虚设栅极20的衬底10；所述衬底10的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅等。作为示例，在本实施例中，衬底10选用单晶硅材料构成。在所述衬底10中还可以形成有埋层(图中未示出)等。此外，对于PMOS而言，所述衬底10中还可以形成有N阱(图中未示出)，并且可以对整个N阱进行一次或多次小剂量硼注入，用于调整PMOS的阈值电压Vth。所述虚设栅极20例如包括虚设栅氧化层21，多晶硅块体22，掩膜层23，以及侧墙24等，所述虚设栅极20可以参考现有技术中的后栅极(gatelast)工艺中的常见选择。
在本步骤之后，例如还包括对衬底进行清洗等常规过程，此处不进行详述。
接着，如图9所示，执行步骤S102，在所述衬底10中虚设栅极20两侧形成源漏区域30，所述源漏区域30掺杂有氘31；具体的，该步骤包括刻蚀所述衬底10位于虚设栅极20两侧的区域形成沟槽，例如采用干法刻蚀，形成Σ状沟槽或U状沟槽，作为示例，本实施例形成的是Σ状沟槽；待所述沟槽形成后，利用均匀气相外延沉积(Homogeneous vapor phaseepitaxial deposition)工艺在所述沟槽中形成掺杂有氘31的源漏区域30。所述源漏区域30可以是包括有硅锗外延层或者硅碳外延层，从而改善器件性能。所述氘31则是掺杂于所述硅锗外延层或者硅碳外延层中。其中，所述均匀气相外延沉积工艺包括利用第一源气及第二源气形成所述掺杂有氘的源漏区域。优选的，所述第一源气占据的体积比为50％-90％。所述第一源气为氘气，或者是氘气和氢气的混合气体，在所述混合气体中，氘气占据的体积比为2％-98％。所述第二源气包括SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4、Si(CH3)4、GeH4,C3H8、CH4中的至少一种或组合。在所述均匀气相外延沉积工艺中，优选的，反应温度为800℃-1100℃，持续时间为10-2000分钟。
依据实际需求，可以对反应气体的含量、反应温度及时间进行灵活调整，以获得符合工艺需求的源漏区域30。
之后，请参考图10和图11，执行步骤S103，去除所述虚设栅极，并在所述虚设栅极处形成包括有栅氧化层41的栅极结构40，所述氘31进入所述栅氧化层41中。具体的，可以是将所述虚设栅极20中的虚设栅氧化层21，多晶硅块体22，掩膜层23去除，去除过程可以是利用光刻胶覆盖除虚设栅极20外的其他区域，经过湿法刻蚀完成去除。待虚设栅氧化层21，多晶硅块体22，掩膜层23去除后，在500℃-1150℃下，重新形成栅氧化层41，以及栅氧化层41上的栅极块体42，例如包括高K介质层，金属栅极等，从而获得最终的栅极结构40。在栅氧化层41的形成时，位于源漏外延层30中的氘31，由于高温作用，同时扩散进入了栅氧化层41中，且将聚集在界面处，则在栅极结构40形成后，由于氘31的存在，在界面处形成了稳固的Si-D共价键。
请继续参考图11，经由上述步骤，本发明获得一种半导体结构，包括：
衬底10；
形成于所述衬底10上的栅极结构40，所述栅极结构40包括栅氧化层41，所述栅氧化层41中掺杂有氘31；
形成于所述衬底10中栅极结构40两侧的源漏区域30，所述源漏区域30掺杂有氘31。
由上述过程获得的半导体结构，由于在栅氧化层41的界面处形成了共价键，因此能够降低悬空键的影响；并且由于共价键的存在，提高了器件在面对热载流子效应时的恢复能力，也就降低了热载流子效应对器件性能的影响。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

1.一种半导体结构的形成方法，包括：
提供具有虚设栅极的衬底；
在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘；
去除所述虚设栅极，并在所述虚设栅极处形成包括有栅氧化层的栅极结构，所述氘进入所述栅氧化层中。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，在所述衬底中虚设栅极两侧形成源漏区域，所述源漏区域掺杂有氘这一步骤包括：
刻蚀所述衬底位于虚设栅极两侧的区域形成沟槽；
利用均匀气相外延沉积工艺在所述沟槽中形成掺杂有氘的源漏区域。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述沟槽为Σ状沟槽或U状沟槽，所述源漏区域包括硅锗外延层或者硅碳外延层，所述氘掺杂于所述硅锗外延层或者硅碳外延层中。
4.如权利要求2所述的半导体结构的形成方法，其特征在于，所述均匀气相外延沉积工艺包括利用第一源气及第二源气形成所述掺杂有氘的源漏区域。
5.如权利要求4所述的半导体结构的形成方法，其特征在于，所述第一源气占据的体积比为50％-90％。
6.如权利要求5所述的半导体结构的形成方法，其特征在于，所述第一源气为氘气，或者是氘气和氢气的混合气体，在所述混合气体中，氘气占据的体积比为2％-98％。
7.如权利要求4所述的半导体结构的形成方法，其特征在于，所述第二源气包括SiH4、Si2H6、SiH2Cl2、SiHCl3、SiCl4、Si(CH3)4、GeH4、C3H8、CH4中的至少一种或组合。
8.如权利要求2所述的半导体结构的形成方法，其特征在于，所述均匀气相外延沉积工艺的温度为800℃-1100℃，持续时间为10-2000分钟。
9.一种由如权利要求1-8中任意一项所述的半导体结构的形成方法获得的半导体结构，包括：
衬底；
形成于所述衬底上的栅极结构，所述栅极结构包括栅氧化层，所述栅氧化层中掺杂有氘；
形成于所述衬底中栅极结构两侧的源漏区域，所述源漏区域掺杂有氘。
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