CN106569040B - Single event transient pulse width measurement circuit, integrated circuit and electronic equipment - Google Patents
Single event transient pulse width measurement circuit, integrated circuit and electronic equipment Download PDFInfo
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- CN106569040B CN106569040B CN201610971907.1A CN201610971907A CN106569040B CN 106569040 B CN106569040 B CN 106569040B CN 201610971907 A CN201610971907 A CN 201610971907A CN 106569040 B CN106569040 B CN 106569040B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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Abstract
The present invention relates to electric pulse width measurement technical field, it is related to the input terminal that a kind of single event transient pulse width measurement circuit includes latch cicuit and is connect with measured signal input terminal；The first input end and the second input terminal of first order delayed latch circuit at least one level delayed latch circuit are connect with measured signal input terminal；When single event transient pulse width measurement circuit includes the delayed latch circuit of second level or more, the first input end of every grade of delayed latch circuit is connect with the first output end of previous stage delayed latch circuit since the delayed latch circuit of the second level, and the second input terminal of every grade of delayed latch circuit is connect with measured signal input terminal；After measured signal input terminal accesses single-particle transient to be measured, latch cicuit overturning driving at least one level delayed latch circuit overturning, using the second output terminal of each delayed latch circuit in the output end of latch cicuit and at least one level delayed latch circuit as the signal output end of single event transient pulse width measurement circuit.
Description
Technical field
The present invention relates to electric pulse width measurement technical field more particularly to single event transient pulse width measurement circuit,
Integrated circuit and electronic equipment.
Background technique
With the development of the fields such as space flight, military affairs technology, more and more integrated circuit needs work under radiation environment.
Radiation is broadly divided into two major classes to the effect of integrated circuit: single particle effect and total dose effect, and total dose effect is integrated electricity
Road is in radiation effect in radiation environment for a long time and accumulates generated effect, and single particle effect is that the entrance of radiation energy particle is integrated
Effect caused by radiation effect instant effect after circuit.Wherein single particle effect can be subdivided into following three classes: single-particle soft error
Accidentally effect, the effect and single hard error effect of potentially dangerous property.
Wherein, single-particle soft error effects include Single Event Upset effect, single-event transients effect, and single-particle overturns effect more
It should wait, interference can be generated to circuit node in a short time.The effect of potentially dangerous property includes single event latch-up effect
It should wait, if not being controlled, may result in chip and single event burnout occurs.Single hard error effect includes displacement damage
Deng meeting is so that the transistor in chip cannot thoroughly work.And single-event transients effect is common influence chip performance
Principal element, in the environment that chip is placed on radiation, ambient energy particle can be injected into chip interior, pass through ionising radiation
Electronics, the hole pair of certain amount are generated on the motion profile of energy particle, they are inhaled under the action of electric field by circuit node
It receives, concept transfer level, if without feedback loop, after the time of single-particle effect, the node level meeting again
It is restored back to original value, to generate a pulse signal in circuit.
Single particle effect is studied and is reinforced, it is necessary to effective test environment is built, it is wide to transient pulse signal
The features such as degree are accurately measured.Wherein, test environment often selects ground irradiation experiment, generates cosmic ray grain by simulation
Son carries out bombardment test to chip to be measured, simulates true cosmic space radiation environment.It is measured to pulse signal width
When, according to differences such as incoming particle type energy, the single-particle pulse signal level of generation is held time also different, pulse width
It can be from tens ps to 1,000 ps or more.
If single event transient pulse width is measured using detection devices such as traditional oscillographs or logic analyser, to setting
Standby frequency requirement is very high, and testing cost is high, realizes that difficulty is very big.It is existing if tested using on-chip circuit
Pulse width measuring method measures pulse signal sampling often through external input high-frequency signal, and acquisition accuracy will be by
Frequency and performance to sampled signal limit, again very excellent due to being difficult to provide very high frequency, wave characteristics in actual test
Sampled signal it is small therefore can to survey range.
Summary of the invention
The present invention solves existing by providing single event transient pulse width measurement circuit, integrated circuit and electronic equipment
Have single event transient pulse width measurement circuit in technology surveys the small technical problem of range.
The embodiment of the invention provides a kind of single event transient pulse width measurement circuit, including measured signal input terminal,
Latch cicuit and at least one level delayed latch circuit；
The input terminal of the latch cicuit is connect with the measured signal input terminal；
The first input end of first order delayed latch circuit in at least one level delayed latch circuit and the second input
End is connect with the measured signal input terminal；
When the single event transient pulse width measurement circuit includes the delayed latch circuit of second level or more, from the second level
Delayed latch circuit starts, the first input end of every grade of delayed latch circuit and the first output end of previous stage delayed latch circuit
Connection, the second input terminal of every grade of delayed latch circuit are connect with the measured signal input terminal；
Wherein, after the measured signal input terminal accesses single-particle transient to be measured, the single-particle to be measured
Transient pulse signal driving at least one level delayed latch circuit is sequentially flipped, by the output end of the latch cicuit and described
The second output terminal of each delayed latch circuit is as the single event transient pulse width at least one level delayed latch circuit
The signal output end of measuring circuit.
Preferably, the latch cicuit be two input RS latch, it is described two input RS latch set input with
The measured signal input terminal connection.
Preferably, the delayed latch circuit includes delay sub-circuit and latches sub-circuit, described to postpone the defeated of sub-circuit
Outlet with it is described latch sub-circuit the first set input connect, it is described latch sub-circuit the second set input with it is described
Measured signal input terminal connection.
Preferably, the delay sub-circuit is made of the cascade of even level reverser.
Preferably, the latch sub-circuit is three input RS latch.
Preferably, the reset terminal of the reset terminal of the latch cicuit and all delayed latch circuits accesses same reset letter
Number.
Based on the same inventive concept, the embodiment of the invention also provides a kind of integrated circuits, including simple grain as described above
Sub- transient pulse width measurement circuit.
Based on the same inventive concept, the embodiment of the invention also provides a kind of electronic equipment, including integrate as described above
Circuit.
One or more technical solutions in the embodiment of the present invention, have at least the following technical effects or advantages:
In the present invention, after measured signal input terminal accesses single-particle transient to be measured, single-particle wink to be measured
State pulse signal driving at least one level delayed latch circuit is sequentially flipped, and the output end of latch cicuit and at least one level are prolonged
The output end of each delayed latch circuit is exported as the signal of single event transient pulse width measurement circuit in slow latch cicuit
End, according to the height of the level of each signal output end, counter can release the pulse width of single-particle transient to be measured,
Series by increasing delayed latch circuit can expand the range of measuring signal, and measurement range is wide, also, by changing delay
The delay time of latch cicuit, i.e., adjustable corresponding measuring accuracy at different levels meet the different of delayed latch circuit not at the same level and survey
Examination requires, in addition, the present invention does not need external input clock signal, so the not requirement to external input clock signal.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the electrical block diagram of single event transient pulse width measurement circuit in first embodiment of the invention；
Fig. 2 is the electrical block diagram of single event transient pulse width measurement circuit in second embodiment of the invention；
Waveform diagram when Fig. 3 is single event transient pulse width measurement circuit work in the embodiment of the present invention；
Fig. 4 is the electrical block diagram of two input RS latch in the embodiment of the present invention；
Fig. 5 is the electrical block diagram of three input RS latch in the embodiment of the present invention；
Fig. 6 is the electrical block diagram for postponing sub-circuit in the embodiment of the present invention.
Wherein, 100 be latch cicuit, and 101 be delayed latch circuit, and 1011 is latch sub-circuit, and 1012 be delay son electricity
Road, 11 be the first PMOS tube, and 12 be the second PMOS tube, and 13 be third PMOS tube, and 14 be the 4th PMOS tube, and 15 be the 5th PMOS
Pipe, 16 be the 6th PMOS tube, and 17 be the 7th PMOS tube, and 18 be the 8th PMOS tube, and 19 be the 9th PMOS tube, and 21 be the first NMOS
Pipe, 22 be the second NMOS tube, and 23 be third NMOS tube, and 24 be the 4th NMOS tube, and 25 be the 5th NMOS tube, and 26 be the 6th NMOS
Pipe, 27 be the 7th NMOS tube, and 28 be the 8th NMOS tube, and 29 be the 9th NMOS tube, and 31 be the tenth PMOS tube, and 32 be the 11st PMOS
Pipe, 41 be the tenth NMOS tube, and 42 be the 11st NMOS tube.
Specific embodiment
The small technical problem of range, this hair are surveyed to solve single event transient pulse width measurement circuit in the prior art
Bright offer single event transient pulse width measurement circuit, integrated circuit and electronic equipment.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of single event transient pulse width measurement circuit, as shown in Figure 1, the single-ion transient state
Pulse width measurement circuit includes including measured signal input terminal, latch cicuit 100 and at least one level delayed latch circuit 101.
The input terminal of latch cicuit 100 is connect with measured signal input terminal, the first order delay at least one level delayed latch circuit 101
The first input end of latch cicuit and the second input terminal are connect with measured signal input terminal, when single event transient pulse width is surveyed
When amount circuit includes the delayed latch circuit 101 of second level or more, since the delayed latch circuit of the second level, every grade of delayed latch electricity
The first input end on road is connect with the first output end of previous stage delayed latch circuit 101, and the second of every grade of delayed latch circuit
Input terminal is connect with measured signal input terminal.
In the present invention, after measured signal input terminal accesses single-particle transient to be measured, single-particle wink to be measured
State pulse signal driving at least one level delayed latch circuit 101 is sequentially flipped, by the output end of latch cicuit 100 and at least
The second output terminal of each delayed latch circuit 101 is wide as the single event transient pulse in level-one delayed latch circuit 101
Spend the signal output end of measuring circuit.According to the height of the level of each signal output end, single-particle wink to be measured counter can be released
The pulse width of state pulse signal, wherein delayed latch circuit can be arranged according to actual measurement demand in those skilled in the art
The series of 101 series, delayed latch circuit 101 is bigger, and the range of measuring signal is also bigger, also, by changing delay lock
It deposits the delay time of circuit 101, i.e., adjustable corresponding measuring accuracy at different levels meets delayed latch circuit 101 not at the same level not
Same test request, in addition, the present invention does not need external input clock signal, so not wanting to external input clock signal
It asks.
In a kind of specific embodiment of the invention, as shown in Fig. 2, latch cicuit 100 can latch for two input RS
Device, two input RS latch include set input (end S), the RESET input (end R), Q output andOutput end, two inputs
The set input of RS latch is connect with measured signal input terminal, and the Q output of latch cicuit 100 is single event transient pulse
The signal output end of width measurement circuit.
Delayed latch circuit 101 in the present invention includes delay sub-circuit 1012 and latch sub-circuit 1011.The first order is prolonged
The input terminal of the delay sub-circuit 1012 of slow latch cicuit is connect with measured signal input terminal, and first order delayed latch circuit prolongs
The output end of slow sub-circuit 1012 is connect with the first input end of the latch sub-circuit 1011 of first order delayed latch circuit, and first
Second input terminal of the latch sub-circuit 1011 of grade delayed latch circuit is connect with the measured signal input terminal.Prolong from the second level
Slow latch cicuit starts, the input terminal and previous stage delayed latch circuit 101 of the delay sub-circuit 1012 of delayed latch circuit 101
Delay sub-circuit 1012 output end connection, the output end of the delay sub-circuit 1012 of every grade of delayed latch circuit prolongs with the grade
The first input end connection of the latch sub-circuit 1011 of slow latch cicuit 101, the latch sub-circuit of every grade of delayed latch circuit
1011 the second input terminal is connect with the measured signal input terminal.
Further, latching sub-circuit 1011 can be three input RS latch, and three input RS latch include the first set
Input terminal (end S1), the second set input (end S2), the RESET input (end R), Q output andOutput end.Specifically, should
Three input RS latch are the three input basic RS latch of nor gate.There are two stable states for three input RS latch tools, defeated
In the case where entering the signal maintenance sufficiently long time, it is steady that three input RS latch can be turned to another from a stable state
Determine state, output signal level changes.For example, when the input signal of three input terminals of three input RS latch becomes
Change, and maintain enough for a long time, the output level of three input RS latch will to be caused to change, specifically, as three input RS
When the first set input and the second set input of latch are not all high level, the Q output of three input RS latch
For low level,Output end is high level, when the RESET input of three input RS latch is low level, the first set input
When being high level with the second set input, Q output is high level,Output end is low level, when three input RS are latched
When the RESET input of device is that low level, the first set input and the second set input are not all high level, Q output
WithOutput end level remains unchanged.
Further, the input terminal of the delay sub-circuit 1012 of first order delayed latch circuit and measured signal input terminal connect
It connects, the output end of the delay sub-circuit 1012 of first order delayed latch circuit and the latch sub-circuit of first order delayed latch circuit
1011 the first set input connection, first order delayed latch circuit latch sub-circuit 1011 the second set input with
The connection of measured signal input terminal.Since the delayed latch circuit of the second level, the delay sub-circuit 1012 of every grade of delayed latch circuit
Input terminal connect with the output end of the delay sub-circuit 1012 of previous stage delayed latch circuit 101, every grade of delayed latch circuit
Delay sub-circuit 1012 output end and the latch sub-circuit 1011 of this grade of delayed latch circuit 101 the first set input
Connection, the second set input of the latch sub-circuit 1011 of every grade of delayed latch circuit are connect with measured signal input terminal.
By the Q output for latching sub-circuit 1011 each in the Q output of latch cicuit 100 and at least one level delayed latch circuit 101
Signal output end as single event transient pulse measuring circuit.In the present invention, delay sub-circuit 1012 can be by even level
Reverser cascade is constituted.
It in the present invention, is guarantee latch cicuit 100 and delayed latch circuit 101 in single-particle transient to be measured
Stable state, the reset terminal access of the reset terminal of latch cicuit 100 and all delayed latch circuits 101 are able to maintain that before variation
Same reset signal, that is, RESET, all latch cicuits 100 are resetted at unified RESET.
The present invention will be in conjunction with a specific input signal, to single event transient pulse width measurement circuit of the invention below
Working principle is described in detail, wherein and single event transient pulse width measurement circuit includes 3 grades of delayed latch circuits 101,
Input is single-particle transient to be measured, and out1 is the signal that the output end of latch cicuit 100 exports, out2 first
The signal of the output end output of grade delayed latch circuit, out3 are the signal that the output end of second level delayed latch circuit exports,
Out4 is the signal that the output end of third level delayed latch circuit 101 exports, each in single event transient pulse width measurement circuit
The work wave of signal is referring to Fig. 3.
Specifically, during the work time, under original state, all latch cicuits 100 are resetted at unified RESET,
The input of measured signal input terminal input at this time is low level, and the signal of the reset terminal input of all latch cicuits 100 is high electricity
Flat, the signal of the output end output of all latch cicuits 100 is 0, that is, out1, out2, out3, out4 and out5 are 0.In t
When=20.5ns, input keeps low level constant, and RESET becomes low level, the signal that all latch cicuits 100 export at this time
It remains unchanged, that is, out1, out2, out3, out4 and out5 are 0.In t=50ns, input generates a pulsewidth and is
The high level pulse of 200ps, by emulation it is found that the high level pulse is enough that latch cicuit 100 is driven to overturn, so that out1 becomes
For high level.
Wherein, input drives the delay sub-circuit 1012 in first order delayed latch circuit, the delay sub-circuit simultaneously
The signal in2 ratio input of 1012 output ends output postpones Δ t2, and therefore, in2 and input is that will compare the period of high level
Input is the period short Δ t2 of high level, but Δ t2 still is able to meet the latch in driving first order delayed latch circuit
Sub-circuit 1011 overturns required minimum time requirement, therefore the latch sub-circuit 1011 in first order delayed latch circuit occurs
Overturning, so that out2 becomes high level.And the letter of delay 1012 output end of the sub-circuit output in the delayed latch circuit of the second level
Number in3 ratio in2 postpones the delay time Δ t3 of the delay sub-circuit 1012 in a second delayed latch circuit 101, therefore,
In3 and input is the time of high level will be Δ t2+ Δ t3 shorter than the time that input is high level.Emulation shows this time
It has been not enough to drive the latch sub-circuit 1011 in third level delayed latch circuit 101 to overturn, therefore out4 is low level, therefore,
It is 0 that out3 and input signal are the period of high level simultaneously, therefore the latch sub-circuit in fourth stage delayed latch circuit 101
1011 can not also be flipped.
Analysis shows, since first order delayed latch circuit, latch in delayed latch circuits 101 at different levels is electric above
First set input and the second set input on road 1011 are that will successively decrease step by step the time of high level simultaneously, until becoming 0.
And input that input signal pulse width is wider, i.e., input signal remain high level time it is longer, will drive more
More latch are flipped, so that the signal number being flipped in out2 ..., outn is more.
In the present invention, by changing input pulse width, using the output of circuit simulation observation various stage latches circuit 100
Correspondence table of the input pulse width with output signal logic level can be obtained in situation, referring to the following table 1, in actual measurement,
It can be counter to release single-particle wink to be measured according to the overturning situation of the latch cicuit 100 detected in actual measurement, according to the following table 1
The pulse width of state pulse signal.
Table 1
Below by the delay son electricity in the circuit structure and delayed latch circuit 101 to the latch cicuit 100 in the present invention
The circuit structure on road 1012 is described in detail:
In the present invention, two input RS latch are nor gate RS latch, as shown in figure 4, two input RS latch packets
Include the first PMOS tube 11, the second PMOS tube 12, third PMOS tube 13, the 4th PMOS tube 14, the first NMOS tube 21, the second NMOS tube
22, third NMOS tube 23 and the 4th NMOS tube 24.The source terminal of first PMOS tube 11 and the source terminal difference of third PMOS tube 13
It connects to power supply, the gate terminal of the gate terminal of the first PMOS tube 11 and the first NMOS tube 21 inputs answering for RS latch with two respectively
The connection of position end, the drain electrode end of the first PMOS tube 11 are connect with the source terminal of the second PMOS tube 12, the gate terminal of the second PMOS tube 12
RS latch are inputted with two respectively with the gate terminal of the second NMOS tube 22Output end connection, the drain electrode end of the first NMOS tube 21
The first connecting node between the drain electrode end of the second NMOS tube 22 is connect with the drain electrode end of the second PMOS tube 12, the first connection section
Point is also connect with the Q output of two input RS latch, the gate terminal of third PMOS tube 13 and the gate terminal of third NMOS tube 23
It is connect respectively with the set end of two input RS latch, the source terminal of the drain electrode end of third PMOS tube 13 and the 4th PMOS tube 14 connects
It connects, the Q output of the gate terminal of the 4th PMOS tube 14 and the gate terminal of the 4th NMOS tube 24 respectively with two input RS latch connects
It connects, the leakage of the second connecting node between the drain electrode end of third CMOS tube and the drain electrode end of the 4th CMOS tube and the 4th PMOS tube 14
Extreme connection, the second connecting node also input RS latch with twoOutput end connection, the source terminal of the first NMOS tube 21, the
The source terminal of the source terminal of two NMOS tubes 22, the source terminal of third NMOS tube 23 and the 4th NMOS tube 24 is grounded respectively.
Wherein, the width of all PMOS tube is 1.92 microns in above-mentioned two inputs RS latch, and length is 0.13 micro-
Rice, the width of all NMOS tubes is 0.64 micron, and length is 0.13 micron.
Certainly, two input RS latch can also be using other two inputs with signal turn over function in addition to Fig. 4
RS flip-latch circuit structure, the application is without limitation.
In the present invention, three input RS latch can have circuit structure as shown in Figure 5, three input RS latch packets
Include the 5th PMOS tube 15, the 6th PMOS tube 16, the 7th PMOS tube 17, the 8th PMOS tube 18, the 9th PMOS tube 19, the 5th NMOS tube
25, the 6th NMOS tube 26, the 7th NMOS tube 27, the 8th NMOS tube 28 and the 9th NMOS tube 29, the source terminal of the 5th PMOS tube 15,
The source terminal of 6th PMOS tube 16 and the source terminal of the 7th PMOS tube 17 connect to power supply respectively, the gate terminal of the 5th PMOS tube 15
With the gate terminal of the 5th NMOS tube 25 respectively with three input RS latch reset terminal connect, the drain electrode end of the 5th PMOS tube 15 and
The source terminal of 8th PMOS tube 18 connects, and the gate terminal of the 6th PMOS tube 16 and the gate terminal of the 7th NMOS tube 27 are defeated with three respectively
Enter the first set end connection of RS latch, the gate terminal of the gate terminal of the 7th PMOS tube 17 and the 9th NMOS tube 29 is respectively with three
The the second set end connection for inputting RS latch, between the drain electrode end of the 7th PMOS tube 17 and the source terminal of the 9th PMOS tube 19
Third connecting node is connect with the drain electrode end of the 6th PMOS tube 16, the gate terminal of the 8th PMOS tube 18 and the grid of the 6th NMOS tube 26
Extremely RS latch are inputted with three respectivelyOutput end connection, the leakage of the drain electrode end, the 5th NMOS tube 25 of the 8th PMOS tube 18
The 4th connecting node extremely between the drain electrode end of the 6th NMOS tube 26 is connect with the Q output of three input RS latch, the
The 5th connection section between the drain electrode ends of nine PMOS tube 19, the drain electrode end of the 7th NMOS tube 27 and the drain electrode end of the 8th NMOS tube 28
Point and three input RS latchThe gate terminal difference that output end connection, the gate terminal of the 9th PMOS tube 19 and the 8th NMOS are closed
It being connect with the Q output of three input RS latch, the source terminal of the 7th NMOS tube 27 is connect with the drain electrode end of the 9th NMOS tube 29,
Source terminal, the source terminal of the 6th NMOS tube 26, the source terminal and the 9th NMOS tube 29 of the 8th NMOS tube 28 of 5th NMOS tube 25
Source terminal be grounded respectively.
Wherein, the width of all PMOS tube is 1.92 microns in above-mentioned three inputs RS latch, and length is 0.13 micro-
Rice, the width of all NMOS tubes is 0.64 micron, and length is 0.13 micron.
Certainly, three input RS latch can also be using other three inputs with signal turn over function in addition to Fig. 5
RS flip-latch circuit structure, the application is without limitation.
In the present invention, delay sub-circuit 1012 can have circuit structure as shown in FIG. 6, and delay sub-circuit 1012 wraps
Include the tenth PMOS tube 31, the 11st PMOS tube 32, the tenth NMOS tube 41 and the 11st NMOS tube 41, the source electrode of the tenth PMOS tube 31
The source terminal of end and the 11st PMOS tube 32 connects to power supply, the source terminal of the tenth NMOS tube 41 and the source of the 11st NMOS tube 42
It is extremely grounded respectively, the connecting node between the gate terminal of the tenth PMOS tube 31 and the gate terminal of the 11st NMOS tube 41 is delay
The input terminal of sub-circuit 1012, the connecting node between 42 drain electrode end of drain electrode end and the 11st NMOS tube of the 11st PMOS tube 32
For the output end for postponing sub-circuit 1012, connection between the drain electrode end of the tenth PMOS tube 31 and the drain electrode end of the tenth NMOS tube 41
Connecting node connection between the gate terminal of the gate terminal and the 11st NMOS tube 42 of node and the 11st PMOS tube 32.
Certainly, delay sub-circuit 1012 can also be using the delay sub-circuit with signal turn over function in addition to Fig. 6
1012 circuit structure, the application is without limitation.
Based on the same inventive concept, the embodiment of the present invention also provides a kind of integrated circuit, including single-particle as described above
Transient pulse width measurement circuit, for single event transient pulse width measurement circuit structure referring to a upper embodiment, herein
It repeats no more.
Based on the same inventive concept, the embodiment of the present invention also provides a kind of electronic equipment, includes integrated electricity as described above
Road.
Technical solution in above-mentioned the embodiment of the present application, at least have the following technical effects or advantages:
In the present invention, after measured signal input terminal accesses single-particle transient to be measured, single-particle wink to be measured
State pulse signal driving at least one level delayed latch circuit is sequentially flipped, and the output end of latch cicuit and at least one level are prolonged
The output end of each delayed latch circuit is exported as the signal of single event transient pulse width measurement circuit in slow latch cicuit
End, according to the height of the level of each signal output end, counter can release the pulse width of single-particle transient to be measured,
Series by increasing delayed latch circuit can expand the range of measuring signal, and measurement range is wide, also, by changing delay
The delay time of latch cicuit, i.e., adjustable corresponding measuring accuracy at different levels meet the different of delayed latch circuit not at the same level and survey
Examination requires, in addition, the present invention does not need external input clock signal, so the not requirement to external input clock signal.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (6)
1. a kind of single event transient pulse width measurement circuit, which is characterized in that including measured signal input terminal, latch cicuit and
Multilevel delay latch cicuit, every grade of delayed latch circuit include delay sub-circuit and latch sub-circuit；
The input terminal of the latch cicuit is connect with the measured signal input terminal, and the latch cicuit is that two input RS are latched
The set input of device, the two inputs RS latch is connect with the measured signal input terminal；
The input terminal of the delay sub-circuit of first order delayed latch circuit in the multilevel delay latch cicuit with it is described to be measured
Signal input part connection, the output end and the first order delayed latch of the delay sub-circuit of the first order delayed latch circuit
The first set input connection of the latch sub-circuit of circuit, the second of the latch sub-circuit of the first order delayed latch circuit
Set input is connect with the measured signal input terminal；
In the multilevel delay latch cicuit, since the delayed latch circuit of the second level, prolonging in every grade of delayed latch circuit
The input terminal of slow sub-circuit is connect with the output end of the delay sub-circuit in previous stage delayed latch circuit, every grade of delayed latch electricity
The output end of delay sub-circuit in road is connect with the first set input of the latch sub-circuit in this grade of delayed latch circuit,
Second set input of the latch sub-circuit in every grade of delayed latch circuit is connect with the measured signal input terminal；
Wherein, after the measured signal input terminal accesses single-particle transient to be measured, the single-ion transient state to be measured
Pulse signal drives the multilevel delay latch cicuit to be sequentially flipped, by the Q output of the latch cicuit and described more
The Q output of the latch sub-circuit of each delayed latch circuit is wide as the single event transient pulse in grade delayed latch circuit
Spend the signal output end of measuring circuit.
2. single event transient pulse width measurement circuit as described in claim 1, which is characterized in that the delay sub-circuit by
The cascade of even level reverser is constituted.
3. single event transient pulse width measurement circuit as described in claim 1, which is characterized in that the latch sub-circuit is
Three input RS latch.
4. single event transient pulse width measurement circuit as described in claim 1, which is characterized in that the latch cicuit is answered
The reset terminal of position end and all delayed latch circuits accesses same reset signal.
5. a kind of integrated circuit, which is characterized in that including the single-ion transient state as described in any claim in claim 1-4
Pulse width measurement circuit.
6. a kind of electronic equipment, which is characterized in that including integrated circuit as claimed in claim 5.
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| CN108233904B (en) * | 2018-01-09 | 2021-11-16 | 中国科学院微电子研究所 | Anti-transient effect gate |
| CN112422116A (en) | 2019-08-23 | 2021-02-26 | 长鑫存储技术有限公司 | Multi-stage driving data transmission circuit and data transmission method |
| CN111487472B (en) * | 2020-03-31 | 2022-08-05 | 北京时代民芯科技有限公司 | Circuit structure for measuring single-particle transient pulse width |
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| CN102818939A (en) * | 2011-06-08 | 2012-12-12 | 中国科学院微电子研究所 | Measuring circuit for single-event transient pulse width |
| CN103063933A (en) * | 2011-10-20 | 2013-04-24 | 中国科学院微电子研究所 | Measuring circuit of single-particle pulse width |
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| CN102981063B (en) * | 2012-11-13 | 2015-09-16 | 工业和信息化部电子第五研究所 | Single event transient pulse method for measuring width and measurement mechanism, pulse generating device |
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