CN106405385B - Logic circuit single particle effect test method based on chain of flip-flops - Google Patents
Logic circuit single particle effect test method based on chain of flip-flops Download PDFInfo
- Publication number
- CN106405385B CN106405385B CN201610793863.8A CN201610793863A CN106405385B CN 106405385 B CN106405385 B CN 106405385B CN 201610793863 A CN201610793863 A CN 201610793863A CN 106405385 B CN106405385 B CN 106405385B
- Authority
- CN
- China
- Prior art keywords
- chain
- flip
- flops
- trigger
- particle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002245 particle Substances 0.000 title claims abstract description 102
- 230000000694 effects Effects 0.000 title claims abstract description 43
- 238000010998 test method Methods 0.000 title claims abstract description 15
- 238000002474 experimental method Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 14
- 230000003071 parasitic effect Effects 0.000 claims abstract description 12
- 230000001052 transient effect Effects 0.000 claims abstract description 10
- 238000013461 design Methods 0.000 claims abstract description 8
- 238000000605 extraction Methods 0.000 claims abstract description 7
- 230000008569 process Effects 0.000 claims abstract description 6
- 230000005855 radiation Effects 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims description 17
- 230000007306 turnover Effects 0.000 claims description 11
- 238000004088 simulation Methods 0.000 claims description 8
- 238000005259 measurement Methods 0.000 claims description 7
- 230000000737 periodic effect Effects 0.000 claims description 5
- 230000007704 transition Effects 0.000 claims description 3
- 235000013399 edible fruits Nutrition 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims description 2
- 238000011156 evaluation Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to a kind of logic circuit single particle effect test method based on chain of flip-flops.It includes the next steps: multistage number chain of flip-flops 1] being designed based on some process node；2] layout design is carried out to chain of flip-flops, then carries out domain parasitic parameter extraction；3] single particle effect experiment is carried out using the radiation source of some heavy ion LET value；4] the SEU cross section ratio ∈ of trigger master-slave latch is obtained by clock signal；5] the time-sensitive factor TVF of the trigger single-particle inversion under different frequency is calculated by following equation；6] pass through step 3] and step 5] obtain soft error section caused by combinatorial logic unit single-ion transient state in multistage chain of flip-flops；Then linear fit is carried out to experimental result.A kind of test method of the single particle effect of logic circuit the present invention provides accurate evaluation based on chain of flip-flops.
Description
Technical field
The present invention relates to a kind of logic circuit single particle effect test method more particularly to a kind of patrolling based on chain of flip-flops
Collect circuit single particle effect test method.
Background technique
Electronic system of many high energy particles present in space and high-energy physics experiment to work in these environment
There is serious reliability to threaten.Single particle effect therein is to the reliability effect of integrated circuit with integrated circuit technology node
Raising become increasingly severe.Single-particle in timing units such as triggers had both been occurred for the logic circuit in microprocessor
Overturning influences, and the threat in the single-ion transient state of combinatorial logic unit is also occurred.
With the raising of integrated circuit technology node, the working frequency of logic circuit is continuously increased, and pipelining is patrolled
It collects depth also increasing, that is, has the trigger of more stages on the same logical path.This trend leads to the simple grain of trigger
Son overturning is influenced to become serious by time screen effect, and has frequency dependence.At the same time, the combination of logic circuit
Window screening effect of the single-ion transient state effect of logic due to being toggled device, it may have frequency dependence itself.This just leads
Cause the soft error that two kinds of single particle effects generate at different frequencies that can not directly distinguish due to all having frequency dependence
Come, brings difficulty to the single particle effect experiment test and analysis of logic circuit.On experimental study, select with combinational logic
Multistage number chain of flip-flops is represented as logic circuit, not only can reflect the structure of general logic circuit, but also can be reduced experiment
The difficulty of test.Therefore the logic circuit single particle effect test based on chain of flip-flops and the accurate analysis of experimental result have generation
Table also has great importance.
Due to the inherent delay of trigger and the logical delay of combinatorial logic unit, the output signal of prime trigger needs
It could be received and be saved by rear class trigger on appropriate clock edge after the regular hour postpones.In permitting for chain of flip-flops
Perhaps within the scope of working clock frequency, the signal of chain of flip-flops input can be transmitted to rear class trigger from prime trigger, not have
There is the fault in timing, i.e. trigger settling time breaks rules.But since single-particle inversion can within a clock cycle
Any time occurs in certain level-one trigger, it is possible that leading to the signal of certain single-particle inversions because being unable to satisfy next
The settling time of grade trigger requires, i.e. trigger settling time breaks rules and can not be transmitted to next stage trigger, and here it is touchings
Send out the single-particle inversion time screen effect of device.This effect has clock frequency correlation: frequency is higher, trigger single-particle
It overturns that shielded probability is bigger, and is linear variation relation with frequency.However, due to principal and subordinate's grade latch of trigger
It can generally have any different in load end, for example the parasitic capacitance loaded is different, so their SEU cross section is variant；
Principal and subordinate's grade latch is influenced variant in timing by the time screen effect of single-particle inversion simultaneously: as frequency increases
Add, is first gradually shielded from the single-particle inversion of grade latch, after it is thus completely shielded, the single-particle inversion of main latch
Just start gradually to be shielded.Both differences of master-slave latch can make the shielding result of single-particle inversion with the variation of frequency
Turnover is generated at some Frequency point.When the inherent delay time and combinational logic of this frequency turning point and trigger postpone
Between have relationship.
The domestic and international existing logic circuit single particle effect test method based on chain of flip-flops, although having done different frequency
Single particle effect test, but but have ignored the time screen effect of trigger single-particle inversion completely in interpretation of result,
Think that soft error caused by the single-particle inversion of chain of flip-flops is similar to the single-particle under chain of flip-flops is quasi-static or low frequency
Soft error section, without changing with frequency.Total single-particle soft error section under different frequency is subtracted quasi-static knot simultaneously
Fruit obtains the single-particle soft error section of combinational logic under corresponding frequencies.Such as document " Chia-Hsiang Chen, et al.
“Characterization of Heavy-Ion-Induced Single-Event Effects in 65nm Bulk CMOS
ASIC Test Chips”,IEEE Trans Nucl.Sci.,vol.61,no.5,Oct.2014.”。
Summary of the invention
In order to solve the technical problem in the presence of background technology, the invention proposes the logic circuits based on chain of flip-flops
Single particle effect test method solves in existing chain of flip-flops single particle effect measurement and analysis method and does not consider trigger list
The problem of time screen effect and its frequency dependence of particle overturning.Meanwhile it accurately distinguishing combination at different frequencies and having patrolled
Soft error caused by single-ion transient state and trigger single-particle inversion is collected, for combinational logic in experimentally accurate evaluation logic circuit
It is supported with the single-particle sensibility providing method of trigger, realizes logic circuit anti-single particle transient state and single-particle inversion performance
Examination.
The technical solution of the invention is as follows: a kind of logic circuit single particle effect test method based on chain of flip-flops,
It is characterized in that the following steps are included:
1] multistage number chain of flip-flops is designed based on some process node；The multistage number chain of flip-flops includes trigger and group
Logical unit；
2] layout design is carried out to chain of flip-flops, then carries out domain parasitic parameter extraction；The parasitic parameter includes parasitism
Resistance and parasitic capacitance；Then circuit simulation is then carried out to the circuit after extraction parasitic parameter；Select wherein level-one trigger
By emulating the delay time for obtaining trigger settling time Tsetup, trigger input signal and passing to from clock edge transition output
The delay time Tlogic of Tclk_q and wherein level-one combinatorial logic unit；Chain of flip-flops is calculated by formula (1)
The shielding time of trigger single-particle inversion time screen effect and turnover dot frequency；
Tmask=Tlogic+Tsetup+Tclk_q； (1)
The turnover dot frequency is 1/ (2Tmask)；
3] single particle effect experiment is carried out using the heavy ion radiation source of some LET value；Carry out the single-particle of different frequency
The experiment of soft error section gauge, the frequency range of covering is from low to high；
4] by FPGA external equipment modulated periodic signal, two kinds of special low frequency repetition pulse clock signals is obtained and are used for
Measure the main of chain of flip-flops and from grade latch single-particle inversion soft error section；And then obtain trigger master-slave latch
SEU cross section ratio ∈；
Because such special clock had both guaranteed the main latch of trigger or from latch in most of clock
It is sensitive to single-particle inversion in hold mode, while the single-particle inversion soft error of its generation, and clock can be repeated each
The final output end that chain of flip-flops is traveled in period, is detected by external measurement devices；
5] by following equation (2), formula (3) calculate different frequency under trigger single-particle inversion time-sensitive because
Sub- TVF；
When working frequency is less than 1/ (2Tmask),
When working frequency is greater than 1/ (2Tmask),
Chain of flip-flops single-particle inversion at different frequencies turn over equal to the quasi-static of chain of flip-flops by caused soft error section
Turn section multiplied by TVF；
6] pass through step 3] the total single-particle soft error section of multistage chain of flip-flops under the different frequency that measures, then to reality
It tests result and carries out linear fit, just obtained the total single-particle soft error section of chain of flip-flops under different frequency；Firstly the need of sentencing
Whether the frequency of disconnected experiment test has reached turnover dot frequency, if do not reached, is directly fitted；If it exceeds turnover
Dot frequency then needs the section before and after dot frequency of transferring to carry out linear fit respectively.
The total single-particle soft error section of chain of flip-flops under different frequency is subtracted step 5 again] in the triggering that is calculated
Device chain single-particle inversion at different frequencies caused by soft error section, just obtain combinatorial logic unit list in multistage chain of flip-flops
Soft error section caused by particle transient state；
Step 2] described in trigger include main latch and from grade latch；The trigger further includes clock input
End and data input pin and a data output end；When clock is low level, main latch is in the open state, input
Data are effective, are in hold mode from latch, input data is invalid；On the contrary, main latch is in when clock is high level
Hold mode, and it is in the open state from latch；The trigger acquires the data of input, data warp at rising edge clock
It crosses certain delay and is transferred to output end；
Step 2] described in combinatorial logic unit include the various types such as chain of inverters and NAND gate chain.
Step 3] it is middle using chip of uncapping.
The invention has the advantages that technical solution provided by the invention may be implemented under some process node, trigger and group
The SEU cross section measurement of logical unit at different frequencies.The technology of the present invention solution Binding experiment and emulation,
The accurate evaluation single particle effect sensibility of the logic circuit based on chain of flip-flops.It can be through the invention logic circuit
Single particle effect experimental evaluation and analysis of experimental results provide technical method support, reinforce for trigger, combinational logic is reinforced
The experimental verification of method provides guarantee.
Detailed description of the invention
Fig. 1 is the principal sketches of the logic circuit single particle effect test method based on chain of flip-flops；
Fig. 2 is 3 grades of chain of flip-flops schematic diagrames；
Fig. 3 is master-slave flip flop schematic diagram；
Fig. 4 is multistage chain of inverters；
Fig. 5 is multistage NAND gate chain；
Fig. 6 is the low frequency repetition pulse signal for measuring trigger master-slave latch single-particle inversion soft error section；
Fig. 7 is that every level-one trigger alpha single-particle that body silicon 40-nm technique multistage chain of flip-flops low-frequency test obtains turns over
Turn section, from latch alpha SEU cross section and main latch alpha SEU cross section figure；
Fig. 8 is under 0.9V operating voltage, and each collection combinational logic alpha of body silicon 40-nm technique multistage chain of flip-flops is mono-
Particle transient state, trigger alpha single-particle inversion and total single-particle soft error section alpha are with frequency variation diagram.
Specific embodiment
The principal sketches of logic circuit single particle effect test method based on chain of flip-flops are as shown in Figure 1, specifically set
It counts as follows:
Step 1. is based on some process node and designs multistage number chain of flip-flops, for example chooses body silicon 40-nm process node.Choosing
The series taken wants enough, such as 1000 grades, and the single-particle sensitivity section to guarantee chain of flip-flops is sufficiently large, to guarantee having
The single-particle soft error miscount for having statistical significance is obtained in the single particle effect experimental period of limit.3 grades of chain of flip-flops schematic diagram
As shown in Fig. 2, including trigger and combinatorial logic unit.The master-slave flip flop of design is as shown in Figure 3.And adjacent trigger it
Between place identical combinatorial logic unit, chain of inverters as shown in Figure 4 or NAND gate chain shown in fig. 5 etc..Combination is patrolled
The scale for collecting unit can correspondingly be chosen according to the needs of experimental study.The upper limiting frequency of chain of flip-flops permission clock work
There is relationship with the delay time of combinatorial logic unit.Delay is bigger, and clock upper limiting frequency is lower.
Step 2. carries out layout design to chain of flip-flops, then carries out domain parasitic parameter extraction, including dead resistance and posts
Raw capacitor.Circuit simulation, i.e. post-simulation are then carried out to the circuit after extraction parasitic parameter.Wherein level-one trigger passes through for selection
Emulation obtains trigger settling time Tsetup, trigger input signal passes to delay time of output from clock edge transition
The delay time Tlogic of Tclk_q and wherein level-one combinatorial logic unit.Due to the trigger and group of the every level-one of chain of flip-flops
Logical unit design is all identical, therefore the simulation result for choosing chain of flip-flops any level can represent every level-one trigger and group
The electric property of logical unit.The shielding time of the trigger single-particle inversion time screen effect of chain of flip-flops is calculated
Tmask=Tlogic+Tsetup+Tclk_q, and turnover dot frequency 1/ (2Tmask).In different circuit voltage or work
Make to carry out duplicate emulation under the conditions of temperature, the value of these electrical parameters at different conditions can be obtained.Table 1 gives one
The trigger shown in Fig. 3 and 20 grades of chain of inverters shown in Fig. 4 make the chain of flip-flops of combinatorial logic unit composition in different works
Make voltage and post-layout simulation results exhibit at room temperature.With the reduction of operating voltage, the shielding time of trigger single-particle inversion increases,
And dot frequency of transferring then correspondingly reduces.
The good chip of step 3. layout design carries out flow, is packaged later using the ceramics that can be uncapped.Utilize certain
The heavy ion radiation source of a LET value carries out single particle effect experiment.The single-particle soft error section gauge for carrying out different frequency is real
It tests, the frequency range of covering is from low to high.The clock frequency of low-frequency test such as 10kHz can be approximated to be quasi-static section and survey
Examination, represents trigger SEU cross section in chain of flip-flops.And high-frequency test takes a series of Frequency points, highest frequency depends on
Highest frequency or chip interior such as phaselocked loop that experiment external equipment such as square wave signal generator can provide etc. can provide upper
Frequency limit rate is also toggled the limitation that device chain itself allows the clock frequency of work certainly.
Step 4. obtains two kinds of special low frequency repetition pulse clock letters by external equipments modulated periodic signals such as FPGA
Number, as shown in fig. 6, the repetition rate of such as 1kHz.One is low levels to account for clock most periods, such as 99% ratio
Example.Remaining fraction of time section, such as 1% are the periodic signals of high frequency, and the quantity in period is not less than multistage number chain of flip-flops
Series.For example, for the special low frequency repetition pulse clock signal of 1kHz, corresponding 1% time is high frequency period letter
Number, it is assumed that the series of multistage number chain of flip-flops is 1000 grades, then the frequency of the high frequency periodic signal of this section 1% at least needs
1000/ (1ms × 1%)=100MHz.It is turned over using the slave latch single-particle of such special clock signal measurement chain of flip-flops
Turn soft error section.Because this clock had both guaranteed that the slave latch of trigger was in hold mode in most of clock, right
Single-particle inversion is sensitive, while the single-particle inversion soft error of its generation, and can repeat travel in the clock cycle each
The final output end of chain of flip-flops, is detected by external measurement devices.On the contrary, another high level accounts for clock most times
The clock signal (602) of section then is used to measure the single-particle inversion soft error section of trigger main latch.In this manner it is possible to
Experimentally measurement obtains the SEU cross section and its ratio ∈ of trigger master-slave latch respectively.Fig. 7 gives body silicon
Every level-one principal and subordinate grade single-particle soft error section latch alpha of 40-nm technique multistage chain of flip-flops and quasi-static alpha are mono-
Particle soft error test result, i.e. trigger SEU cross section.Since the single-particle soft error section standard in trigger is quiet
Clock low and high level respectively accounts for half in state test, so its effective cross-section should be the average value in master-slave latch section.It can be with
The measurement result approximation for finding out that Fig. 7 is provided meets this relationship.
Step 5. consider trigger single-particle inversion time screen effect and its frequency dependence, test in low frequency or
The quasi-static chain of flip-flops single-particle soft error section measured of person, i.e. chain of flip-flops single-particle inversion soft error section is extrapolated to not
Under same frequency.The time screen effect of trigger single-particle inversion is specifically utilized, the trigger list under different frequency is first calculated
The time-sensitive factor TVF of particle overturning: when working frequency is less than 1/ (2Tmask), When working frequency is greater than 1/ (2Tmask), And trigger
Chain at different frequencies single-particle inversion soft error section (i.e. chain of flip-flops single-particle inversion at different frequencies caused by soft error
Accidentally section) the quasi-static upset cross section of chain of flip-flops is equal to multiplied by TVF.
Multistage chain of flip-flops, total single-particle soft error section subtracts step 5 and is calculated step 6. at different frequencies
Chain of flip-flops single-particle inversion at different frequencies caused by soft error section, just obtained in multistage chain of flip-flops combination and patrolled
Collect soft error section caused by unit single-ion transient state.Chain of flip-flops total single-particle soft error at different frequencies in order to obtain
Section needs to carry out linear fit to discrete experimental result obtained in step 3.But before linear fit, reality is first judged
Whether the frequency of test examination has reached turnover dot frequency, if do not reached, is directly fitted；If it exceeds turning point frequency
Rate then needs the section before and after dot frequency of transferring to carry out linear fit respectively.Fig. 8 gives under 0.9V operating voltage, body silicon 40-
Every level-one combinational logic alpha single-ion transient state of nm technique multistage chain of flip-flops, trigger alpha single-particle inversion and total
The single-particle soft error section alpha with frequency variation diagram.Since the clock frequency in experiment test is not above turning point
Frequency (620MHz, as shown in table 1), so total soft error section that Fig. 8 is provided only needs a linear fit section.
Step 7. above embodiment is a preferable embodiment of the invention, but implementation of the invention is not by upper
The example in face limits, such as the selection of trigger type, the selection of combinatorial logic unit, the selection etc. in heavy ion irradiation source.Its
Its any change made without departing from the spirit and principles of the present invention, modification, combination simplification etc., should be included in the present invention
Protection scope within.
The corresponding electrical parameter simulation result (domain under room temperature of the chain of flip-flops of 1:20 grades of combinatorial logic units of table
Post-simulation)
Claims (4)
1. a kind of logic circuit single particle effect test method based on chain of flip-flops, it is characterised in that: the following steps are included:
1] multistage number chain of flip-flops is designed based on some process node；The multistage number chain of flip-flops includes that trigger and combination are patrolled
Collect unit；
2] layout design is carried out to chain of flip-flops, then carries out domain parasitic parameter extraction；The parasitic parameter includes dead resistance
And parasitic capacitance；Then circuit simulation is then carried out to the circuit after extraction parasitic parameter；Wherein level-one trigger passes through for selection
Emulation obtains trigger settling time Tsetup, trigger input signal passes to delay time of output from clock edge transition
The delay time Tlogic of Tclk_q and wherein level-one combinatorial logic unit；Chain of flip-flops is calculated by formula (1)
The shielding time of trigger single-particle inversion time screen effect and turnover dot frequency；
Tmask=Tlogic+Tsetup+Tclk_q； (1)
The turnover dot frequency is 1/ (2Tmask)；
3] single particle effect experiment is carried out using the heavy ion radiation source of some LET value；Carry out the single-particle soft error of different frequency
Accidentally section gauge experiment, the frequency range of covering is from low to high；
4] by FPGA external equipment modulated periodic signal, two kinds of special low frequency repetition pulse clock signals are obtained for measuring
The main of chain of flip-flops and from grade latch single-particle inversion soft error section；And then obtain the simple grain of trigger master-slave latch
Sub- upset cross section ratio ∈；
Because such special clock had both guaranteed the main latch of trigger or had been in most of clock from latch to protect
State is held, it is sensitive to single-particle inversion, while the single-particle inversion soft error of its generation, and the clock cycle can be repeated each
The final output end for inside traveling to chain of flip-flops, is detected by external measurement devices；
5] the time-sensitive factor of the trigger single-particle inversion under different frequency is calculated by following equation (2), formula (3)
TVF；
When working frequency is less than 1/ (2Tmask),
When working frequency is greater than 1/ (2Tmask),
Quasi-static overturning of the caused soft error section equal to chain of flip-flops at different frequencies of the single-particle inversion of chain of flip-flops
Section is multiplied by TVF；
6] pass through step 3] the total single-particle soft error section of multistage chain of flip-flops under the different frequency that measures, then experiment is tied
Fruit carries out linear fit, has just obtained the total single-particle soft error section of chain of flip-flops under different frequency；It is real firstly the need of judgement
Whether the frequency of test examination has reached turnover dot frequency, if do not reached, is directly fitted；If it exceeds turning point frequency
Rate then needs the section before and after dot frequency of transferring to carry out linear fit respectively；
The total single-particle soft error section of chain of flip-flops under different frequency is subtracted step 5 again] in the chain of flip-flops that is calculated
Single-particle inversion at different frequencies caused by soft error section, just obtain combinatorial logic unit single-particle in multistage chain of flip-flops
Soft error section caused by transient state.
2. a kind of logic circuit single particle effect test method based on chain of flip-flops according to claim 1, feature
Be: step 2] described in trigger include main latch and from grade latch；The trigger further includes input end of clock
And data input pin and a data output end；When clock is low level, main latch is in the open state, inputs number
According to effective, it is in hold mode from latch, input data is invalid；On the contrary, main latch, which is in, to be protected when clock is high level
State is held, and it is in the open state from latch；The trigger acquires the data of input at rising edge clock, and data are passed through
Certain delay is transferred to output end.
3. a kind of logic circuit single particle effect test method based on chain of flip-flops according to claim 1, feature
Be: step 2] described in combinatorial logic unit include chain of inverters and NAND gate chain.
4. a kind of logic circuit single particle effect test method based on chain of flip-flops according to claim 1, feature
It is: step 3] it is middle using chip of uncapping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610793863.8A CN106405385B (en) | 2016-08-31 | 2016-08-31 | Logic circuit single particle effect test method based on chain of flip-flops |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610793863.8A CN106405385B (en) | 2016-08-31 | 2016-08-31 | Logic circuit single particle effect test method based on chain of flip-flops |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106405385A CN106405385A (en) | 2017-02-15 |
| CN106405385B true CN106405385B (en) | 2019-03-05 |
Family
ID=58001421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610793863.8A Active CN106405385B (en) | 2016-08-31 | 2016-08-31 | Logic circuit single particle effect test method based on chain of flip-flops |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106405385B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108267679B (en) * | 2017-12-01 | 2019-03-26 | 西安电子科技大学 | Germanium and silicon heterogeneous junction transistors single particle effect test method based on heavy ion microbeam irradiation |
| CN108491296B (en) * | 2018-03-09 | 2019-04-05 | 中国人民解放军国防科技大学 | Method for testing single event upset section of microprocessor |
| US10782343B2 (en) * | 2018-04-17 | 2020-09-22 | Nxp Usa, Inc. | Digital tests with radiation induced upsets |
| CN110119539B (en) * | 2019-04-17 | 2022-12-06 | 西北核技术研究所 | Analysis method for single event upset effect propagation rule of combined logic circuit |
| CN117347839B (en) * | 2023-12-05 | 2024-03-12 | 飞腾信息技术有限公司 | Chip test circuit and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102879730A (en) * | 2012-09-21 | 2013-01-16 | 中国空间技术研究院 | Single event upset characteristic testing method for partially triple modular redundancy reinforced SRAM (static random access memory) type FPGA (field programmable gate array) |
| CN104237685A (en) * | 2014-09-05 | 2014-12-24 | 兰州空间技术物理研究所 | Space single event effect testing method |
| CN104461808A (en) * | 2014-11-06 | 2015-03-25 | 北京空间飞行器总体设计部 | FPGA single-particle soft error impact evaluation method |
| KR20160027912A (en) * | 2014-09-02 | 2016-03-10 | 성균관대학교산학협력단 | Methods and appratus for soft error immunity test in digital integrated circuits |
| CN105811935A (en) * | 2016-03-06 | 2016-07-27 | 中国人民解放军国防科学技术大学 | On-chip SET pulse testing method based on dynamic input vector |
| CN105866659A (en) * | 2016-03-31 | 2016-08-17 | 中国人民解放军国防科学技术大学 | Universal single-particle multi-transient-pulse distribution measurement method |
-
2016
- 2016-08-31 CN CN201610793863.8A patent/CN106405385B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102879730A (en) * | 2012-09-21 | 2013-01-16 | 中国空间技术研究院 | Single event upset characteristic testing method for partially triple modular redundancy reinforced SRAM (static random access memory) type FPGA (field programmable gate array) |
| KR20160027912A (en) * | 2014-09-02 | 2016-03-10 | 성균관대학교산학협력단 | Methods and appratus for soft error immunity test in digital integrated circuits |
| CN104237685A (en) * | 2014-09-05 | 2014-12-24 | 兰州空间技术物理研究所 | Space single event effect testing method |
| CN104461808A (en) * | 2014-11-06 | 2015-03-25 | 北京空间飞行器总体设计部 | FPGA single-particle soft error impact evaluation method |
| CN105811935A (en) * | 2016-03-06 | 2016-07-27 | 中国人民解放军国防科学技术大学 | On-chip SET pulse testing method based on dynamic input vector |
| CN105866659A (en) * | 2016-03-31 | 2016-08-17 | 中国人民解放军国防科学技术大学 | Universal single-particle multi-transient-pulse distribution measurement method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106405385A (en) | 2017-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106405385B (en) | Logic circuit single particle effect test method based on chain of flip-flops | |
| Eaton et al. | Single event transient pulsewidth measurements using a variable temporal latch technique | |
| Black et al. | Modeling of single event transients with dual double-exponential current sources: Implications for logic cell characterization | |
| Ceschia et al. | Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs | |
| CN105675984B (en) | A kind of impulse waveform test circuit | |
| US9835680B2 (en) | Method, device and computer program product for circuit testing | |
| Gomina et al. | Power supply glitch attacks: Design and evaluation of detection circuits | |
| Cao et al. | Exploring active manipulation attacks on the TERO random number generator | |
| CN105811935B (en) | SET pulse method of testing on piece based on dynamic input vector | |
| Wang et al. | Single-event transient sensitivity evaluation of clock networks at 28-nm CMOS technology | |
| CN110119539A (en) | A kind of analysis method of combinational logic circuit Single event upset effecf propagation law | |
| Azimi et al. | On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs | |
| Nakamura et al. | Measurement of neutron-induced single event transient pulse width narrower than 100ps | |
| Nakamura et al. | Scaling effect and circuit type dependence of neutron induced single event transient | |
| CN106569040B (en) | Single-event transient pulse width measuring circuit, integrated circuit and electronic device | |
| Anghel et al. | Evaluation of SET and SEU effects at multiple abstraction levels | |
| Julai et al. | Error detection and correction of single event upset (SEU) tolerant latch | |
| Naseer et al. | Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology | |
| KR101697213B1 (en) | Methods and appratus for soft error immunity test in digital integrated circuits | |
| Castellani-Coulie et al. | Circuit effect on collection mechanisms involved in single event phenomena: Application to the response of a NMOS transistor in a 90 nm SRAM cell | |
| Balaji et al. | A survey on effective Automatic Test Pattern Generator for self-checking Scan-BIST VLSI circuits | |
| Furuta et al. | Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates | |
| EP3438678B1 (en) | Power supply noise sensor | |
| Pfeifer et al. | Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs | |
| Kumar et al. | An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |