CN105811935B - SET pulse method of testing on piece based on dynamic input vector - Google Patents
SET pulse method of testing on piece based on dynamic input vector Download PDFInfo
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- CN105811935B CN105811935B CN201610124947.2A CN201610124947A CN105811935B CN 105811935 B CN105811935 B CN 105811935B CN 201610124947 A CN201610124947 A CN 201610124947A CN 105811935 B CN105811935 B CN 105811935B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses SET pulse method of testing on the piece based on dynamic input vector, it is therefore an objective to provides SET pulse method of testing on a kind of and more close piece of circuit actual working environment.Technical scheme is：1. design SET pulse test circuit on the piece based on dynamic input vector；2. it is electric in SET pulse test circuit on pair piece based on dynamic input vector, load a dynamic input vector in the input of chain of inverters；3. SET pulse test circuit on the piece based on dynamic input vector is placed in particle radiation environment, SET pulse is tested, finally the SET pulse caused by circuit in the case where outside host port obtains dynamic input vector.Compared to existing upper SET pulse method of testing of the present invention, caused SET pulse is more close when mean breadth of SET pulse number, the width of each SET pulse and SET pulse measured etc. is bombarded with circuit in practical work process by single-particle, so that test result has more directive significance, the difficulty of integrated circuit soft error rate analysis is reduced.
Description
Technical field
The present invention relates to single-ion transient state on a kind of piece (Single-Event Transient, SET) pulse test method,
SET pulse method of testing on more particularly to a kind of piece based on dynamic input vector.
Background technology
Electronic system applied to space flight, aviation is highly susceptible to the influence of radiation effect and failed.Work under radiation environment
The electronic system of work, the radiation effect mainly considered have single particle effect (Single-Event Effect, SEE) and accumulated dose
Two kinds of effect (Total Ionizing Dose, TID).With the continuous diminution of integrated circuit technology characteristic size, accumulated dose effect
The influence of reply chip is being gradually reduced；And influence of the single particle effect to electronic device in space equipment is then increasingly sharpening.
As one kind of single particle effect, SET is typically to be declined naturally by cosmic ray, solar particle events, transuranium material
Become the phenomenon that either circuit function caused by high-energy particle bombardment circuit caused by nuclear weapon blast is mutated.Semiconductor devices
After being bombarded by single-particle, the energy of high energy particle deposition can cause the ionization by collision of particle, in concentration gradient and electric field
The electric charge ionized out under effect is collected and transported, and causes circuit node electric current and voltage transient mutation occur.
With the continuous reduction of process, the clock frequency in integrated circuit is also constantly rising.Scholar is general in the world
Time viewpoint be that the increase of clock frequency can improve the probability of SET pulse latch, however as the rising of clock frequency, in circuit
The pace of change of portion's node state is consequently increased, and this will carry out huge challenge to the analytic band of integrated circuit soft error rate.
At present, (Narasimham et al. 2006 exists as shown in Figure 1 for common SET pulse tilted object circuit in the world
" the On-Chip delivered on IEEE Transaction on Device and Materials Reliability
The one kind proposed first in Characterization of Single-Event Transient Pulsewidths " articles can
Test automatic triggering circuit on the piece of SET pulse width), by N, (N is the natural number more than 1, according to process and ion irradiation
Experimental enviroment determines N size) the SET pulse generation circuit that forms of the chain of inverters of level phase inverter composition, and pulse is wide
Test circuit composition is spent, i-stage phase inverter is designated as INVi, i is integer, 1≤i≤N.The process that SET pulse width is tested
It is that Fig. 1 input is fixed as into 0 or 1 (to carry out the test of SET pulse on piece using static input vector, see fixed in Fig. 2
For 0 quiescent input signal, be fixed as 1 quiescent input signal).However, in real circuit, input is constantly to become
Change (i.e. input be dynamic change, the peak frequency of change be clock frequency, as Fig. 2 frequencies be 1GHz dynamic input believe
Shown in number), dynamic input signal constantly changes between 0,1 in real circuits.
It is (fixed for static vector in input such as the PMOS of the phase inverter INV2 in Fig. 3 for SET pulse generation circuit
Determined for 0 or 1 by INV2 input, when INV2 input port is fixed as situation 1) in Fig. 3, it is assumed that the transistor by
To the bombardment of single-particle, the SET pulse that width is 300ps can be produced, then can be tested at the signal output of output port
To 300ps SET pulse width.And when input vector dynamic change, it is defeated in signal for Fig. 3 SET pulse generation circuit
Enter the dynamic input signal that frequency is 1GHz in place's loading such as Fig. 2, similarly for the PMOS in INV2, when no particle bombardment
When, SET pulse is not produced, phase inverter INV2 output is as shown in the output of the phase inverter INV2 in Fig. 4；And working as has particle to bang
When hitting, and the time occurs when it is near high level that it, which exports saltus step, and the signified place such as arrow in Fig. 4, SET is produced and exported
Before saltus step is high level, at this moment originally can caused by 300ps SET pulse now will also be changed into high due to INV2 output
Level and the high level that causes SET pulse width caused by reality to be output are cut down, and are in particular in signal output part
The phenomenon of mouth is less than 300ps for SET pulse width, such as the SET pulse width after cutting down in Fig. 4.This phenomenon is sent out at low frequency
Raw probability is relatively fewer, but the probability occurred in high frequency will greatly increase.
Above analytic explanation, the method that SET pulse test on piece is carried out using static input vector, the actual work with circuit
Deviate from as situation so that mean breadth of the number of the SET pulse measured, the width of each SET pulse and SET pulse etc. is equal
The number of caused SET pulse, the width of each SET pulse when being bombarded with circuit in practical work process by single-particle
And mean breadth of SET pulse etc. is deviated, the analytic band to integrated circuit soft error rate comes difficult.
The content of the invention
The technical problem to be solved in the present invention is：For integrated circuit in practical work process, its input is continuous with the time
Change, i.e., input is dynamic change；But circuit input is permanent when testing SET pulse width in the world at present
Fixed --- 0 or 1 is fixed as, i.e., the test of SET pulse on piece is carried out using static input vector.With circuit real work feelings
Deviating from for condition will cause the number using the SET pulse measured by SET pulse method of testing on current piece, each SET pulse
Width and the mean breadth etc. of SET pulse it is caused when being bombarded with circuit in practical work process by single-particle
Mean breadth of the number of SET pulse, the width of each SET pulse and SET pulse etc. is deviated, and gives integrated circuit soft error
The analytic band of rate comes difficult by mistake.
For being currently based on the problems of SET pulse method of testing on the piece of static input vector, the present invention provides
SET pulse method of testing on a kind of piece based on dynamic input vector.SET pulse method of testing based on dynamic input vector,
Due to using the test that SET pulse is carried out with input identical dynamic input during circuit real work, measured SET pulse
Number, each SET pulse width and SET pulse mean breadth etc. can with circuit in practical work process by
Caused SET pulse situation when single-particle bombards is more closely, so that test result has more directive significance, reduction collection
Into the difficulty of circuit soft error rate analysis.
The technical scheme is that：
The first step, design SET pulse test circuit on the piece as shown in Figure 5 based on dynamic input vector.Based on dynamic
SET pulse test circuit (is designated as the first chain of inverters, second anti-by two duplicate chain of inverters on the piece of input vector
Phase device chain), XOR gate, SET pulse tilted object circuit form.
First chain of inverters, the second chain of inverters are connected with XOR gate, are formed by N levels phase inverter.First phase inverter
Chain, the input of the second chain of inverters connect together, as the input port of dynamic vector, from the piece based on dynamic input vector
Upper one dynamic input vector of SET pulse test circuit external reception；The output point of first chain of inverters, the second chain of inverters
Two input ports of XOR gate are not connect.
XOR gate is connected with the first chain of inverters, the second chain of inverters, SET pulse tilted object circuit, anti-phase from first
Device chain, the second chain of inverters receive the output pulse of the first chain of inverters, the second chain of inverters, by the first chain of inverters, second
After the output pulse of chain of inverters carries out XOR, SET pulse is given to SET pulse tilted object circuit by output port
Input port.
SET pulse tilted object circuit is identical with the SET pulse tilted object circuit in background technology.SET pulse width
Test circuit is connected with XOR gate, external host.The input port of SET pulse tilted object circuit connects the output end of XOR gate
Mouthful, SET pulse is received from XOR gate, is exported SET pulse width to outside by output port after testing out SET pulse width
Main frame.
Second step, to electric in SET pulse test circuit on the piece based on dynamic input vector, in the input of chain of inverters
A dynamic input vector is loaded, dynamic input vector can be produced by crystal oscillator.
3rd step, SET pulse test circuit on the piece based on dynamic input vector is placed in particle radiation environment, utilized
SET pulse test circuit test SET pulse on piece of the invention based on dynamic input vector.The present invention is based on dynamic input vector
Piece on SET pulse method of testing operation principle as shown in fig. 7, due to two chain of inverters striking resemblances, be reasonably laid out
Under the conditions of, during particle bombardment, while hit in two chain of inverters, the identical transistor at identical series (being designated as i-stage) place
Probability is very low, it is therefore assumed that during particle bombardment, only wherein a chain of inverters has transistor by particle bombardment.It is false
If the first chain of inverters is not affected by particle bombardment, its output waveform and input vector are completely the same, simply slightly postpone；Second is anti-
There is transistor by particle bombardment in phase device chain.After SET pulse reaches the XOR gate in test circuit, due to the two of XOR gate
Individual input output when identical is 0, and output is 1 when different, and now XOR gate is not using by the first chain of inverters of particle bombardment
Output, filtered the original output composition in the output waveform of the second chain of inverters.In this way, surveyed again by SET pulse width
Try circuit test, can under the conditions of outside host port obtains dynamic input vector SET pulse caused by circuit reality.
Following technique effect can be reached using the present invention：
1. the present invention carries out SET pulse test on piece based on dynamic input vector, specific input vector can be according to quilt
Input in the case of slowdown monitoring circuit real work is determined, and because dynamic input vector is more nearly real circuit signal, is surveyed
Test result is also more nearly actual conditions.
2. SET pulse test circuit is by two duplicate phase inverters on the piece of the invention based on dynamic input vector
Chain, XOR gate obtain SET pulse caused by circuit reality under the conditions of dynamic input vector.Due to two moulds one of chain of inverters one
Sample, under rational distributional condition, during particle bombardment, while hit the phase allomeric in two chain of inverters, at identical series
The probability of pipe is very low.When the transistor in an only chain of inverters receives particle bombardment, the SET pulse of two chain of inverters
After reaching XOR gate, due to two of XOR gate inputs, output is 0 when identical, and output is 1 when different, and now XOR gate utilizes
The first chain of inverters by particle bombardment does not export, filtered original output in the output waveform of the second chain of inverters into
Point.Pass through the test of SET pulse tilted object circuit again, can under the conditions of host port obtains dynamic input vector circuit it is real
SET pulse caused by border.Therefore, the number of SET pulse measured by the present invention, the width of each SET pulse and each
The mean breadth of SET pulse, the SET pulse method of testing based on static input vector relatively generally used in the world at present are surveyed
Result it is more accurate, be more nearly actual conditions.
Brief description of the drawings
Fig. 1 is current SET pulse test circuit building-block of logic used in the world in background technology；
Fig. 2 is three kinds of input signal schematic diagrames of SET pulse tilted object circuit in background technology, is respectively：It is fixed as 0
Quiescent input signal, be fixed as 1 quiescent input signal, frequency be 1GHz dynamic input signal；
Fig. 3 is SET pulse generation circuit schematic diagram on piece in background technology, is the section bombarded assumed at arrow meaning
Point；
Fig. 4 be background technology in when in Fig. 3 arrow meaning at node bombarded after, in a static condition, phase inverter INV2
Output, at arrow produce an original 300ps SET pulse width；In a dynamic condition, phase inverter INV2 output,
SET pulse width after actual measurement to abatement at arrow；
Fig. 5 is SET pulse method of testing flow chart on the piece of the invention based on dynamic input vector；
Fig. 6 is SET pulse test circuit building-block of logic on the piece of the invention based on dynamic input vector；
Fig. 7 is SET pulse method of testing operation principle schematic diagram on the piece of the invention based on dynamic input vector：When two
SET pulse is produced in the same chain of inverters in a certain bar chain, XOR gate, which will check, to be come, and measures pulse width；
Fig. 8 is shown to be carried out using SET pulse method of testing on piece current in background technology to SET pulse width
The result of Hspice simulations；
It is wide to SET pulse that Fig. 9 show SET pulse method of testing on the piece based on dynamic input vector using the present invention
Degree carries out the result of Hspice simulations.
Embodiment
Fig. 1 is current SET pulse test circuit building-block of logic used in the world in background technology.At present, it is international
The SET pulse generation circuit that the chain of inverters that upper common SET pulse tilted object circuit is made up of N level phase inverters is formed, with
And pulse width test circuit composition, i-stage phase inverter are designated as INVi, i is integer, 1≤i≤N.SET pulse width is surveyed
The process of examination is that Fig. 1 input is fixed as into 0 or 1 (to carry out the test of SET pulse on piece using static input vector, see
0 quiescent input signal is fixed as in Fig. 2, is fixed as 1 quiescent input signal).However, in real circuit, input is
Constantly change (i.e. input is dynamic change, and the peak frequency of change be clock frequency, if Fig. 2 frequencies is 1GHz
Shown in dynamic input signal), dynamic input signal constantly changes between 0,1 in real circuits.
Fig. 3 is SET pulse generation circuit schematic diagram on piece in background technology.For SET pulse generation circuit, in Fig. 3
Phase inverter INV2 PMOS, (be fixed as 0 or 1 by INV2 input to determine, in Fig. 3 in input for static vector
When INV2 input port is fixed as situation 1), it is assumed that the transistor is bombarded by single-particle, is hypothesis at arrow meaning
The node bombarded, as shown in figure 4, when in Fig. 3 arrow meaning at node bombarded after, in a static condition, phase inverter
INV2 output, original 300ps SET pulse width is produced at arrow；In a dynamic condition, when input vector dynamic
During change, for Fig. 3 SET pulse generation circuit, in signal input, dynamic of the loading as frequency is 1GHz in Fig. 2 inputs letter
Number, similarly for the PMOS in INV2, when there is no particle bombardment, SET pulse is not produced, phase inverter INV2 output is as schemed
Shown in the output of phase inverter INV2 in 4；And when there is particle bombardment, and it is near high level that the time, which occurs to export saltus step at it,
When, the signified place such as arrow in Fig. 4, SET is produced before output saltus step is high level, at this moment originally can be caused
Output due to INV2 is now also changed into high level and causes SET pulse width caused by reality defeated by 300ps SET pulse
The high level gone out is cut down, and is in particular in that the phenomenon of signal output port is less than 300ps, such as Fig. 4 for SET pulse width
SET pulse width after middle abatement.The probability that this phenomenon occurs at low frequency is relatively fewer, but occurs in high frequency general
Rate will greatly increase.
Fig. 6 is SET pulse method of testing flow chart on the piece of the invention based on dynamic input vector.The present invention is based on dynamic
SET pulse method of testing flow is as follows on the piece of input vector：
The first step, design SET pulse test circuit on the piece as shown in Figure 5 based on dynamic input vector.Based on dynamic
SET pulse test circuit (is designated as the first chain of inverters, second anti-by two duplicate chain of inverters on the piece of input vector
Phase device chain), XOR gate, SET pulse tilted object circuit form.
First chain of inverters, the second chain of inverters are connected with XOR gate, are formed by N levels phase inverter.First phase inverter
Chain, the input of the second chain of inverters connect together, as the input port of dynamic vector, from the piece based on dynamic input vector
Upper one dynamic input vector of SET pulse test circuit external reception；The output point of first chain of inverters, the second chain of inverters
Two input ports of XOR gate are not connect.
XOR gate is connected with the first chain of inverters, the second chain of inverters, SET pulse tilted object circuit, anti-phase from first
Device chain, the second chain of inverters receive the output pulse of the first chain of inverters, the second chain of inverters, by the first chain of inverters, second
After the output pulse of chain of inverters carries out XOR, SET pulse is given to SET pulse tilted object circuit by output port
Input port.
SET pulse tilted object circuit is identical with the SET pulse tilted object circuit in background technology.SET pulse width
Test circuit is connected with XOR gate, external host.The input port of SET pulse tilted object circuit connects the output end of XOR gate
Mouthful, SET pulse is received from XOR gate, is exported SET pulse width to outside by output port after testing out SET pulse width
Main frame.
Second step, to electric in SET pulse test circuit on the piece based on dynamic input vector, in the input of chain of inverters
A dynamic input vector is loaded, dynamic input vector can be produced by crystal oscillator.
3rd step, SET pulse test circuit on the piece based on dynamic input vector is placed in particle radiation environment.By
The test of SET pulse tilted object circuit, obtained in outside host port under the conditions of dynamic input vector produced by circuit reality
SET pulse.
Fig. 7 is SET pulse method of testing operation principle schematic diagram on the piece of the invention based on dynamic input vector.Due to two
Bar chain of inverters is the same, under rational distributional condition, during particle bombardment, while hits in two chain of inverters, be identical
The probability of the identical transistor at series (being designated as i-stage) place is very low, it is therefore assumed that during particle bombardment, only wherein one
Chain of inverters has transistor by particle bombardment, when producing SET pulse in a certain bar chain in two the same chain of inverters,
XOR gate, which will check, to be come, and measures pulse width.Assuming that the first chain of inverters is not affected by particle bombardment, its output waveform with
Input vector is completely the same, simply slightly postpones；There is transistor by particle bombardment in second chain of inverters.When SET pulse arrives
Up to after the XOR gate in test circuit, due to two of XOR gate inputs, output is 0 when identical, and output is 1 when different, now
XOR gate is exported using the first chain of inverters not by particle bombardment, has filtered the original in the output waveform of the second chain of inverters
Begin output composition.In this way, passing through the test of SET pulse tilted object circuit again, it is defeated dynamic can be obtained in outside host port
SET pulse caused by circuit reality under the conditions of incoming vector.
Fig. 8 is the result that Hspice simulations are carried out using SET pulse method of testing on current piece.The simulation uses Fig. 1
Shown test circuit.3 small figures are included in Fig. 8, as shown in uppermost small figure in Fig. 8, in the simulation process, input
Mouth a uses static input vector (being fixed as low level), i.e., v (a) is 0 always in figure.
As shown in the small figure of Fig. 8 bottoms, bombardment simulation using double Exponential current sources, the bombardment moment be respectively t=32ns,
At the time of 38ns, 53.5ns and 71.9ns, bombardment analog current is identical used by four moment, and bombardment position selects
The output end of second phase inverter in chain of inverters.
As shown in the small figure among Fig. 8, v (y) is the output signal of whole chain of inverters.Four arteries and veins in the signal waveform
Rush four double Exponential current pulses when waveform corresponds to bombardment simulation respectively.Can intuitively it find out from signal y analog waveform,
In the case of using static input vector and identical bombardment analog signal, circuit is produced when being bombarded at different moments
SET pulse width it is completely the same --- the occurrence of this pulse width counted from table 1 it is also seen that；Meanwhile
In the case of being tested using static input vector, circuit after by particle bombardment the number of caused SET pulse with
It is completely the same by the number bombarded.
Fig. 9 show SET pulse method of testing on the piece based on dynamic input vector using the present invention and carries out Hspice
The result of simulation.
Using the test circuit shown in Fig. 5, two chain of inverters therein are completely the same, and static with using for the simulation
Chain of inverters when input vector is simulated in circuit is identical.It is unified in Fig. 9 to include 3 small figures, such as the top in Fig. 9
Small figure shown in, in the simulation process, input port a use dynamic input vector (input for a mechanical periodicity signal, signal
Cycle is 12ns).
As shown in the small figure of Fig. 9 bottoms, bombardment simulation is same static with using using double Exponential current sources, bombardment moment
Consistent at the time of selected when input vector is simulated (at the time of being respectively t=32ns, 38ns, 53.5ns and 71.9ns, four
Bombardment analog current is identical used by the individual moment), bombardment position select in chain of inverters 1 second phase inverter
Output end.
As shown in the small figure among Fig. 9, in the case of four simulation bombardment pulses of input, but only observed in output end y
To three SET pulses；Also, different (the width of specific each SET pulse of the width of three observed SET pulses
1) angle value is shown in Table.
In simulation process, with the change at bombardment moment, the number of the SET pulse observed at output port y with
And the width of some specific SET pulse can be all varied from.
Table 1
In upper table " " represent corresponding to SET pulse be not present.From the comparing result of upper table it is concluded that：Equally
Bombarding conditions under, using the SET pulse on the piece based on dynamic input vector of the present invention measured by SET pulse method of testing
Number, the width of each SET pulse and the mean breadth etc. of each SET pulse with current based on static input vector
Result on piece measured by SET pulse method of testing is different.On the piece based on dynamic input vector using the present invention
Result measured by SET pulse method of testing is caused when will more conform in circuit practical work process by particle bombardment
The situation of SET pulse.
Claims (1)
1. SET pulse method of testing on the piece based on dynamic input vector, it is characterised in that comprise the steps of：
The first step, design SET pulse test circuit on the piece based on dynamic input vector；On piece based on dynamic input vector
SET pulse test circuit is designated as the first chain of inverters, the second chain of inverters by two duplicate chain of inverters, XOR gate,
SET pulse tilted object circuit is formed；
First chain of inverters, the second chain of inverters are connected with XOR gate, are formed by N levels phase inverter, and N is the nature more than 1
Number, N size is determined according to process and ion irradiation experimental enviroment；First chain of inverters, the second chain of inverters it is defeated
Enter end to connect together, as the input port of dynamic vector, from the piece based on dynamic input vector outside SET pulse test circuit
Portion receives a dynamic input vector；The output of first chain of inverters, the second chain of inverters connect XOR gate respectively two are defeated
Inbound port；
XOR gate is connected with the first chain of inverters, the second chain of inverters, SET pulse tilted object circuit, from the first chain of inverters,
Second chain of inverters receives the output pulse of the first chain of inverters, the second chain of inverters, by the first chain of inverters, the second phase inverter
After the output pulse of chain carries out XOR, SET pulse is given to the input of SET pulse tilted object circuit by output port
Port；
SET pulse tilted object circuit is connected with XOR gate, external host；The input port of SET pulse tilted object circuit connects
The output port of XOR gate, SET pulse is received from XOR gate, tested out SET pulse after SET pulse width by output port
Width is exported to external host；
Second step, to electric in SET pulse test circuit on the piece based on dynamic input vector, loaded in the input of chain of inverters
Input vector；
3rd step, SET pulse test circuit on the piece based on dynamic input vector is placed in particle radiation environment, using described
SET pulse test circuit tests SET pulse on piece based on dynamic input vector；By the survey of SET pulse tilted object circuit
Examination, the SET pulse caused by circuit reality under the conditions of outside host port obtains dynamic input vector.
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| CN106899287A (en) * | 2017-04-12 | 2017-06-27 | 长沙中部芯空微电子研究所有限公司 | The reinforcing circuit and clock line length line transmission circuit of a kind of Long line transmission driver |
| CN110988496B (en) * | 2019-12-13 | 2021-05-11 | 西安电子科技大学 | Three-way-test single-particle transient pulse width measuring circuit |
| CN111342821B (en) * | 2020-03-03 | 2023-05-23 | 合肥工业大学 | Single-event transient pulse generation and measurement system and method based on FPGA |
| CN113484604B (en) * | 2021-07-08 | 2023-04-21 | 中国人民解放军国防科技大学 | SET pulse measuring circuit capable of eliminating influence of measuring circuit and integrated circuit chip |
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