CN105811935A - On-chip SET pulse testing method based on dynamic input vector - Google Patents
On-chip SET pulse testing method based on dynamic input vector Download PDFInfo
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- CN105811935A CN105811935A CN201610124947.2A CN201610124947A CN105811935A CN 105811935 A CN105811935 A CN 105811935A CN 201610124947 A CN201610124947 A CN 201610124947A CN 105811935 A CN105811935 A CN 105811935A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
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Abstract
The invention discloses an on-chip SET(Single-Event Transient) pulse testing method based on a dynamic input vector and aims to provide an on-chip SET pulse testing method whose results are more approximate to those of a circuit in a practical working environment. The technical scheme includes steps of 1, designing an on-chip SET pulse testing circuit based on the dynamic input vector; 2, closing the on-chip SET pulse testing circuit based on the dynamic input vector and loading the dynamic input vector on the input terminal of an inverter chain; 3, placing the on-chip SET pulse testing circuit based on the dynamic input vector in a particle radiation environment, testing SET pulses and obtaining the SET pulses generated by the circuit under the dynamic input vector at an external port of an host finally. Compared with a traditional on-chip SET pulse testing method, the method provided by the invention is advantaged in that the measured SET pulse number, the width of each SET pulse and the average width of each SET pulse are more approximate to those of SET pulses generated by a circuit subjected to single particle bombardment during a practical working process, so that the testing results are more instructive and difficulty of soft error analysis of integrated circuits is reduced.
Description
Technical field
The present invention relates to single-ion transient state (Single-EventTransient, SET) pulse test method on a kind of sheet, particularly to a kind of based on SET pulse method of testing on the sheet of dynamic input vector.
Background technology
Be applied to space flight, the electronic system of aviation is highly susceptible to the impact of radiation effect and lost efficacy.The electronic system worked under radiation environment, the main radiation effect considered has single particle effect (Single-EventEffect, SEE) and total dose effect (TotalIonizingDose, TID) two kinds.Along with constantly reducing of integrated circuit technology characteristic size, the impact of chip is being gradually reduced by total dose effect；The impact of electronic device in space equipment is then being increasingly sharpened by single particle effect.
As the one of single particle effect, SET is usually by the phenomenon of the caused circuit function sudden change of the produced high-energy particle bombardment circuit of cosmic ray, solar particle events, transuranium material natural radioactive decay or nuclear weapon blast.Semiconductor device is after being subject to single-particle bombardment, and the energy deposition of high energy particle can cause the ionization by collision of particle, and the electric charge ionized out under the effect of Concentraton gradient and electric field is collected and transports, and causes that electric current and voltage transient sudden change occurs in circuit node.
Along with the continuous reduction of process, the clock frequency in integrated circuit is also in continuous rising.The increase that the viewpoint that scholar is general in the world is clock frequency can improve the probability that SET pulse latches, rising however as clock frequency, the pace of change of circuit internal node state is consequently increased, and the analysis to integrated circuit soft error rate is brought huge challenge by this.
nullAt present，SET pulse tilted object circuit common in the world is (on a kind of sheet testing SET pulse width proposed first in " On-ChipCharacterizationofSingle-EventTransientPulsewidth s " article that Narasimham et al. delivers for 2006 on IEEETransactiononDeviceandMaterialsReliability automatic triggering circuit) as shown in Figure 1，By N, (N is the natural number more than 1，Determine the size of N according to process and ion irradiation experimental enviroment) level phase inverter composition chain of inverters constitute SET pulse produce circuit，And pulse width test circuit composition，I-stage phase inverter is designated as INVi, i is integer, 1≤i≤N.The process that SET pulse width carries out testing is that the input of Fig. 1 is fixed as 0 or 1 (namely adopting static input vector to carry out the test of SET pulse on sheet, the quiescent input signal see the quiescent input signal being fixed as 0 in Fig. 2, being fixed as 1).But, in real circuit, input be constantly change (namely input is dynamically change, and the peak frequency of change is clock frequency, as shown in dynamic input signal that Fig. 2 frequency is 1GHz), in real circuits, dynamic input signal constantly changes between 0,1.
Circuit is produced for SET pulse, the PMOS of the phase inverter INV2 in Fig. 3, in input, for static vector, (being fixed as 0 or 1 is determined by the input of INV2, in Fig. 3, the input port of INV2 is fixed as 1) situation time, assume that this transistor is subject to the bombardment of single-particle, the SET pulse that width is 300ps can be produced, then can test the SET pulse width of 300ps in signal output place of output port.And when input vector dynamically changes, SET pulse for Fig. 3 produces circuit, loading such as Fig. 2 medium frequency in signal input is the dynamic input signal of 1GHz, similarly for the PMOS in INV2, when there is no particle bombardment, do not produce SET pulse, shown in the output of the output of phase inverter INV2 phase inverter INV2 in Fig. 4；And when there being particle bombardment, and the time occurs when its output saltus step is near high level, the place of arrow indication in Fig. 4, SET produces before output saltus step is high level, the SET pulse of the 300ps that at this moment originally can produce now also will become high level due to the output of INV2 and causes the high level that the SET pulse width of actual generation is output to cut down, it is in particular in that the phenomenon of signal output port is SET pulse width less than 300ps, SET pulse width after abatement in Fig. 4.The probability that this phenomenon occurs at low frequency is relatively fewer, but the probability occurred in high frequency will be greatly increased.
Above analytic explanation, static input vector is adopted to carry out the method for SET pulse test on sheet, deviate from the real work situation of circuit, make the number of the SET pulse recorded, the width of each SET pulse and the mean breadth etc. of SET pulse all be subject to during single-particle bombardment the deviation to some extent such as the mean breadth of the number of produced SET pulse, the width of each SET pulse and SET pulse in practical work process with circuit, bring difficulty to the analysis of integrated circuit soft error rate.
Summary of the invention
The technical problem to be solved in the present invention is: integrated circuit is in practical work process, and its input constantly changes in time, and namely input is dynamically change；But, at present in the world test SET pulse width time circuit input be all constant be fixed as 0 or 1, namely adopt static input vector to carry out the test of SET pulse on sheet.With circuit real work situation deviate from the deviation to some extent such as the number of SET pulse made to adopt on current sheet measured by SET pulse method of testing, the width of each SET pulse and the mean breadth etc. of SET pulse are all subject in practical work process the number of produced SET pulse when single-particle bombards, the width of each SET pulse and SET pulse mean breadth with circuit, bring difficulty to the analysis of integrated circuit soft error rate.
For the problem being currently based on the sheet of static input vector existing for SET pulse method of testing, the present invention provides a kind of based on SET pulse method of testing on the sheet of dynamic input vector.SET pulse method of testing based on dynamic input vector, the dynamically input identical due to input when adopting with circuit real work carries out the test of SET pulse, when the mean breadths of the measured number of SET pulse, the width of each SET pulse and SET pulse etc. can be subject to single-particle bombardment with circuit in practical work process produced SET pulse situation closer to, so that test result has more directive significance, reduce the difficulty that integrated circuit soft error rate is analyzed.
The technical scheme is that
The first step, design as shown in Figure 5 based on the sheet of dynamic input vector SET pulse test circuit.It is made up of two duplicate chain of inverters (being designated as the first chain of inverters, the second chain of inverters), XOR gate, SET pulse tilted object circuit based on SET pulse test circuit on the sheet of dynamic input vector.
First chain of inverters, the second chain of inverters are all connected with XOR gate, form by N level phase inverter.First chain of inverters, the second chain of inverters input connect together, as the input port of dynamic vector, from the sheet based on dynamic input vector SET pulse test circuit external receive a dynamic input vector；First chain of inverters, the second chain of inverters output connect two input ports of XOR gate respectively.
XOR gate and the first chain of inverters, the second chain of inverters, SET pulse tilted object circuit are connected, the output pulse of the first chain of inverters, the second chain of inverters is received from the first chain of inverters, the second chain of inverters, after the output pulse of the first chain of inverters, the second chain of inverters is carried out XOR, by output port, SET pulse is given the input port of SET pulse tilted object circuit.
SET pulse tilted object circuit is identical with the SET pulse tilted object circuit in background technology.SET pulse tilted object circuit is connected with XOR gate, external host.The input port of SET pulse tilted object circuit connects the output port of XOR gate, receives SET pulse from XOR gate, is exported SET pulse width to external host by output port after testing out SET pulse width.
Second step, powers on to SET pulse test circuit on the sheet based on dynamic input vector, and the input in chain of inverters loads a dynamic input vector, and dynamic input vector can be produced by crystal oscillator.
3rd step, is placed in SET pulse test circuit on the sheet based on dynamic input vector in particle radiation environment, utilizes the present invention based on SET pulse test circuit test SET pulse on the sheet of dynamic input vector.The present invention is based on SET pulse method of testing operation principle on the sheet of dynamic input vector as shown in Figure 7, due to two chain of inverters striking resemblances, under rational distributional condition, during particle bombardment, hit in two chain of inverters simultaneously, the probability of the identical transistor at identical progression (being designated as i-stage) place very low, it is therefore assumed that in particle bombardment process, only wherein a chain of inverters has transistor to be subject to particle bombardment.Assuming that the first chain of inverters is not affected by particle bombardment, its output waveform is completely the same with input vector, simply slightly postpones；Second chain of inverters there is transistor to be subject to particle bombardment.When after the XOR gate that SET pulse arrives in test circuit, owing to two inputs of XOR gate are output as 0 when identical, asynchronously being output as 1, now XOR gate utilizes the output of the first chain of inverters not being subject to particle bombardment, has filtered the original output composition in the output waveform of the second chain of inverters.So, then through the test of SET pulse tilted object circuit, just can when outside host port obtains dynamic input vector SET pulse produced by circuit reality.
Adopt the present invention can reach techniques below effect:
1. the present invention carries out SET pulse test on sheet based on dynamic input vector, concrete input vector can be determined according to the input in circuit-under-test real work situation, owing to dynamic input vector is more nearly real circuit signal, test result is also more nearly practical situation.
2. the present invention is based on SET pulse produced by circuit reality when SET pulse test circuit is obtained dynamic input vector by two duplicate chain of inverters, XOR gate on the sheet of dynamic input vector.Due to two chain of inverters striking resemblances, under rational distributional condition, during particle bombardment, hit in two chain of inverters simultaneously, the probability of the identical transistor at identical progression place very low.When only having the transistor in a chain of inverters to receive particle bombardment, article two, after the SET pulse of chain of inverters arrives XOR gate, owing to two inputs of XOR gate are output as 0 when identical, asynchronously it is output as 1, now XOR gate utilizes the output of the first chain of inverters not being subject to particle bombardment, has filtered the original output composition in the output waveform of the second chain of inverters.Then through the test of SET pulse tilted object circuit, just can when host port obtains dynamic input vector SET pulse produced by circuit reality.Therefore, the mean breadth of the number of the SET pulse measured by the present invention, the width of each SET pulse and each SET pulse, relatively at present in the world commonly used more accurate based on the result measured by the SET pulse method of testing of static input vector, be more nearly practical situation.
Accompanying drawing explanation
Fig. 1 is the SET pulse test circuit logic structure chart adopted in the world at present in background technology；
Fig. 2 is three kinds of input signal schematic representations of SET pulse tilted object circuit in background technology, is respectively as follows: the quiescent input signal being fixed as 0, is fixed as the quiescent input signal of 1, and frequency is the dynamic input signal of 1GHz；
Fig. 3 is that in background technology, on sheet, SET pulse produces circuit diagram, and arrow indication place is the node bombarded assumed；
Fig. 4 is in background technology after in Fig. 3, arrow indication place node is bombarded, in a static condition, the output of phase inverter INV2, the SET pulse width of an original 300ps is produced at arrow place；In a dynamic condition, the output of phase inverter INV2, the SET pulse width after arrow place surveys abatement；
Fig. 5 is that the present invention is based on SET pulse method of testing flow chart on the sheet of dynamic input vector；
Fig. 6 is that the present invention is based on SET pulse test circuit logic structure chart on the sheet of dynamic input vector；
Fig. 7 be the present invention based on SET pulse method of testing operation principle schematic diagram on the sheet of dynamic input vector: when in bar chain a certain in two living chain of inverters produce SET pulse, XOR gate will check out, and records pulse width；
Fig. 8 show and utilizes SET pulse method of testing on sheet current in background technology that SET pulse width carries out the result of Hspice simulation；
Fig. 9 show the result that SET pulse width carries out Hspice simulation based on SET pulse method of testing on the sheet of dynamic input vector utilizing the present invention.
Detailed description of the invention
Fig. 1 is the SET pulse test circuit logic structure chart adopted in the world at present in background technology.At present, the SET pulse that the chain of inverters that SET pulse tilted object circuit common in the world is made up of N level phase inverter is constituted produces circuit and pulse width test circuit composition, and i-stage phase inverter is designated as INVi, i is integer, 1≤i≤N.The process that SET pulse width carries out testing is that the input of Fig. 1 is fixed as 0 or 1 (namely adopting static input vector to carry out the test of SET pulse on sheet, the quiescent input signal see the quiescent input signal being fixed as 0 in Fig. 2, being fixed as 1).But, in real circuit, input be constantly change (namely input is dynamically change, and the peak frequency of change is clock frequency, as shown in dynamic input signal that Fig. 2 frequency is 1GHz), in real circuits, dynamic input signal constantly changes between 0,1.
Fig. 3 is that in background technology, on sheet, SET pulse produces circuit diagram.Circuit is produced for SET pulse, the PMOS of the phase inverter INV2 in Fig. 3, in input, for static vector, (being fixed as 0 or 1 is determined by the input of INV2, in Fig. 3, the input port of INV2 is fixed as 1) situation time, assume that this transistor is subject to the bombardment of single-particle, arrow indication place is the node bombarded assumed, as shown in Figure 4, after in Fig. 3, arrow indication place node is bombarded, in a static condition, the output of phase inverter INV2, produces the SET pulse width of an original 300ps at arrow place；In a dynamic condition, when input vector dynamically changes, SET pulse for Fig. 3 produces circuit, loading such as Fig. 2 medium frequency in signal input is the dynamic input signal of 1GHz, similarly for the PMOS in INV2, when there is no particle bombardment, it does not have produce SET pulse, shown in the output of the output of phase inverter INV2 phase inverter INV2 in Fig. 4；And when there being particle bombardment, and the time occurs when its output saltus step is near high level, the place of arrow indication in Fig. 4, SET produces before output saltus step is high level, the SET pulse of the 300ps that at this moment originally can produce now also will become high level due to the output of INV2 and causes the high level that the SET pulse width of actual generation is output to cut down, it is in particular in that the phenomenon of signal output port is SET pulse width less than 300ps, SET pulse width after abatement in Fig. 4.The probability that this phenomenon occurs at low frequency is relatively fewer, but the probability occurred in high frequency will be greatly increased.
Fig. 6 is that the present invention is based on SET pulse method of testing flow chart on the sheet of dynamic input vector.The present invention is as follows based on SET pulse method of testing flow process on the sheet of dynamic input vector:
The first step, design as shown in Figure 5 based on the sheet of dynamic input vector SET pulse test circuit.It is made up of two duplicate chain of inverters (being designated as the first chain of inverters, the second chain of inverters), XOR gate, SET pulse tilted object circuit based on SET pulse test circuit on the sheet of dynamic input vector.
First chain of inverters, the second chain of inverters are all connected with XOR gate, form by N level phase inverter.First chain of inverters, the second chain of inverters input connect together, as the input port of dynamic vector, from the sheet based on dynamic input vector SET pulse test circuit external receive a dynamic input vector；First chain of inverters, the second chain of inverters output connect two input ports of XOR gate respectively.
XOR gate and the first chain of inverters, the second chain of inverters, SET pulse tilted object circuit are connected, the output pulse of the first chain of inverters, the second chain of inverters is received from the first chain of inverters, the second chain of inverters, after the output pulse of the first chain of inverters, the second chain of inverters is carried out XOR, by output port, SET pulse is given the input port of SET pulse tilted object circuit.
SET pulse tilted object circuit is identical with the SET pulse tilted object circuit in background technology.SET pulse tilted object circuit is connected with XOR gate, external host.The input port of SET pulse tilted object circuit connects the output port of XOR gate, receives SET pulse from XOR gate, is exported SET pulse width to external host by output port after testing out SET pulse width.
Second step, powers on to SET pulse test circuit on the sheet based on dynamic input vector, and the input in chain of inverters loads a dynamic input vector, and dynamic input vector can be produced by crystal oscillator.
3rd step, is placed in SET pulse test circuit on the sheet based on dynamic input vector in particle radiation environment.Through the test of SET pulse tilted object circuit, the SET pulse produced by circuit reality when outside host port obtains dynamic input vector.
Fig. 7 is that the present invention is based on SET pulse method of testing operation principle schematic diagram on the sheet of dynamic input vector.Due to two chain of inverters striking resemblances, under rational distributional condition, during particle bombardment, hit in two chain of inverters simultaneously, the probability of the identical transistor at identical progression (being designated as i-stage) place very low, it is therefore assumed that in particle bombardment process, only wherein a chain of inverters has transistor to be subject to particle bombardment, when bar chain a certain in two living chain of inverters produces SET pulse, XOR gate will check out, and records pulse width.Assuming that the first chain of inverters is not affected by particle bombardment, its output waveform is completely the same with input vector, simply slightly postpones；Second chain of inverters there is transistor to be subject to particle bombardment.When after the XOR gate that SET pulse arrives in test circuit, owing to two inputs of XOR gate are output as 0 when identical, asynchronously being output as 1, now XOR gate utilizes the output of the first chain of inverters not being subject to particle bombardment, has filtered the original output composition in the output waveform of the second chain of inverters.So, then through the test of SET pulse tilted object circuit, just can when outside host port obtains dynamic input vector SET pulse produced by circuit reality.
Fig. 8 utilizes SET pulse method of testing on current sheet to carry out the result of Hspice simulation.This simulation adopts the test circuit shown in Fig. 1.Comprising 3 little figure in Fig. 8, in Fig. 8 shown in uppermost little figure, in this simulation process, input port a adopts static input vector (being fixed as low level), and namely in figure, v (a) is 0 always.
As shown in the little figure of Fig. 8 bottom, bombardment simulation adopts double; two Exponential current source, bombard the moment of moment respectively t=32ns, 38ns, 53.5ns and 71.9ns, the bombardment analog current that four moment adopt is identical, and bombardment position all selects the outfan of second phase inverter in chain of inverters.
As shown in the little figure in the middle of Fig. 8, the output signal that v (y) is whole chain of inverters.Four double; two Exponential current pulses during the correspondence bombardment simulation respectively of four impulse waveforms in this signal waveform.Can find out intuitively from the analog waveform of signal y, when adopting static input vector and identical bombardment analogue signal, the occurrence of the circuit width of produced SET pulse this pulse width added up from table 1 completely the same when not being subject in the same time bombarding it is also seen that；Meanwhile, when adopting static input vector to test, circuit number of produced SET pulse after being subject to particle bombardment is on all four with the number of times bombarded.
Fig. 9 show and utilizes the present invention's to carry out the result of Hspice simulation based on SET pulse method of testing on the sheet of dynamic input vector.
This simulation adopts the test circuit shown in Fig. 5, and two chain of inverters therein are completely the same, and identical with the chain of inverters in circuit when adopting static input vector to be simulated.In Fig. 9, unification comprises 3 little figure, and in Fig. 9 shown in uppermost little figure, in this simulation process, input port a adopts dynamic input vector (input is a mechanical periodicity signal, and the signal period is 12ns).
As shown in the little figure of Fig. 9 bottom, bombardment simulation is same adopts double; two Exponential current source, in moment selected when being simulated with adopting static input vector in bombardment moment consistent (in the respectively moment of t=32ns, 38ns, 53.5ns and 71.9ns, the bombardment analog current that four moment adopt is identical), bombard position and all select the outfan of second phase inverter in chain of inverters 1.
As shown in the little figure in the middle of Fig. 9, when inputting four simulation bombardment pulses, but only observed three SET pulse at outfan y；Further, the width of viewed three SET pulse different (specifically the width value of each SET pulse is in Table 1).
In simulation process, along with the change in bombardment moment, the width of the number of the viewed SET pulse in output port y place and specifically certain SET pulse all can be varied from.
Table 1
In upper table " " represent that corresponding SET pulse is absent from.From the comparing result of upper table it can be concluded that under same bombarding conditions, adopt the mean breadth based on the number of the SET pulse measured by SET pulse method of testing on the sheet of dynamic input vector, the width of each SET pulse and each SET pulse etc. of the present invention all different based on the result measured by SET pulse method of testing on the sheet of static input vector with current.Adopt the present invention based on the result measured by SET pulse method of testing on the sheet of dynamic input vector by the situation of produced SET pulse when more conforming to be subject in circuit practical work process particle bombardment.
Claims (3)
1. based on SET pulse method of testing on the sheet of dynamic input vector, it is characterised in that comprise the steps of
The first step, designs based on SET pulse test circuit on the sheet of dynamic input vector；By two duplicate chain of inverters, being designated as the first chain of inverters, the second chain of inverters, XOR gate based on SET pulse test circuit on the sheet of dynamic input vector, SET pulse tilted object circuit is constituted；
First chain of inverters, the second chain of inverters are all connected with XOR gate, form by N level phase inverter, and N is the natural number more than 1, determines the size of N according to process and ion irradiation experimental enviroment；First chain of inverters, the second chain of inverters input connect together, as the input port of dynamic vector, from the sheet based on dynamic input vector SET pulse test circuit external receive a dynamic input vector；First chain of inverters, the second chain of inverters output connect two input ports of XOR gate respectively；
XOR gate and the first chain of inverters, the second chain of inverters, SET pulse tilted object circuit are connected, the output pulse of the first chain of inverters, the second chain of inverters is received from the first chain of inverters, the second chain of inverters, after the output pulse of the first chain of inverters, the second chain of inverters is carried out XOR, by output port, SET pulse is given the input port of SET pulse tilted object circuit；
SET pulse tilted object circuit is identical with the SET pulse tilted object circuit in background technology；SET pulse tilted object circuit is connected with XOR gate, external host；The input port of SET pulse tilted object circuit connects the output port of XOR gate, receives SET pulse from XOR gate, is exported SET pulse width to external host by output port after testing out SET pulse width；
Second step, powers on to SET pulse test circuit on the sheet based on dynamic input vector, and the input in chain of inverters loads input vector；
3rd step, is placed in SET pulse test circuit on the sheet based on dynamic input vector in particle radiation environment, utilizes the present invention based on SET pulse test circuit test SET pulse on the sheet of dynamic input vector；Through the test of SET pulse tilted object circuit, the SET pulse produced by circuit reality when outside host port obtains dynamic input vector.
2. as claimed in claim 1 based on SET pulse method of testing on the sheet of dynamic input vector, it is characterised in that the input vector that the input of described chain of inverters loads is static input vector or dynamic input vector.
3. as claimed in claim 2 based on SET pulse method of testing on the sheet of dynamic input vector, it is characterised in that described dynamic input vector is produced by crystal oscillator.
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| CN110988496A (en) * | 2019-12-13 | 2020-04-10 | 西安电子科技大学 | Three-way-test single-particle transient pulse width measuring circuit |
| CN110988496B (en) * | 2019-12-13 | 2021-05-11 | 西安电子科技大学 | Three-way-test single-particle transient pulse width measuring circuit |
| CN111342821A (en) * | 2020-03-03 | 2020-06-26 | 合肥工业大学 | Single-particle transient pulse generating and measuring system and method based on FPGA |
| CN113484604A (en) * | 2021-07-08 | 2021-10-08 | 中国人民解放军国防科技大学 | SET pulse measuring circuit capable of eliminating influence of measuring circuit and integrated circuit chip |
| CN113484604B (en) * | 2021-07-08 | 2023-04-21 | 中国人民解放军国防科技大学 | SET pulse measuring circuit capable of eliminating influence of measuring circuit and integrated circuit chip |
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