CN105866659A - Universal single-particle multi-transient-pulse distribution measurement method - Google Patents

Abstract

The invention discloses a general single-event multi-transient pulse distribution measurement method, which includes the following steps: the first step is to construct a target circuit for generating SEMT, which is used to generate single-event transient SET or single-event multi-transient SEMT; The second step is to build a SEMT capture circuit; the third step is to connect the target circuit and the SEMT capture circuit to form a test circuit; the fourth step is to construct a test chip and produce a test chip; the fifth step is to conduct a radiation experiment and conduct an online test in a radiation environment Measure SEMT pulse distribution. Compared with the existing SET capture circuit, the SEMT capture circuit in the present invention not only strengthens the trigger chain in it, but also can accurately obtain the SEMT pulse distribution information of the inverter unit, and can accurately obtain other The unit SEMT pulse distribution information avoids the measurement error caused by single event flipping/single event multi-bit flipping, and for the first time adopts the method of simultaneous capture by N capture circuits, which improves the measurement efficiency.

Description

A Universal Measurement Method of Single Event Multiple Transient Pulse Distribution

technical field

The invention relates to a method for measuring single-particle multi-transient in nanometer integrated circuits, in particular to a method for measuring the distribution of single-particle multi-transient pulses generated on transistors and circuit units in nanometer integrated circuits.

Background technique

In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions and neutrons, etc.) and high-energy rays. After the integrated circuit is bombarded by these high-energy particles and rays, a single event transient (Single Event Transient, SET for short) will be generated. The existence of single event transients greatly affects the normal operation of integrated circuits. For example, when a single event transient pulse propagates to a storage circuit, it will be transformed into a single event upset (Single Event Upset, referred to as SEU) if the corresponding timing constraints are met. ). With the continuous shrinking of the process size, the critical charge of each transistor state change in the integrated circuit continues to decrease, and the transistor density continues to increase. The probability of multiple transistors being bombarded by particles at the same time is greatly increased, and multiple transistors are bombarded at the same time. Multi-node charge collection occurs (Multi-node Charge Collection, referred to as MCC), and then trigger single event multiple transient (Single Event Multiple Transient, referred to as SEMT). The emergence of single event multiple transients will invalidate logic shielding in integrated circuits, and even invalidate traditional redundancy reinforcement technologies, posing a more serious threat to the normal operation of integrated circuits. Therefore, the invention of advanced single-event multi-transient measurement technology is particularly important for mastering the harm of single-event multi-transient to integrated circuits under advanced technology, developing single-event transient hardening technology, and realizing high-precision soft error analysis and evaluation.

Standard units such as inverters, NAND gates, and NOR gates are the basic units that make up integrated circuits. Therefore, understanding the occurrence of single event and multiple transients between standard units is conducive to more efficient reinforcement of the layout, thereby effectively improving Single Event Transient Immunity of Integrated Circuits. "Laser verification of charge sharing in a 90nm bulk CMOS process" published by O.A.Amusan et al. in IEEE Transaction on Nuclear Science (December 2009) No. 6, Volume 56, pages 3065-3070) proposed a laser measurement technology for multi-node charge collection of large-scale transistors, and took NMOS transistors as an example to illustrate the working mechanism of the measurement circuit. This technology places two large-sized NMOS tubes side by side at a certain distance, bombards one of them (referred to as the main device in this article) with laser light, and measures the charge collection on the two devices at the same time, so that the charge collection amount that is not directly bombarded can be obtained. The relationship between the charge collection amount of the transistor (referred to as the slave device in the text) and the laser energy, and the relationship between the charge collection amount of the slave device and the distance between the two transistors. This technique has enabled people to have a more rational understanding of MCC and SEMT; however, the drawbacks of this technique are also obvious, because the data of the charge collection amount of MCC obtained in the measurement is difficult to convert into the data of each transient pulse in SEMT. Pulse shape (such as width, amplitude, etc.) information. Later, W.G.Bennett and others published "Experimental characterization of radia-tion-induced charge sharing" (Experimental characterization of radiation-induced charge sharing) in IEEE Transaction on Nuclear Science (Journal of IEEE Atomic Energy Science) (No. 6, December 2013 Vol. 60, pp. 4159-4166) proposed another single-event multi-transient measurement method based on diodes. This method places four diodes on the four corners of a square, and the positions of the four diodes are symmetrical. Not only laser experiments, but also heavy ion experiments are carried out, and multiple transient current pulses induced by single particles are obtained. Although compared with the previous method, this experiment is not only suitable for heavy ion wide-beam experiments, but also can directly observe the generated single-particle multiple transient current pulses; however, the measurement of multiple current transient pulses in this method often relies on Due to the high-precision oscilloscope, the measured current transient pulses are often severely distorted; therefore, this method still cannot accurately measure the single event multiple transient characteristics in integrated circuits.

Contents of the invention

The technical problem to be solved by the present invention is: when the process size is reduced to 65nm and below, the single particle multiple transient induced by charge sharing in the integrated circuit becomes a common phenomenon, but the current single particle multiple transient measurement method cannot be accurate Therefore, the present invention proposes a general-purpose method for measuring single event and multiple transients in integrated circuits. The measurement circuit includes a target circuit and a SEMT capture circuit.

Technical scheme of the present invention is:

The first step is to construct the target circuit for generating SEMT, which is used to generate single-event transient SET or single-event multiple-transient SEMT, including the following steps:

1.1 According to the measurement target, select M1 similar standard cells from the standard cell library, such as inverters, NAND gates, etc., M1≥1, and M1 is an integer. For example, to measure the SEMT between inverters, select the inverter cells in M1 standard cell libraries, and to measure the SEMT between NAND gates, select the NAND gate cells in the M1 standard segment cell libraries.

1.2 String M1 selected standard units into an M1-level unit chain, and arrange each unit in the unit chain vertically in the shape of a longitudinal strip in the layout design.

1.3 On the layout, copy N-1 copies of the unit chain, and place N unit chains vertically and side by side at equal intervals in the layout, N≥2, and N is an integer.

1.4 Connect the inputs of the N unit chains to the output terminals of the logic constant 0 unit (Tie-Low) or the logic constant 1 unit (Tie-High) in the standard cell library.

The second step is to build the SEMT capture circuit

The SEMT capture circuit in the present invention is based on the proposed SET capture structure of B.Narasimham (published in IEEE Transaction on Device & Material Reliability <IEEE Device and Material Reliability Journal> Volume 6, Issue 4 in 2006, titled "On-chip Characterization of single event transient pulse widths"<online characterization of single event transient pulse width>) improved. The technology proposed by B. Narasimham is to use a trigger chain composed of dozens or hundreds of flip-flops in the capture circuit to convert the SET propagated on the inverter chain into a value and automatically latch it. If no SET is generated in the target circuit, the value in the flip-flop chain in the capture circuit is 01...0101...01 (or 10...1010...10); if there is a SET generated in the target circuit, the value in the capture circuit is The value in the flip-flop chain will become 01...1010...01 (or 10...0101...10). At this time, the number of flip-flops in the flip-flop chain in the capture circuit that continuously flips its value multiplied by the delay of the inverter is the pulse width of the SET to be tested. The SEMT capture circuit construction process among the present invention is as follows:

2.1 Construct N M2-level inverter chains and N M3-level D flip-flop chains. The selection of M2 is determined according to the designed measurement range of SEMT. M3 is a positive integer, and M2 is an integer multiple of M3.

2.2 Apply engineering-mature reinforcement technology (such as three-mode redundancy reinforcement, etc.) to each trigger in the N trigger chains to perform single-event flip reinforcement to avoid single-event flip or single-event multiple bits caused by particle bombardment of the trigger chain. Flips the interference measurement.

2.3 Set any inverter output terminal close to the midpoint (M2/2) in the N inverter chains as a self-trigger node, and construct N corresponding self-trigger circuits as described in B. Naramsimham's article ( 543 penultimate paragraph, penultimate paragraph 1 and 544 first paragraph).

2.4 The reset signals of the N self-triggering circuits are directly connected together so that the N capturing circuits can be reset at the same time after the SEMT capture is completed to prepare for the next SEMT capture.

The third step is to connect the target circuit and the SEMT capture circuit into a test circuit, the process is as follows:

The target circuit and the SEMT capture circuit are connected to form a measurement circuit by connecting the output terminals of the N M1-level unit chains to the input terminals of the corresponding M2-level inverter chains in the N capture circuits.

The fourth step is to construct the test chip and produce the test chip:

According to the relevant process of chip design and production, a number of test chips are produced, and the number of test chips is determined according to actual needs.

The fifth step is to conduct a radiation experiment and measure the SEMT pulse distribution online in a radiation environment. The process is as follows:

5.1 Place the test chip containing the target circuit and the SEMT capture circuit in a radiation environment, which can be a real radiation environment or a laboratory radiation environment;

5.2 Judging whether the radiation injection amount reaches the set value, if the radiation injection amount reaches the set value during the experiment (for example, when the radiation injection amount reaches 1e7ions/ ^cm2 in the heavy ion radiation environment, etc.), stop the online measurement, and measure all Save the collected SET or SEMT information, and the radiation experiment is over; otherwise, go to step 5.3;

5.3 When the particle bombards the target circuit, if it happens to pass through the sensitive area of one or several transistors, this or these transistors may produce SET or SEMT;

5.4 The generated SET or SEMT propagates forward along the unit chain, and when it reaches the end of the unit chain, it starts to propagate in the corresponding inverter chain in the SEMT capture circuit;

5.5 When SET or SEMT is transmitted to the self-trigger node, the trigger self-trigger circuit latches the SET or SEMT propagated on the inverter into the corresponding trigger chain in the capture circuit, and the trigger chain in the SEMT capture circuit keeps its The data remains unchanged, and sends a capture completion signal to an external test platform (such as an FPGA platform that can communicate with a test chip through programming) and waits for the external test platform to reset;

5.6 The external test platform reads out each SEMT pulse according to the capture completion signal, and sends it to the computer for graphic display through the serial port, and then sends a reset signal to the SEMT capture circuit in the test chip;

5.7 After the SEMT capture circuit receives the reset signal from the external test platform, it returns to the state where the SEMT can be captured, and then go to step 5.3.

The following technical effects can be achieved by adopting the present invention:

Compared with the SET capture circuit proposed by Narasimham, the SEMT capture circuit in the present invention not only strengthens the flip-flop chain therein, can accurately obtain the SEMT pulse distribution information of the inverter unit, and can accurately obtain the information in the standard cell library The SEMT pulse distribution information of other units avoids the measurement error caused by single event flipping/single event multi-bit flipping, and for the first time, N capture circuits are used to capture at the same time, which improves the measurement efficiency.

Description of drawings

Fig. 1 is the overall flow chart of general-purpose single-particle multi-transient pulse distribution measurement method of the present invention;

Fig. 2 is that the standard unit is an inverter unit as an embodiment, the schematic diagram of the target circuit constructed in the first step of the present invention;

Fig. 3 is the measurement circuit logic structure diagram that the first step and the second step of the present invention build;

FIG. 4 is a schematic diagram of a SEMT capture circuit constructed in the second step of the present invention, taking the example that M3 and M2 are equal.

detailed description

Fig. 1 is the overall flow chart of the general-purpose single event multi-transient pulse distribution measuring method of the present invention, comprises following flow process:

The first step is to construct the target circuit for generating SEMT, which is used to generate single-event transient SET or single-event multiple-transient SEMT, including the following steps:

1.5 According to the measurement target, select M1 similar standard cells from the standard cell library, such as inverters, NAND gates, etc., M1≥1, and M1 is an integer. For example, to measure the SEMT between inverters, select the inverter cells in M1 standard cell libraries, and to measure the SEMT between NAND gates, select the NAND gate cells in the M1 standard segment cell libraries.

1.6 String M1 selected standard units into an M1-level unit chain, and arrange each unit in the unit chain vertically in the shape of a longitudinal strip in the layout design.

1.7 On the layout, copy N-1 copies of the unit chain, and place N unit chains vertically and side by side at equal intervals in the layout, N≥2, and N is an integer.

1.8 Connect the inputs of the N unit chains to the output terminals of the logic constant 0 unit (Tie-Low) or the logic constant 1 (Tie-High) unit in the standard cell library.

The second step is to build the SEMT capture circuit, the process is as follows:

2.1 Construct N M2-level inverter chains and N M3-level D flip-flop chains. The selection of M2 is determined according to the designed measurement range of SEMT. M3 is a positive integer, and M2 is an integer multiple of M3.

2.2 Apply engineering-mature reinforcement technology (such as three-mode redundancy reinforcement, etc.) to each trigger in the N trigger chains to perform single-event flip reinforcement to avoid single-event flip or single-event multiple bits caused by particle bombardment of the trigger chain. Flips the interference measurement.

2.3 Set any inverter output terminal close to the midpoint (M2/2) in the N inverter chains as a self-trigger node, and construct N corresponding self-trigger circuits as described in B. Naramsimham's article ( 543 penultimate paragraph, penultimate paragraph 1 and 544 first paragraph).

2.4 The reset signals of the N self-triggering circuits are directly connected together so that the N capturing circuits can be reset at the same time after the SEMT capture is completed to prepare for the next SEMT capture.

The 3rd step, the measurement circuit of measuring SEMT distribution among the present invention is made up of two parts, and the first part is used to produce the target circuit of SEMT, and the second part is the SEMT capture circuit of capturing SET or SEMT, and target circuit and SEMT capture circuit are connected As shown in Figure 3 into the measurement circuit, the process is as follows:

The target circuit and the SEMT capture circuit are connected to form a measurement circuit by connecting the output terminals of the N M1-level unit chains to the input terminals of the corresponding M2-level inverter chains in the N capture circuits.

The fourth step is to construct the test chip and produce the test chip:

According to the relevant process of chip design and production, a number of test chips are produced.

The fifth step is to conduct a radiation experiment and measure the SEMT pulse distribution online in a radiation environment. The process is as follows:

5.1 Place the test chip containing the target circuit and the SEMT capture circuit in a radiation environment, which can be a real radiation environment or a laboratory radiation environment;

5.2 Judging whether the radiation injection amount reaches the set value, if the radiation injection amount reaches the set value during the experiment (for example, when the radiation injection amount reaches 1e7ions/ ^cm2 in the heavy ion radiation environment, etc.), stop the online measurement, and measure all Save the collected SET or SEMT information, and the radiation experiment is over; otherwise, go to step 5.3;

5.3 When the particle bombards the target circuit, if it happens to pass through the sensitive area of one or several transistors, this or these transistors may produce SET or SEMT;

5.4 The generated SET or SEMT propagates forward along the unit chain, and when it reaches the end of the unit chain, it starts to propagate in the corresponding inverter chain in the SEMT capture circuit;

5.5 When SET or SEMT is transmitted to the self-trigger node, the trigger self-trigger circuit latches the SET or SEMT propagated on the inverter into the corresponding trigger chain in the capture circuit, and the trigger chain in the SEMT capture circuit keeps its The data remains unchanged, and sends a capture completion signal to an external test platform (such as an FPGA platform that can communicate with a test chip through programming) and waits for the external test platform to reset;

5.6 The external test platform reads each SEMT pulse according to the capture completion signal and sends it to the computer through the serial port for graphic display, and then sends a reset signal to the SEMT capture circuit in the test chip;

5.7 After the SEMT capture circuit receives the reset signal from the external test platform, it returns to the state where the SEMT can be captured, and then go to step 5.3.

Fig. 2 is a schematic diagram of the target circuit constructed in the first step of the present invention, taking the standard cell as an inverter cell as an example. In this embodiment, M1 selected inverter units are connected in series to form an M1-level unit chain, and each unit in the unit chain is vertically arranged in the shape of a longitudinal strip in the layout design. Then, on the layout, copy N-1 copies of the unit chain, and place N unit chains vertically and side by side at equal intervals in the layout, N≥2, where N is an integer. Then, the inputs of the N unit chains are respectively connected to the output terminals of the logic constant 0 units in the standard unit library to form the target circuit of the present invention.

FIG. 4 is a schematic diagram of a SEMT capture circuit constructed in the second step of the present invention, taking the example that M3 and M2 are equal. It consists of an M2-level inverter chain and an M3 (M2 divisible by M3) level flip-flop chain, and the flip-flop is a D flip-flop (Data Flip-Flop, DFF) flip-flop. In this embodiment, M3 is equal to M2, and the output node of each stage of the inverter chain in the capture circuit is connected to the data input of the corresponding flip-flop in the flip-flop chain of the capture circuit. The dotted line represents the self-triggering signal of the self-trigger circuit, which is used to control each flip-flop to latch the output terminal signal of each inverter in the inverter chain as a value.

Claims (5)

1. a general-purpose single-event multi-transient pulse distribution measurement method, is characterized in that, comprises the following steps: The first step is to construct the target circuit for generating SEMT, which is used to generate single-event transient SET or single-event multiple-transient SEMT, including the following steps: 1.1 According to the measurement target, select M1 similar standard cells from the standard cell library, such as inverters, NAND gates, etc., M1≥1, M1 is an integer; 1.2 String M1 selected standard units into an M1-level unit chain, and arrange each unit in the unit chain vertically in the shape of a longitudinal strip in the layout design; 1.3 On the layout, copy N-1 copies of the unit chain, and place N unit chains vertically and side by side at equal intervals in the layout, N≥2, where N is an integer; 1.4 Connect the inputs of N unit chains to the output terminals of logic constant 0 units or logic constant 1 units in the standard cell library; The second step is to construct the SEMT capture circuit, including the following steps: 2.1 Construct N M2-level inverter chains and N M3-level D flip-flop chains. The selection of M2 is determined according to the designed measurement range of SEMT. M3 is a positive integer, and M2 is an integer multiple of M3; 2.2 Use mature reinforcement technology in engineering to carry out single event flip reinforcement for each trigger in the N trigger chains; 2.3 Set any inverter output near the midpoint in the N inverter chains as a self-trigger node, and construct N self-trigger circuits; 2.4 Connect the reset signals of N self-triggering circuits directly together; The third step is to connect the target circuit and the SEMT capture circuit into a test circuit, the process is as follows: By connecting the output terminals of N M1-level unit chains to the input terminals of the corresponding M2-level inverter chains in the N capture circuits, the target circuit and the SEMT capture circuit are connected to form a measurement circuit; The fourth step is to construct the test chip and produce the test chip; The fifth step is to conduct a radiation experiment and measure the SEMT pulse distribution online in a radiation environment. The process is as follows: 5.1 Place the test chip containing the target circuit and the SEMT capture circuit in a radiation environment, which can be a real radiation environment or a laboratory radiation environment; 5.2 Determine whether the radiation injection amount reaches the set value. If the radiation injection amount reaches the set value during the experiment, stop the online measurement, and save the collected SET or SEMT information, and the radiation experiment ends; otherwise, enter the step 5.3; 5.3 When the particle bombards the target circuit, if it happens to pass through the sensitive area of one or several transistors, this or these transistors may produce SET or SEMT; 5.4 The SET or SEMT generated by the target circuit propagates forward along the unit chain, and when it reaches the end of the unit chain, it starts to propagate in the corresponding inverter chain in the SEMT capture circuit; 5.5 When SET or SEMT is transmitted to the self-trigger node, the trigger self-trigger circuit latches the SET or SEMT propagated on the inverter into the corresponding trigger chain in the capture circuit, and the trigger chain in the SEMT capture circuit keeps its The data remains unchanged, and sends a capture completion signal to the external test platform that can communicate with the test chip through programming, and waits for the external test platform to reset; 5.6 The external test platform reads out each SEMT pulse according to the capture completion signal, sends it to the computer, and then sends a reset signal to the SEMT capture circuit in the test chip; 5.7 After the SEMT capture circuit receives the reset signal from the external test platform, it returns to the state where the SEMT can be captured, and then go to step 5.3. 2. The general-purpose single-event multi-transient pulse distribution measurement method according to claim 1, characterized in that, the single-event reversal reinforcement technology in the step 2.2 adopts a triple-mode redundancy reinforcement technology. 3. The general-purpose single-event multi-transient pulse distribution measurement method according to claim 1, characterized in that, the self-trigger circuit in the step 2.3 adopts the self-trigger circuit invented by B.Naramsimham. 4. The general-purpose single-event multi-transient pulse distribution measurement method according to claim 1, characterized in that, in said step 2.3, the output terminal of the M2/2 inverter is set as a self-trigger node. 5. the general-purpose single-event multi-transient pulse distribution measurement method as claimed in claim 1, is characterized in that, in the described step 5.5, external test platform adopts FPGA platform.