CN105866659A - Universal single-particle multi-transient-pulse distribution measurement method - Google Patents
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
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Abstract
The invention discloses a universal single-particle multi-transient-pulse distribution measurement method comprising the following steps that step one, a target circuit generating SEMT is constructed and used for generating single-particle transient SET or single-particle multi-transient SEMT; step two, an SEMT capture circuit is constructed; step three, the target circuit and the SEMT capture circuit are connected to form a test circuit; step four, a test chip is constructed and the test chip is produced; and step five, a radiation experiment is performed and SEMT pulse distribution is measured online in the radiation environment. The trigger chain of the SEMT capture circuit is strengthened in comparison with the existing SET capture circuit, inverter unit SEMT pulse distribution information can be accurately acquired, and other unit SEMT pulse distribution information in a standard unit library can be accurately acquired so that measurement error caused by single-particle upset/single-particle multiple-bit upsets can be avoided, and the method of performing capturing by using N capture circuits is firstly adopted and thus measurement efficiency is enhanced.
Description
Technical field
The present invention relates to the measuring method of the many transient states of single-particle in Nanometer integrated circuit, espespecially each transistor in Nanometer integrated circuit,
The measuring method of produced single-particle many transient pulses distribution on each circuit unit.
Background technology
In cosmic space, there is a large amount of high energy particle (proton, electronics, heavy ion and neutron etc.) and high-energy ray.Integrated
After the circuit bombardment by these high energy particles and ray, (Single Event Transient is called for short to produce single-ion transient state
SET).The existence of single-ion transient state greatly have impact on the normal work of integrated circuit, such as, when single event transient pulse passes
When casting to store circuit, if meeting corresponding temporal constraint, single-particle inversion (Single Event Upset, letter can be converted into
Claim SEU).Along with the continual reductions of process, the critical charge that in integrated circuit, each transistor state changes persistently reduces,
Transistor density continues to increase, and multiple transistors are greatly promoted by the probability of particle bombardment simultaneously, and multiple transistors are subject to simultaneously
Bombard and multinode charge-trapping (Multi-node Charge Collection is called for short MCC) occurs, and then cause single-particle many
Transient state (Single Event Multiple Transient is called for short SEMT).The appearance of the many transient states of single-particle can make integrated circuit
The shielding of middle logic was lost efficacy, and tradition redundancy reinforcement technique even can be made to lose efficacy, and work normal to integrated circuit constitutes even more serious prestige
The side of body.Therefore single-particle many instantaneous measurements technology of advanced person is invented, to the many transient states of single-particle under grasp advanced technologies to integrated circuit
Harm, exploitation single-ion transient state reinforcement technique and realization high accuracy soft error analysis are particularly important with assessment.
The standard blocks such as phase inverter, NAND gate, nor gate be composition integrated circuit elementary cell, therefore understand standard block it
Between single-particle many transient states production, be conducive to more efficiently domain being reinforced, thus be effectively improved integrated circuit
Anti-single particle transient state ability.O.A.Amusan et al. is at IEEE Transaction on Nuclear Science (IEEE atomic energy
Science journal) on " the Laser verification of charge sharing in a 90nm bulk CMOS process " that deliver (90 receive
The laser checking that under rice bulk silicon technological, electric charge is shared) (2009 December the 6th phase volume 56, the 3065-3070 page) proposed
A kind of laser measuring technique of large-size crystals pipe multinode charge-trapping, and as a example by nmos pass transistor, illustrate this measurement
The working mechanism of circuit.This technology is placed side by side by certain spacing by two large-sized NMOS tube, with laser bombardment its
In one (referred to herein as main device), measure the charge-trapping amount on two devices, it is hereby achieved that not by directly simultaneously
Bombard the relation between charge-trapping amount and the laser energy of transistor (referred to herein as from device) and from device charge-trapping amount
Relation with the spacing of two transistor.This technology makes people have the understanding of more rationality to MCC and SEMT；But,
The defect of this technology is also apparent from, because the charge-trapping amount data of the MCC obtained in Ce Lianging are difficult to be converted into SEMT
In pulse shape (such as width, the amplitude etc.) information of each transient pulse.Later, W.G.Bennett et al. was at IEEE Transaction
" the Experimental characterization of radia-delivered on Nuclear Science (IEEE atomic energy science journal)
Tion-induced charge sharing " (Experimental Characterization that radiation induced electric charge is shared) (December the 6th phase the 60th in 2013
Volume, the 4159-4166 page) propose the many transient measurement methods of another single-particle based on diode.The method is by four two
Pole pipe is placed on foursquare four angles, and the positional symmetry of four diodes not only carries out Laser Experiments, but also carries out
Heavy ion experiment, and obtain many transient current pulse of single-particle induction.Although for this experiment relatively former approach, no
Only can be suitably used for heavy ion wide beam to test, and the many transient current pulse of single-particle that generation can also be directly observed；But the party
In method, the measurement of many current transient pulse tends to rely on high accuracy oscillograph, thus measured current transient pulse is the tightest
Heavily distortion；Therefore the method still cannot weigh the many transient responses of single-particle in integrated circuit exactly.
Summary of the invention
The technical problem to be solved in the present invention is: process tapers in 65nm and following technique thereof, and in integrated circuit, electric charge is altogether
The many transient states of single-particle enjoying induction become a kind of universal phenomenon, and the many transient measurement methods of current single-particle can not reflect exactly
The many transient responses of single-particle in integrated circuit, thus the present invention proposes what a kind of transient state many to single-particle in integrated circuit measured
Universal method, its measuring circuit comprises objective circuit and SEMT captures circuit.
The technical scheme is that
The first step, builds the objective circuit producing SEMT, is used for producing single-ion transient state SET or single-particle many transient states SEMT,
Comprise the following steps:
1.1 according to measuring target, selects M1 similar standard block from standard cell lib, such as phase inverter, NAND gate etc.,
M1 >=1, M1 is integer.Such as, during SEMT between phase inverter to be measured, select in M1 standard cell lib
Inverter module, during SEMT between NAND gate to be measured, selects the NAND gate unit in M1 standard paragraphs unit storehouse.
The standard block that M1 is selected is conspired to create the cellular chain of M1 level by 1.2, and by list each in this cellular chain in layout design
Longitudinal elongate in shape is longitudinally put into by unit.
1.3 on domain, this cellular chain replicates N-1 part, and is placed the most side by side at domain intermediate reach by N number of cellular chain,
N >=2, N is integer.
The permanent Unit 0 (Tie-Low) of the logic that the input of N number of cellular chain is connected respectively in standard cell lib by 1.4 or logic are permanent
The outfan of 1 (Tie-High) unit.
Second step, builds SEMT and captures circuit
SEMT capture circuit proposed SET arresting structure based on B.Narasimham in the present invention (was delivered in 2006 years
At IEEE Transaction on Device&Material Reliability<IEEE device and reliability of material journal>volume 64
On phase, exercise question is " On-chip characterization of single event transient pulse widths " < single event transient pulse width
The online sign of degree >) improve and form.The technology that B.Narasimham proposes is to use dozens of or a hundred or so individual in capture circuit
The chain of flip-flops that constitutes of trigger the SET propagated in chain of inverters is changed into numerical value and automatically latches.If in objective circuit
Producing without SET, in this capture circuit, the numerical value in chain of flip-flops is 01 ... 0101 ... 01 (or 10 ... 1010 ... 10)；
If there being SET to produce in objective circuit, then in this capture circuit, the numerical value in chain of flip-flops will become 01 ... 1010 ... 01 (or
10……0101……10).At this moment the trigger number recurring numerical value upset in this capture circuit in chain of flip-flops is multiplied by instead
Phase device time delay is the pulse width of SET to be measured.SEMT capture circuit structure process in the present invention is as follows:
The chain of inverters of 2.1 structure N bar M2 levels and the d type flip flop chain of N bar M3 level, the selection gist of M2 is designed to be measured
The range of SEMT determines, M3 is positive integer, and M2 is the integral multiple of M3.
Reinforcement technique (such as triplication redundancy reinforcing etc.) ripe on each trigger application engineering in 2.2 pairs of N bar chain of flip-flops is carried out
Single-particle inversion is reinforced, to avoid single-particle inversion that particle bombardment chain of flip-flops causes or single event multiple bit upset interferometry to tie
Really.
Any inverter output at midpoint (M2/2) close in N bar chain of inverters is set as from trigger node by 2.3, and
Construct N number of correspondence as described in B.Naramsimham literary composition from flip-flop circuit (543 2nd section reciprocal, reciprocal 1st section and
Page 544 the 1st section).
The reset signal of N number of automatic triggering circuit is directly linked together by 2.4, in order to capture SEMT complete after can simultaneously by
N number of capture circuit carries out resetting and is ready for SEMT capture next time.
3rd step, captures circuit by objective circuit and SEMT and connects into test circuit, and flow process is as follows:
By the outfan of the cellular chain of N bar M1 level being connected the input of M2 level chain of inverters corresponding in N number of capture circuit
On end, objective circuit and SEMT are captured circuit and connects into measuring circuit.
4th step, constructs test chip and also produces test chip:
According to chip design and production related procedure, produce some test chips, depending on test number of chips is according to being actually needed.
5th step, carries out radiation experiments, on-line measurement SEMT distribution of pulses in radiation environment, and flow process is as follows:
The test chip capturing circuit containing objective circuit and SEMT is placed in radiation environment by 5.1, and radiation environment can be true
Radiation environment or laboratory radiation environment；
5.2 judge to radiate whether injection volume reaches setting value, if experimentation radiates injection rate reach set value (as weight from
Radiate injection rate under sub-radiation environment and reach 1e7ions/cm2Deng) time, stop on-line measurement, and to SET or SEMT gathered
Information preserves, and radiation experiments terminates；Otherwise, step 5.3 is entered；
5.3 when particle bombardment to objective circuit, if just through the sensitizing range of certain or certain several transistors, this or these
Transistor may produce SET or SEMT；
5.4 SET or SEMT produced propagate forward along cellular chain, pass to start during cellular chain end at SEMT capture electricity
Chain of inverters corresponding in road is propagated；
5.5 when SET or SEMT passes to from trigger node, trigger from flip-flop circuit by the SET propagated on phase inverter or
SEMT is latched in the capture circuit of correspondence in chain of flip-flops, and in SEMT capture circuit, chain of flip-flops keeps its data constant,
And to outside test platform (as FPGA platform etc. can by programming and test the platform that chip communicate) send capture and complete
Signal and wait external testing platform reset；
Test platform outside 5.6 completes signal according to capture and reads to walk by each SEMT pulse, and is sent to computer by serial ports
Carrying out figure to show, the SEMT capture circuit in right back testing chip sends reset signal；
5.7SEMT capture circuit, after external testing platform receives reset signal, is restored to capture the state of SEMT,
Go to step 5.3.
Use the present invention can reach techniques below effect:
In the present invention, SEMT capture circuit is for the SET capture circuit that Narasimham proposes, not only by therein
Chain of flip-flops is reinforced, and can obtain inverter module SEMT distribution of pulses information exactly, and can obtain standard exactly
Other cell S EMT distribution of pulses information in cell library, it is to avoid the measurement that single-particle inversion/single event multiple bit upset causes is by mistake
Difference, and have employed the mode that N number of capture circuit carries out capturing simultaneously first, improve measurement efficiency.
Accompanying drawing explanation
Fig. 1 is the overview flow chart of the present invention universal single-particle many transient pulses distribution measurement method；
Fig. 2 be with standard block be inverter module as embodiment, the first step of the present invention build objective circuit schematic diagram；
Fig. 3 is the first step of the present invention and the measuring circuit building-block of logic of second step structure；
Fig. 4 is equal as embodiment with M3 with M2, and the SEMT that second step of the present invention builds captures circuit diagram.
Detailed description of the invention
Fig. 1 is the overview flow chart of the present invention universal single-particle many transient pulses distribution measurement method, including below scheme:
The first step, builds the objective circuit producing SEMT, is used for producing single-ion transient state SET or single-particle many transient states SEMT,
Comprise the following steps:
1.5 according to measuring target, selects M1 similar standard block from standard cell lib, such as phase inverter, NAND gate etc.,
M1 >=1, M1 is integer.Such as, during SEMT between phase inverter to be measured, select in M1 standard cell lib
Inverter module, during SEMT between NAND gate to be measured, selects the NAND gate unit in M1 standard paragraphs unit storehouse.
The standard block that M1 is selected is conspired to create the cellular chain of M1 level by 1.6, and by list each in this cellular chain in layout design
Longitudinal elongate in shape is longitudinally put into by unit.
1.7 on domain, this cellular chain replicates N-1 part, and is placed the most side by side at domain intermediate reach by N number of cellular chain,
N >=2, N is integer.
The permanent Unit 0 (Tie-Low) of the logic that the input of N number of cellular chain is connected respectively in standard cell lib by 1.8 or logic are permanent
The outfan of 1 (Tie-High) unit.
Second step, builds SEMT and captures circuit, and flow process is as follows:
The chain of inverters of 2.1 structure N bar M2 levels and the d type flip flop chain of N bar M3 level, the selection gist of M2 is designed to be measured
The range of SEMT determines, M3 is positive integer, and M2 is the integral multiple of M3.
Reinforcement technique (such as triplication redundancy reinforcing etc.) ripe on each trigger application engineering in 2.2 pairs of N bar chain of flip-flops is carried out
Single-particle inversion is reinforced, to avoid single-particle inversion that particle bombardment chain of flip-flops causes or single event multiple bit upset interferometry to tie
Really.
Any inverter output at midpoint (M2/2) close in N bar chain of inverters is set as from trigger node by 2.3, and
Construct N number of correspondence as described in B.Naramsimham literary composition from flip-flop circuit (543 2nd section reciprocal, reciprocal 1st section and
Page 544 the 1st section).
The reset signal of N number of automatic triggering circuit is directly linked together by 2.4, in order to capture SEMT complete after can simultaneously by
N number of capture circuit carries out resetting and is ready for SEMT capture next time.
3rd step, the measuring circuit measuring SEMT distribution in the present invention is made up of two parts, and Part I is for producing SEMT
Objective circuit, Part II is that the SEMT of capture SET or SEMT captures circuit, objective circuit and SEMT is captured
Circuit connects into measuring circuit as shown in Figure 3, and flow process is as follows:
By the outfan of the cellular chain of N bar M1 level being connected the input of M2 level chain of inverters corresponding in N number of capture circuit
On end, objective circuit and SEMT are captured circuit and connects into measuring circuit.
4th step, constructs test chip and also produces test chip:
According to chip design and production related procedure, produce some test chips.
5th step, carries out radiation experiments, on-line measurement SEMT distribution of pulses in radiation environment, and flow process is as follows:
The test chip capturing circuit containing objective circuit and SEMT is placed in radiation environment by 5.1, and radiation environment can be true
Radiation environment or laboratory radiation environment；
5.2 judge to radiate whether injection volume reaches setting value, if experimentation radiates injection rate reach set value (as weight from
Radiate injection rate under sub-radiation environment and reach 1e7ions/cm2Deng) time, stop on-line measurement, and to SET or SEMT gathered
Information preserves, and radiation experiments terminates；Otherwise, step 5.3 is entered；
5.3 when particle bombardment to objective circuit, if just through the sensitizing range of certain or certain several transistors, this or these
Transistor may produce SET or SEMT；
5.4 SET or SEMT produced propagate forward along cellular chain, pass to start during cellular chain end at SEMT capture electricity
Chain of inverters corresponding in road is propagated；
5.5 when SET or SEMT passes to from trigger node, trigger from flip-flop circuit by the SET propagated on phase inverter or
SEMT is latched in the capture circuit of correspondence in chain of flip-flops, and in SEMT capture circuit, chain of flip-flops keeps its data constant,
And to outside test platform (as FPGA platform etc. can by programming and test the platform that chip communicate) send capture and complete
Signal and wait external testing platform reset；
Test platform outside 5.6 completes signal according to capture and reads to walk and be sent to computer by serial ports by each SEMT pulse
Row figure shows, the SEMT capture circuit in right back testing chip sends reset signal；
5.7SEMT capture circuit, after external testing platform receives reset signal, is restored to capture the state of SEMT,
Go to step 5.3.
Fig. 2 be with standard block be inverter module as embodiment, the objective circuit schematic diagram that the first step of the present invention builds.This
In embodiment, M1 selected inverter module conspires to create the cellular chain of M1 level, and by each in this cellular chain in layout design
Unit longitudinally puts into longitudinal elongate in shape.Then, on domain, this cellular chain is replicated N-1 part, and by N number of cellular chain
Placing the most side by side at domain intermediate reach, N >=2, N is integer.Then the input of N number of cellular chain is connected respectively to standard
The outfan of the permanent Unit 0 of the logic in cell library, constitutes the objective circuit of the present invention.
Fig. 4 is equal as embodiment with M3 with M2, and the SEMT that second step of the present invention builds captures circuit diagram.It by
The chain of flip-flops of the chain of inverters of M2 level and M3 (M2 divides exactly M3) level is constituted, trigger be d type flip flop (Data Flip-Flop,
DFF) trigger.In the present embodiment, M3 with M2 is equal, and in capture circuit, every grade of phase inverter output node of chain of inverters is even
Receive in the data input of corresponding trigger in capture circuit trigger device chain.Dotted line therein represents certainly touching from flip-flop circuit
Signaling, being used for controlling each trigger by inverter output signal latch each in chain of inverters is numerical value.
Claims (5)
1. universal single-particle many transient pulses distribution measurement method, it is characterised in that comprise the following steps:
The first step, builds the objective circuit producing SEMT, is used for producing single-ion transient state SET or single-particle many transient states SEMT,
Comprise the following steps:
1.1 according to measuring target, selects M1 similar standard block from standard cell lib, such as phase inverter, NAND gate etc.,
M1 >=1, M1 is integer；
The standard block that M1 is selected is conspired to create the cellular chain of M1 level by 1.2, and by list each in this cellular chain in layout design
Longitudinal elongate in shape is longitudinally put into by unit；
1.3 on domain, this cellular chain replicates N-1 part, and is placed the most side by side at domain intermediate reach by N number of cellular chain,
N >=2, N is integer；
The permanent Unit 0 of logic that the input of N number of cellular chain is connected respectively in standard cell lib by 1.4 or the permanent Unit 1 of logic defeated
Go out end；
Second step, builds SEMT and captures circuit, comprise the following steps:
The chain of inverters of 2.1 structure N bar M2 levels and the d type flip flop chain of N bar M3 level, the selection gist of M2 is designed to be measured
The range of SEMT determines, M3 is positive integer, and M2 is the integral multiple of M3；
Reinforcement technique ripe on each trigger application engineering in 2.2 pairs of N bar chain of flip-flops carries out single-particle inversion reinforcing；
Any inverter output at midpoint close in N bar chain of inverters is set as from trigger node by 2.3, and constructs N number of
From flip-flop circuit；
The reset signal of N number of automatic triggering circuit is directly linked together by 2.4；
3rd step, captures circuit by objective circuit and SEMT and connects into test circuit, and flow process is as follows:
By the outfan of the cellular chain of N bar M1 level being connected the input of M2 level chain of inverters corresponding in N number of capture circuit
On end, objective circuit and SEMT are captured circuit and connects into measuring circuit；
4th step, structure test chip also produces test chip；
5th step, carries out radiation experiments, on-line measurement SEMT distribution of pulses in radiation environment, and flow process is as follows:
The test chip capturing circuit containing objective circuit and SEMT is placed in radiation environment by 5.1, and radiation environment can be true
Radiation environment or laboratory radiation environment；
5.2 judge to radiate whether injection volume reaches setting value, if radiate the value that injection rate reaches set in experimentation, stop
On-line measurement, and SET or the SEMT information gathered is preserved, radiation experiments terminates；Otherwise, step 5.3 is entered；
5.3 when particle bombardment to objective circuit, if just through the sensitizing range of certain or certain several transistors, this or these
Transistor may produce SET or SEMT；
SET or SEMT that 5.4 objective circuits produce propagates forward along cellular chain, passes to start at SEMT during cellular chain end
Chain of inverters corresponding in capture circuit is propagated；
5.5 when SET or SEMT passes to from trigger node, trigger from flip-flop circuit by the SET propagated on phase inverter or
SEMT is latched in the capture circuit of correspondence in chain of flip-flops, and in SEMT capture circuit, chain of flip-flops keeps its data constant,
And complete signal to capture can be sent by the external testing platform that programming and test chip communicate, wait external testing platform
Reset；
Test platform outside 5.6 completes signal according to capture and reads to walk by each SEMT pulse, and is sent to computer, then to
SEMT capture circuit in test chip sends reset signal；
5.7SEMT capture circuit, after external testing platform receives reset signal, is restored to capture the state of SEMT,
Go to step 5.3.
Universal single-particle many transient pulses distribution measurement method the most as claimed in claim 1, it is characterised in that described step
In 2.2, single-particle inversion reinforcement technique uses triplication redundancy reinforcement technique.
Universal single-particle many transient pulses distribution measurement method the most as claimed in claim 1, it is characterised in that described step
In 2.3 from flip-flop circuit use B.Naramsimham invention from flip-flop circuit.
Universal single-particle many transient pulses distribution measurement method the most as claimed in claim 1, it is characterised in that described step
In 2.3, M2/2 inverter output is set as from trigger node.
Universal single-particle many transient pulses distribution measurement method the most as claimed in claim 1, it is characterised in that described step
5.5 peripheral test platforms use FPGA platform.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106405385A (en) * | 2016-08-31 | 2017-02-15 | 西北核技术研究所 | Trigger chain-based logic circuit single event effect test method |
| CN110988496A (en) * | 2019-12-13 | 2020-04-10 | 西安电子科技大学 | Three-way-test single-particle transient pulse width measuring circuit |
| CN111766438A (en) * | 2020-07-28 | 2020-10-13 | 哈尔滨工业大学 | Transient current test system and test method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101551421A (en) * | 2009-02-27 | 2009-10-07 | 北京时代民芯科技有限公司 | A structure of SET collecting and detecting circuit |
| US20100256937A1 (en) * | 2009-04-07 | 2010-10-07 | The Boeing Company | Method using time to digital converter for direct measurement of set pulse widths |
-
2016
- 2016-03-31 CN CN201610194323.8A patent/CN105866659B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101551421A (en) * | 2009-02-27 | 2009-10-07 | 北京时代民芯科技有限公司 | A structure of SET collecting and detecting circuit |
| US20100256937A1 (en) * | 2009-04-07 | 2010-10-07 | The Boeing Company | Method using time to digital converter for direct measurement of set pulse widths |
Non-Patent Citations (3)
| Title |
|---|
| BALAJI NARASIMHAM等: "On-Chip Characterization of Single-Event Transient Pulsewidths", 《IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY》 * |
| HE YIBAI等: "Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology", 《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》 * |
| 薛召召等: "单粒子瞬态脉冲窄化的试验测试电路设计", 《第十八届计算机工程与工艺年会暨第四届微处理器技术论坛论文集》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106405385A (en) * | 2016-08-31 | 2017-02-15 | 西北核技术研究所 | Trigger chain-based logic circuit single event effect test method |
| CN106405385B (en) * | 2016-08-31 | 2019-03-05 | 西北核技术研究所 | Logic circuit single particle effect test method based on chain of flip-flops |
| CN110988496A (en) * | 2019-12-13 | 2020-04-10 | 西安电子科技大学 | Three-way-test single-particle transient pulse width measuring circuit |
| CN110988496B (en) * | 2019-12-13 | 2021-05-11 | 西安电子科技大学 | Three-way-test single-particle transient pulse width measuring circuit |
| CN111766438A (en) * | 2020-07-28 | 2020-10-13 | 哈尔滨工业大学 | Transient current test system and test method thereof |
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| Publication number | Publication date |
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| CN105866659B (en) | 2018-05-25 |
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