CN111487472B - Circuit structure for measuring single-particle transient pulse width - Google Patents

Abstract

The invention discloses a circuit structure for measuring the width of a single-particle transient pulse, which comprises a control circuit, an attenuation unit, a delay unit, a drive Buffer and a counting circuit. The control circuit is used for controlling the pulse to be transmitted to a cycle structure formed by the circuit, the attenuation unit, the delay unit and the drive buffer after the single-particle transient pulse arrives. The attenuation unit is used for reducing the pulse width, and the delay unit is used for enabling the delay width of the circulating structure to be larger than the pulse width. The counting circuit utilizes a register and an adder to count the number of times that the pulse circulates in the circulating structure, a clock signal of the register is provided by the pulse without additional provision, and the measurement result of the width of the single-particle transient pulse is the amount of attenuation of each circulation multiplied by the number of times of the circulation. The circuit structure realized by the invention has the advantages of large measurable range and high measurement precision.

Description

A circuit structure for measuring single-particle transient pulse width

technical field

The invention relates to a circuit structure for measuring single-particle transient pulse width, in particular to a structure for realizing pulse attenuation by a certain amount of width and counting the pulse cycle times of a circuit by a cyclic structure, so as to measure single-particle transient pulses in a space radiation environment. state pulse width.

Background technique

Single Event Transient (SET) refers to the fact that when high-energy particles are incident on the sensitive area of the device, transient current pulses are generated in the device, resulting in circuit malfunction. Aerospace integrated circuits, because they work in the complex space irradiation environment, will affect the normal operation of the integrated circuits.

SET propagates down the data path in the circuit and may be latched by the sequential unit in the circuit, resulting in circuit system output failure and soft errors. In addition, the SET occurring on the cross-coupled inverter may cause flip-flops, SRAMs Wait until the storage state of the storage unit changes, that is, SEU. With the increasing demand for integrated circuit performance, the operating frequency of the circuit is increasing, but the soft error caused by SET in the combinational logic unit is proportional to the increase of the clock frequency. In digital circuits, SETs form transient voltage or current pulses. Although it does not directly cause cell toggling, it can propagate to the memory cell input to indirectly cause memory cell toggling. The reduction of the process size and the reduction of the operating voltage causes the SET pulse width to increase, the reduction of the gate delay causes the weakening of the electrical shielding, and the increase of the operating frequency increases the capture probability of the SET pulse width.

At present, the publicly reported circuit structures for measuring single-event transient pulse widths mainly use inverter chains and registers for measurement. Use inverter chain, latch chain, flip-flop chain and self-triggering circuit to input the transient pulse to the input of the inverter chain, and then realize the data transmission through each inverter with a latch and a flip-flop. recording and serial readout. If the single-particle pulse width is wide, the number of series required will be very large, and the consumption of hardware resources and power consumption will be very large.

In addition, there is a circuit structure that uses the counting principle in the structure to measure the single-particle transient pulse width, but its measurement accuracy is limited by the delay time of the minimum three-stage inverter and the time required for each counting process of the counter used therein. limit. In addition, a relatively complex microcontroller circuit is also used, which increases the difficulty of design, and at the same time consumes large hardware resources and power consumption.

SUMMARY OF THE INVENTION

The technical solution of the present invention is to overcome the deficiencies of the prior art and provide a circuit structure for measuring the transient pulse width of a single particle, including an attenuation unit that can control the attenuation of several picoseconds, a multiplexing cyclic structure, and a reduction in the number of electronic elements. The number of devices enables a wide range of measurable pulse widths, and at the same time improves the measurement accuracy of pulse widths.

The technical solution of the present invention is:

A circuit structure for measuring single-particle transient pulse width, including a control circuit, an attenuation unit, a delay unit, a driving buffer and a counting circuit, and a cyclic structure composed of a control circuit, an attenuation unit, a delay unit and a driving buffer is multiplexed, and the precision Set as the minimum delay time of the two-stage inverter;

The input terminal In1 of the control circuit is connected to the original pulse signal, and the output of the control circuit is used as the input of the first-stage attenuation unit. Using the different effects of different series inverters on the signal to be measured, the control pulse is first input to the attenuation unit and the attenuated The process of the pulse circulating in a cyclic structure;

The attenuation unit is used to attenuate a certain width of the pulse each time the unit passes through it;

The attenuation unit includes a NAND gate and an inverter. The delay time of the inverter between the two inputs of the NAND gate is the attenuation of the pulse passing through each attenuation unit. The number of inverters in this part is an even number. The number of inverters connected after the output of the NAND gate is an odd number, and the output of the last stage attenuation unit is the input of the first stage delay unit;

The delay unit is used to make the delay of the cyclic structure larger than the pulse width to be measured;

The delay unit is composed of an inverter. According to the different range of the pulse width to be measured, the width-length ratio of the MOS tube that constitutes the inverter is adjusted, and the output of the last stage of the delay unit is used as the input of the driving Buffer;

The driving Buffer is used to drive the pulse signal passing through the control circuit, several attenuation units and delay units;

The output of the drive Buffer is connected to the CLK terminal of the counting circuit and the input port In2 of the control circuit. After the falling edge of the pulse signal that has not been attenuated at first arrives, the transmission gate TG2 is controlled to open, and the pulse signal input from the input terminal In2 circulates. cycle through the structure.

Preferably, the control circuit realizes that the pulse is controlled to be transmitted to the attenuation unit after the pulse is input to the control circuit for the first time, and the control pulse is input to the attenuation unit again after each cycle in the cyclic structure.

Preferably, after the pulse is input to the control circuit for the first time, the pulse is controlled to be transmitted to the attenuation unit through the control circuit: the transmission gate TG1 is used, wherein the NMOS gate constituting the transmission gate TG1 is connected to the input terminal In1 of the control circuit after the pulse is input to the input terminal In1 of the control circuit. The output of the even-numbered stage inverter; the PMOS gate constituting the transmission gate TG1 is connected to the output of the odd-numbered stage inverter after the pulse is input to the input terminal In1 of the control circuit.

Preferably, after each cycle of the control circuit in the cyclic structure, the pulse is input into the attenuation unit again: use the transmission gate TG2, wherein the NMOS gate of TG2 is connected to the PMOS gate of TG1; the PMOS gate of TG2 is connected The pole is connected to the NMOS gate of TG1.

Preferably, a NAND gate and an inverter are used to realize the attenuation of the pulse width, and the two inputs of the NAND gate logic are connected to a signal of the same polarity, that is, both are connected to 0 or 1, and one input and the other input are separated by several There are even-numbered inverter units, and the number of inverters connected to the output of the NAND gate is an odd number.

Preferably, a cyclic structure composed of a control circuit, an attenuation unit, a delay unit and a driving buffer is used. After the pulse to be measured is input from the In1 terminal of the control circuit, it is connected to the input of the control circuit after passing through the attenuation unit, the delay unit and the driving buffer. terminal In2, so as to be input into the attenuation unit again, and so on in the cyclic structure.

Preferably, the pulse is connected to the CLK terminal of the register in the counting circuit through several attenuation units and delay units and the signal after driving the Buffer to provide the register with a clock signal.

Preferably, ResetB is the inverted signal of the reset signal Reset, ResetB is connected to the gate of the reset MOS transistor in the register circuit, and the input of the register circuit is connected to a transmission gate controlled by Reset and ResetB, in addition, the master-slave in the register circuit A transmission gate controlled by Reset and ResetB is added to the structure of Latch, and the above-mentioned structure realizes that when the reset signal Reset is 0, the data stored in the register is set to 0.

Preferably, the number of driving buffers is an even number.

Preferably, the control circuit is used to control the original pulse signal that has not been attenuated to be input into the attenuation unit, and then connected to the control circuit as its input signal after passing through several attenuation units, delay units and drive buffers. Provide reset signal.

The beneficial effects of the present invention are:

(1) A circuit structure for measuring single-particle transient pulse width provided by the present invention is based on a reusable loop structure and a counting circuit composed of an adder and a register. The characteristic that the range of the count can be increased exponentially by 2 makes the hardware cost of the circuit of the present invention very small;

(2) The measurement accuracy of the measurement circuit provided by the present invention is determined by the delay of the two-stage inverter, and the accuracy that can be provided under the existing process conditions is picosecond level, which greatly improves the measurement accuracy;

(3) The measurement range of the circuit structure provided by the present invention can be flexibly adjusted, the pulse width can be measured in a large range, and is better suited to various types of single-particle transient pulses.

Description of drawings

1 is a schematic diagram of a circuit structure of the present invention;

Fig. 2 is the structural diagram of the control circuit in the circuit structure of the present invention;

Fig. 3 is the circuit structure diagram of the attenuation unit in the circuit structure of the present invention;

Fig. 4 is the attenuation principle diagram of the attenuation unit in the circuit structure of the present invention;

5 is a circuit structure diagram of a delay unit in the circuit structure of the present invention;

Fig. 6 is the circuit structure diagram of register Reg unit in the circuit structure of the present invention;

FIG. 7 is a schematic diagram of a counting circuit in the circuit structure of the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

All features disclosed in this specification, or steps in all disclosed methods or processes, may be combined in any way except mutually exclusive features and/or steps.

Any feature disclosed in this specification, unless expressly stated otherwise, may be replaced by other equivalent or alternative features serving a similar purpose.

The invention obtains the width (time measure) of the pulse signal to be measured by detecting the cycle times of the single-particle transient pulse in the cyclic structure and multiplying it by the pulse decay value.

include:

Step 1: When the signal to be tested passes through several attenuation units and delay units, it is connected to the counting circuit as its clock signal.

Step 2: Every cycle, the clock signal of the counting circuit arrives once and counts once.

Step 3: Multiply the count result and the decay value per cycle in the cycle structure to obtain the width of the single-particle transient pulse to be measured.

FIG. 1 is a schematic diagram of the circuit structure of a single-particle transient pulse width measurement provided by an example of the present invention. It consists of a control circuit 101, an attenuation unit 102, a delay unit 103, a driving buffer 104 and a counting circuit 105, and the loop structure composed of the control circuit 101, the attenuation unit 102, the delay unit 103 and the driving buffer 104 is multiplexed, and its minimum measurement accuracy is two stage inverter minimum delay time.

FIG. 2 shows a specific circuit implementation form of the control circuit 101 . The control circuit 101 has an input terminal In1 of the initial pulse signal, and an input terminal In2 after the pulse is attenuated. The control circuit 101 also provides a reset signal, the reset signal Reset is connected to the input of the inverter 207, and the output thereof is ResetB. The pulse to be tested passes through the two-stage inverter 200 as the input of the inverter 201 , and is simultaneously connected to the gates of the NMOS of the transmission gate 203 and the PMOS of the transmission gate 206 . The gate of the PMOS in the transmission gate 203 and the gate of the NMOS 206 of the transmission gate are connected to the output of the inverter 201 , that is, the input of the inverter 202 . The purpose of this connection mode is that only one of the transmission gate 203 and the transmission gate 206 is in an open state when the pulse width is measured. When there is no pulse signal input, the In1 terminal always inputs 0, the transmission gate 203 is closed, and the transmission gate 206 is opened. Since there is no pulse with a rising edge input to the counting circuit, the counting circuit will not start counting in this case.

Before the formal measurement, the circuit should be reset. The reset signal is connected to 0 to make the reset signal valid. At this time, the input of the first-stage inverter 205 is set to 0 by using the pull-up transistor 204 whose input is ResetB. Connect the Reset signal to 1 when starting to measure the single-event pulse width. The pulse to be measured is input from the input terminal In1. When the signal changes from 0 to 1, according to the above-mentioned principle, the transmission gate 203 is in an open state and the transmission gate 206 is in a closed state. The pulse passes through the inverters 200, 201, and 202, and then passes through the transmission gate 203, and is connected to the two-stage inverter 205, and the output is Q1. When the pulse is transmitted from the In1 terminal, it starts to transmit the low level 0 signal again, after which the transmission gate 203 is closed, the transmission gate 206 is opened, and the pulse after passing through the loop structure is input from the input terminal In2.

FIG. 3 shows a circuit realization form of the first-stage attenuation unit 102 . The attenuation unit 102 is composed of inverters 301 , 302 , 303 and 304 , a NAND gate 305 , and three-stage inverters 306 , 307 and 308 . The input port of the attenuation unit is Q1, and the output port is Q2. The output terminal of the control circuit is connected to the input terminal of the attenuation unit of the first stage, and is transmitted in the unit, as follows:

The pulses are input from Q1 through inverters 301 and 302, and the output of 302 is used as one input of NAND gate 305 and the input of inverter 303. In order to improve the measurement accuracy, two-stage inverters 303 and 304 are selected in this example, of course, they can be flexibly adjusted according to different measurement requirements. The two-stage inverters 303 and 304 can control the measurement accuracy of the present invention to the order of a few picoseconds. The output of inverter 304 serves as the other input to the NAND gate. The output pulse width of NAND gate 305 will be attenuated by a certain amount due to the delay generated by the pulses passing through inverters 303 and 304 so that there is a certain time interval between the two inputs of the NAND gate. The output of the NAND gate 305 is connected to an odd number of inverters, 3 are selected in this example, which will adjust the 1-0-1 pulse to a 0-1-0 pulse, and then output to the next attenuation unit 102. input. According to the nature of the pulse to be measured, in addition to adjusting the number of stages of the delay inverters 303 and 304 to adapt to different pulse widths to be measured, the number of stages of the attenuation unit 102 can also be flexibly adjusted.

FIG. 4 shows the principle of pulse width attenuation realized by NAND gate 305 and delay inverters 303 and 304 .

FIG. 5 shows a specific circuit implementation form of the delay unit 103 in the present invention. It is mainly realized by an inverter, and the main purpose is to make the delay of the cyclic structure larger than the single-particle pulse width (time measurement) to be measured. According to the range of the measured pulse width, the width-length ratios of several inverters can be adjusted in the case of being proportional, or the width-length ratios of the inverters can be adjusted in the case of being inversely proportional. In the case of inverse ratio, it is an inverted tube, and the delay of the inverter formed by the inverted tube is larger. The output of the last stage delay unit 103 is connected to the two-stage driving buffer 104 . The output of the driving buffer 104 is connected to two ports, one is the CLK terminal of the register in the counting circuit, and the other is the In2 terminal of the control circuit 101 . As mentioned above, when the single-event pulse is transmitted from the In1 end of the inverter 200, it starts to transmit the 0 signal again. At this time, the transmission gate 203 is closed, the transmission gate 206 is opened, and the output of the two-stage driving buffer 104 is connected to the transmission gate 206. In2, it can be seen that the control circuit 101, the attenuation unit 102, the delay unit 103 and the driving buffer 104 constitute a cyclic structure.

FIG. 6 shows the specific realization and formation of the register Reg circuit in the counting circuit of the present invention. Its input terminal is connected to the sum of the adder at the same level, and the stored value is connected to an input terminal of the adder at the same level. The register circuit is mainly composed of transmission gates 601, 605, 612 controlled by a reset signal, transmission gates 602, 609 controlled by a clock signal, an inverter 608 that inverts the clock signal, a master-slave latch, and reset MOS transistors 603, 610. . When in the reset state before measurement, Reset is 0 and ResetB is 1 as described above. At this time, the transfer gates 601, 605, and 612 are in a closed state. Since the gates of the reset MOS transistors 603 and 610 are connected to ResetB, during the reset operation, the inputs of the master and slave latches are both 0, so the output Reg<n> of the register is reset to 0.

When in the measurement state, Reset is 1 and ResetB is 0 as described above. At this time, the transfer gates 601, 605, and 612 are in an open state. At this time, since the CLK signal is connected to the attenuated single-event pulse, it can provide rising and falling edges for the master-slave latch circuit, and this register circuit is triggered by the rising edge.

FIG. 7 is a schematic diagram showing the structure of the counting circuit of the present invention. Each stage includes a register unit and adder unit. Except that one input of the first-stage adder is DATA_IN, the other two inputs of the adder are the carry of the previous stage and the output of the register circuit of this stage. It should be noted that the DATA_IN signal is always at a high level of 1. At the same time, the number of unit stages composed of the register circuit and the adder circuit can be flexibly adjusted according to the number of pulse cycles. The increase of the number of stages makes the counting range increase exponentially by 2. Therefore, if the number of cycles is large, it will not consume a lot of energy. hardware resources. This example illustrates the measurement principle by taking the count of 1 and the count of 2 as examples. Since the reset is performed before the measurement, as mentioned above, Reg<0> and Reg<1> can be realized as 0. At this time, the two inputs of the first-stage adder are 1 and 0, and the sum S of this adder is is 1, C is 0 for carry; the two inputs of the second-stage adder are 0 and 0, the sum S of the adder is 0, and C is 0 for carry. At this time, the input INPUT of the first-level register becomes 1, but since its clock signal is 0, Reg<0> is still 0, and the input INPUT of the second-level register is 0 at the same time.

At the end of the reset operation, when the measurement is performed, when the pulse circulates once in the cyclic structure and is input to the CLK terminal, after its rising edge comes, Reg<0> is 1, and Reg<1> is still 0, if this pulse is in Its width decays to 0 (time measurement) when it loops for the second time, and the measurement result of the pulse width at this time is 1 multiplied by the decay width of the pulse in one cycle of the loop structure. If the width of the pulse does not decay to 0 after the second cycle, and it has not been transmitted to the CLK terminal at this time, since Reg<0> is 1, the S of the first-stage adder is 0, that is, the register circuit of the first-stage The input INPUT is 0, while the carry terminal C of the first-stage adder is 1, that is, the second-stage adder and S are 1, so the input INPUT of the second-stage register is 1.

When the attenuated pulse is input to the CLK terminal of the register for the second time, when the rising edge of CLK arrives, the value of the INPUT of the first stage is output to Reg<0>, so that Reg<0> is 0 and the second stage is The value of INPUT is output to Reg<1> so that Reg<1> is 1. At this time, Reg<1:0>=10, and this binary number is 2 when converted to decimal. If the pulse width decays to 0 on the third cycle (time meter), the measurement of the pulse width at this time is 2 times the decay width (time meter) of the pulse in one cycle of the cycle structure. By analogy, the pulse widths from three to N cycles can be easily calculated.

The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art. Although the embodiments of the present invention have been described with reference to the accompanying drawings, various changes or modifications may be made by those of ordinary skill in the art within the scope of the appended claims.

Claims (9)

1. A circuit structure for measuring the width of a single-particle transient pulse is characterized by comprising a control circuit (101), an attenuation unit (102), a delay unit (103), a drive Buffer (104) and a counting circuit (105), wherein a cycle structure formed by the control circuit (101), the attenuation unit (102), the delay unit (103) and the drive Buffer (104) is multiplexed, and the circuit measurement precision is determined by the delay of two stages of inverters;

an input end In1 of the control circuit (101) is connected with an original pulse signal, the output of the control circuit (101) is used as the input of the first-stage attenuation unit (102), the different functions of inverters with different stages on a signal to be detected are utilized to control the process that the pulse is firstly input into the attenuation unit (102) and the attenuated pulse circulates In a circulating structure;

the attenuation unit (102) is used for attenuating a certain width of the unit pulse every time when the unit pulse passes once;

the attenuation unit (102) comprises a NAND gate and inverters, the delay time of the inverter at intervals between two inputs of the NAND gate is the attenuation amount of a pulse passing through each attenuation unit, the number of the inverters at the part is even, the number of the inverters connected after the output of the NAND gate is odd, and the output of the last stage of attenuation unit (102) is the input of the first stage of delay unit (103);

the delay unit (103) is used for enabling the delay of the circulating structure to be larger than the pulse width to be measured;

the delay unit (103) is composed of inverters, the width-to-length ratio of MOS (metal oxide semiconductor) transistors forming the inverters is adjusted according to different ranges of pulse widths to be detected, and the output of the last-stage delay unit (103) is used as the input of a driving Buffer (104);

the driving Buffer (104) is used for driving pulse signals passing through the control circuit (101), the attenuation units (102) and the delay unit (103);

signals of pulses passing through a plurality of attenuation units (102), delay units (103) and driving buffers (104) are connected to a register CLK end in a counting circuit, and clock signals are provided for the register;

the output of the driving Buffer (104) is connected to the CLK terminal of the counting circuit and the input port In2 of the control circuit, and the transmission gate TG2 In the control circuit (101) is turned on after the falling edge of the pulse signal which has not been attenuated initially arrives, so that the pulse signal input from the input port In2 circulates In the circulation structure.

2. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, characterized in that the control circuit (101) is used for controlling the pulse to be transmitted to the attenuation unit (102) after the pulse is firstly input into the control circuit and controlling the pulse to be input into the attenuation unit (102) again after the pulse is circulated once in a circulating structure.

3. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, characterized in that the control circuit (101) is used for controlling the pulse to be transmitted to the attenuation unit (102) after the pulse is firstly input into the control circuit: using a transmission gate TG1, wherein an NMOS gate constituting a transmission gate TG1 connects the output of the inverter of the even-numbered stage after the pulse is input to the input terminal In1 of the control circuit; the PMOS gate constituting the transmission gate TG1 is connected to the output of the inverter of the odd-numbered stage after the pulse is input to the input terminal In1 of the control circuit.

4. The circuit structure for measuring the width of the single-event transient pulse according to claim 1, characterized in that the control circuit (101) controls the pulse to be input into the attenuation unit (102) again after one cycle in the cycle structure: a transmission gate TG2 is utilized, wherein an NMOS gate forming TG2 is connected with a PMOS gate of TG 1; the PMOS gate constituting TG2 is connected to the NMOS gate of TG 1.

5. The circuit structure for measuring the transient pulse width of the single event according to claim 1, wherein the attenuation of the pulse width is realized by using a nand gate and an inverter, two inputs of the nand gate logic are connected with signals with the same polarity, namely both are connected with 0 or 1, a plurality of even-numbered inverter units are arranged between one input and the other input, and the number of the inverters connected with the output of the nand gate is odd.

6. The circuit structure for measuring the width of the single-event transient pulse according to claim 1, wherein a cyclic structure consisting of the control circuit (101), the attenuation unit (102), the delay unit (103) and the driving Buffer (104) is utilized, and the pulse to be measured is input from the In1 end of the control circuit, passes through the attenuation unit (102), the delay unit (103) and the driving Buffer (104), and then is connected to the In2 end of the control circuit (101), and then is input into the attenuation unit (102) again, so that the pulse is circulated In the cyclic structure.

7. The circuit structure for measuring the width of the single-event transient pulse according to claim 1, wherein ResetB is an inverted signal of a Reset signal Reset, ResetB is connected to a gate of a Reset MOS transistor in a register circuit, an input of the register circuit is connected to a transmission gate controlled by Reset and ResetB, the transmission gate controlled by Reset and ResetB is added to a master-slave Latch structure in the register circuit, and the structure is used for setting the data stored in the register to 0 when the Reset signal Reset is 0.

8. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, wherein the number of driving buffers (104) is an even number.

9. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, wherein the control circuit (101) is used for controlling an original pulse signal which is not attenuated to be input into the attenuation unit (102), and the original pulse signal is connected to the control circuit (101) as an input signal after passing through the attenuation unit (102), the delay unit (103) and the drive Buffer (104).

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