CN111487472B

CN111487472B - Circuit structure for measuring single-particle transient pulse width

Info

Publication number: CN111487472B
Application number: CN202010247272.7A
Authority: CN
Inventors: 李同德; 赵元富; 陈雷; 王亮; 李建成; 孙永姝
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2022-08-05
Anticipated expiration: 2040-03-31
Also published as: CN111487472A

Abstract

The invention discloses a circuit structure for measuring the width of a single-particle transient pulse, which comprises a control circuit, an attenuation unit, a delay unit, a drive Buffer and a counting circuit. The control circuit is used for controlling the pulse to be transmitted to a cycle structure formed by the circuit, the attenuation unit, the delay unit and the drive buffer after the single-particle transient pulse arrives. The attenuation unit is used for reducing the pulse width, and the delay unit is used for enabling the delay width of the circulating structure to be larger than the pulse width. The counting circuit utilizes a register and an adder to count the number of times that the pulse circulates in the circulating structure, a clock signal of the register is provided by the pulse without additional provision, and the measurement result of the width of the single-particle transient pulse is the amount of attenuation of each circulation multiplied by the number of times of the circulation. The circuit structure realized by the invention has the advantages of large measurable range and high measurement precision.

Description

Circuit structure for measuring single-particle transient pulse width

Technical Field

The invention relates to a circuit structure for measuring the width of a single-particle transient pulse, in particular to a structure which realizes a certain amount of pulse attenuation by a cycle structure and counts the number of pulse cycles by a counting circuit so as to measure the width of the single-particle transient pulse in a space radiation environment.

Background

The single-particle transient effect (SET) is that when high-energy particles are incident on a sensitive region of a device, transient current pulses are generated in the device, and further a circuit function error is caused. The aerospace integrated circuit can influence the normal operation of the integrated circuit because the aerospace integrated circuit works in a complex space irradiation environment.

The SET propagates down a data path in the circuit and may be latched by a timing unit in the circuit, which may cause a malfunction of the output of the circuit system, a soft error occurs, and the SET occurring on the cross-coupled inverter may cause a change of a storage state of a storage unit such as a flip-flop, an SRAM, or the like, i.e., an SEU. With the increasing requirements of application requirements on the performance of integrated circuits, the operating frequency of the circuit is continuously increased, and soft errors caused by the SET in the combinational logic unit are in direct proportion to the increase of the clock frequency. In digital circuits, SET forms transient voltage or current pulses. Although it does not directly cause the memory cell to flip, it may propagate to the memory cell input to indirectly cause the memory cell to flip. The reduction of the process size and the reduction of the operating voltage cause the SET pulse width to increase, the reduction of the gate delay causes the electrical shielding to weaken, and the increase of the operating frequency causes the capture probability of the SET pulse width to increase.

At present, the circuit structure for measuring the width of a single-event transient pulse is disclosed and reported mainly uses an inverter chain and a register to cooperate for measurement. Transient pulses are input to the input of the inverter chain by using the inverter chain, the latch chain, the trigger chain and the self-triggering circuit, and then data recording and serial reading are realized by matching one latch and one trigger through each inverter. If the single-particle pulse width is wide, the required stage number is large, and consumed hardware resources, power consumption and the like are very large.

In addition, a circuit structure for measuring the width of the single-event transient pulse is also adopted, wherein the counting principle is used in the structure, but the measurement precision is limited by the delay time of a minimum three-stage inverter and the time required by each counting process of a counter used in the circuit structure. In addition, a relatively complex microcontroller circuit is used, so that the design difficulty is increased, and meanwhile, the consumed hardware resources and the power consumption are large.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the circuit structure comprises an attenuation unit capable of controlling the attenuation of picoseconds, and a multiplexing cycle structure, reduces the number of electronic components, ensures that the measurable pulse width range is large, and improves the measurement precision of the pulse width.

The technical solution of the invention is as follows:

a circuit structure for measuring the transient pulse width of a single particle comprises a control circuit, an attenuation unit, a delay unit, a drive Buffer and a counting circuit, wherein a circulating structure consisting of the control circuit, the attenuation unit, the delay unit and the drive Buffer is multiplexed, and the precision is set as the minimum delay time of two stages of inverters;

the input end In1 of the control circuit is connected with an original pulse signal, the output of the control circuit is used as the input of the first-stage attenuation unit, the different functions of the inverters with different stages on the signal to be detected are utilized to control the process that the pulse is input to the attenuation unit for the first time and the attenuated pulse circulates In the circulating structure;

the attenuation unit is used for attenuating a certain width of the unit pulse every time the unit pulse passes through the attenuation unit;

the attenuation units comprise NAND gates and inverters, the delay time of the inverter at intervals between two inputs of the NAND gates is the attenuation amount of a pulse passing through each attenuation unit, the number of the inverters is even, the number of the inverters connected after the output of the NAND gates is odd, and the output of the attenuation unit at the last stage is the input of the delay unit at the first stage;

the delay unit is used for enabling the delay of the circulating structure to be larger than the pulse width to be measured;

the delay unit is composed of phase inverters, the width-length ratio of MOS (metal oxide semiconductor) tubes forming the phase inverters is adjusted according to different ranges of pulse widths to be detected, and the output of the last stage of delay unit is used as the input of a driving Buffer;

the driving Buffer is used for driving pulse signals passing through the control circuit, the plurality of attenuation units and the delay unit;

the output of the driving Buffer is connected to the CLK terminal of the counting circuit and the input port In2 of the control circuit, the transmission gate TG2 is turned on after the falling edge of the pulse signal which has not been attenuated initially arrives, and the pulse signal inputted from the input port In2 circulates In a circulation structure.

Preferably, the control circuit is used to control the transmission of the pulse to the damping unit after the pulse is first input to the control circuit and to control the pulse to be input to the damping unit again after each cycle in the cyclic structure.

Preferably, the control circuit is used for controlling the pulse to be transmitted to the attenuation unit after the pulse is firstly input into the control circuit: using a transmission gate TG1, wherein an NMOS gate constituting a transmission gate TG1 connects the output of the inverter of the even-numbered stage after the pulse is input to the input terminal In1 of the control circuit; the PMOS gate constituting the transmission gate TG1 is connected to the output of the inverter of the odd-numbered stage after the input terminal In1 of the pulse input to the control circuit.

Preferably, after the pulse is controlled by the control circuit to circulate once in the cyclic structure, the pulse is input into the attenuation unit again: a transmission gate TG2 is utilized, wherein an NMOS gate forming TG2 is connected with a PMOS gate of TG 1; the PMOS gate constituting TG2 is connected to the NMOS gate of TG 1.

Preferably, the attenuation of the pulse width is realized by using a nand gate and inverters, two inputs of the nand gate logic are connected with signals of the same polarity, namely both connected with 0 or 1, a plurality of even-numbered inverter units are arranged between one input and the other input, and the number of the inverters connected with the output of the nand gate is odd.

Preferably, by using a circulating structure formed by the control circuit, the attenuation unit, the delay unit and the driving Buffer, after the pulse to be measured is input from the In1 end of the control circuit, the pulse to be measured passes through the attenuation unit, the delay unit and the driving Buffer, and then is connected to the In2 end of the control circuit, so as to be input into the attenuation unit again, and the pulse to be measured circulates In the circulating structure.

Preferably, the signals after the pulses pass through the attenuation units and the delay units and the driving Buffer are connected to the CLK terminal of the register in the counting circuit to provide clock signals for the register.

Preferably, ResetB is an inverse signal of the Reset signal Reset, ResetB is connected to the gate of the Reset MOS transistor in the register circuit, and the input of the register circuit is connected to a transmission gate controlled by Reset and ResetB, and the transmission gate controlled by Reset and ResetB is added to the structure of the master Latch and the slave Latch in the register circuit, so that the data stored in the register is set to 0 when the Reset signal Reset is 0.

Preferably, the number of driving buffers is an even number.

Preferably, the control circuit is configured to control an original pulse signal that has not been attenuated to be input to the attenuation unit, and to be connected to the control circuit as an input signal after passing through the plurality of attenuation units, the delay unit, and the drive Buffer, and the control circuit further provides a reset signal.

The invention has the beneficial effects that:

(1) the circuit structure for measuring the width of the single-event transient pulse is based on a reusable cycle structure and a counting circuit consisting of an adder and a register, and due to the multiplexing characteristic and the characteristic that the counting range can be increased by 2 exponential levels when the adder and the register are added at each level, the hardware cost of the circuit is very low;

(2) the measurement precision of the measurement circuit provided by the invention is determined by the delay of the 2-stage inverter, and the precision provided under the existing process condition is picosecond, so that the measurement precision is greatly improved;

(3) the circuit structure provided by the invention has the advantages that the measurement range can be flexibly adjusted, the measurable range of the pulse width is large, and the circuit structure is better suitable for various single-particle transient pulses.

Drawings

FIG. 1 is a schematic diagram of the circuit configuration of the present invention;

FIG. 2 is a block diagram of a control circuit in the circuit configuration of the present invention;

FIG. 3 is a circuit configuration diagram of an attenuating unit in the circuit configuration of the present invention;

FIG. 4 is a schematic diagram of the attenuation unit in the circuit configuration of the present invention;

FIG. 5 is a circuit diagram of a delay unit in the circuit configuration of the present invention;

FIG. 6 is a circuit diagram of a register Reg unit in the circuit structure of the present invention;

fig. 7 is a schematic diagram of a counting circuit in the circuit structure of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

All of the features disclosed in this specification, or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where mutually exclusive features and/or steps are present.

Any feature disclosed in this specification may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise.

The invention obtains the width (time measurement) of the pulse signal to be measured by detecting the cycle times of the single-particle transient pulse in the cycle structure and multiplying the cycle times by the pulse attenuation value.

The method comprises the following steps:

step 1: when the signal to be measured passes through a plurality of attenuation units and delay units, the signal to be measured is connected to the counting circuit to be used as the clock signal of the counting circuit.

Step 2: the clock signal of the counting circuit arrives once every cycle, and the counting is carried out once.

And step 3: and multiplying the counting result by the value of once attenuation in each cycle in the cycle structure to obtain the width of the single-particle transient pulse to be detected.

Fig. 1 is a schematic diagram of a circuit structure for measuring a single-event transient pulse width according to an embodiment of the present invention. The circuit comprises a control circuit 101, an attenuation unit 102, a delay unit 103, a drive Buffer104 and a counting circuit 105, wherein a circulating structure formed by the control circuit 101, the attenuation unit 102, the delay unit 103 and the drive Buffer104 is multiplexed, and the minimum measurement precision of the circuit is the minimum delay time of two stages of inverters.

Fig. 2 shows a specific circuit implementation form of the control circuit 101. The control circuit 101 has an input terminal In1 for initial pulse signal and an input terminal In2 for attenuated pulse. The control circuit 101 also provides a Reset signal, Reset to the input of inverter 207, the output of which is ResetB. The pulse to be measured passes through the two-stage inverter 200 and then serves as the input of the inverter 201, and is simultaneously connected to the NMOS gate of the transmission gate 203 and the PMOS gate of the transmission gate 206. The gate of the PMOS of the transmission gate 203 and the gate of the NMOS 206 of the transmission gate are connected to the output of the inverter 201 and the input of the inverter 202. The purpose of this connection is that only one of the transmission gate 203 and the transmission gate 206 is in an open state in the operating state for measuring the pulse width. When no pulse signal is input, 0 is always input to the In1 terminal, the transfer gate 203 is closed, the transfer gate 206 is opened, and no pulse having a rising edge is input to the counter circuit.

Before the formal measurement, the circuit should be Reset, the Reset signal is asserted with 0 being asserted, at which time the input of the first stage inverter 205 is set to 0 by the pull-up transistor 204 with input ResetB. When the single-particle pulse width measurement is started, the Reset signal is connected with 1. When a pulse to be measured is input from the input terminal In1, and the signal changes from 0 to 1, the transmission gate 203 is In the open state and the transmission gate 206 is In the closed state according to the principle described above. The pulse passes through

inverters

200, 201, and 202, then passes through transmission gate 203, and is coupled to two-stage inverter 205, and the output is Q1. When the pulse is transmitted from the In1 terminal, the transmission of the low level 0 signal is started again, and then the transmission gate 203 is closed, the transmission gate 206 is opened, and the pulse after passing through the cyclic structure is input from the input terminal In 2.

Fig. 3 shows a circuit implementation of the first stage attenuation unit 102. The attenuation unit 102 is composed of

inverters

301, 302, 303 and 304, a nand gate 305, and 3-

stage inverters

306, 307 and 308. The input port of the attenuation unit is Q1, and the output port of the attenuation unit is Q2. The output end of the control circuit is connected to the input end of the attenuation unit of the first stage and is transmitted in the unit, and the specific steps are as follows:

the pulse is input from Q1 through the outputs of

inverters

301 and 302, 302 as one input to nand gate 305 and the input to inverter 303. In order to improve the measurement accuracy, two stages of

inverters

303 and 304 are selected in the present example, which can be flexibly adjusted according to different measurement requirements. The two-

stage inverters

303 and 304 can control the measurement accuracy of the present invention to the order of several picoseconds. The output of inverter 304 serves as the other input to the nand gate. The output pulse width of nand gate 305 is attenuated by a certain amount because of the delay of the pulse through

inverters

303 and 304, which causes a certain time interval between the two inputs of the nand gate. The output of nand gate 305 is connected to an odd number of inverters, in this example 3, which will adjust the 1-0-1 pulse to a 0-1-0 pulse, and then output to the input of the next attenuation unit 102. According to the properties of the pulse to be measured, the number of stages of the attenuation units 102 can be flexibly adjusted, in addition to the adjustment of the number of stages of the

delay inverters

303 and 304 to adapt to different pulse widths to be measured.

Fig. 4 shows the principle of implementing pulse width attenuation by nand gate 305 and delay

inverters

303, 304.

Fig. 5 shows a specific circuit implementation of the delay unit 103 according to the present invention. The method is mainly realized by an inverter, and the main purpose is to enable the delay of a cycle structure to be larger than the width (time measurement) of the single-particle pulse to be measured. The width-to-length ratios of the inverters can be adjusted in a proportional manner or in an inversely proportional manner according to the range of the measured pulse width. In the case of inverse ratio, that is, inverse ratio tubes, the delay of the inverter formed by the inverse ratio tubes is larger. The output of the last stage of delay unit 103 is connected to two stages of driving buffers 104. The output of the drive Buffer104 is connected to two ports, one is the CLK terminal of the register In the counter circuit, and the other is the In2 terminal of the control circuit 101. As described above, when the single-particle pulse is transmitted from the In1 end of the inverter 200, the transmission of the 0 signal is started, the transmission gate 203 is closed, the transmission gate 206 is opened, and the output of the two-stage driving Buffer104 is connected to the In2 of the transmission gate 206, so that the control circuit 101, the attenuation unit 102, the delay unit 103, and the driving Buffer104 form a cyclic structure.

Fig. 6 shows a specific implementation of the register Reg circuit in the counting circuit according to the present invention. The input of which is connected to the sum of the same adder and the stored value of which is connected to one input of the same adder. The register circuit is mainly composed of

transmission gates

601, 605 and 612 controlled by a reset signal,

transmission gates

602 and 609 controlled by a clock signal, an inverter 608 for inverting the clock signal, and master-slave latch and reset

MOS transistors

603 and 610. When in the Reset state before measurement, Reset is 0 and ResetB is 1 as described above. At this time, the

transmission gates

601, 605, and 612 are in a closed state. Since the gates of the

reset MOS transistors

603 and 610 are connected to ResetB, the inputs of the master and slave latches are both 0 when the reset operation is performed, and thus the output Reg < n > of the register is reset to 0.

When in the measured state, Reset is 1 and ResetB is 0 as described above. At this time, the

transmission gates

601, 605, and 612 are in an open state. At this time, since the CLK signal is connected with the attenuated single-event pulse, a rising edge and a falling edge can be provided for the master-slave latch circuit, and the register circuit is triggered by the rising edge.

Fig. 7 is a schematic structural diagram of a counting circuit according to the present invention. Each stage comprises a register unit and an adder unit. Except that one input of the adder at the first stage is DATA _ IN, two inputs of the remaining adders are the carry of the previous stage and the output of the register circuit at the present stage. Note that the DATA _ IN signal is directly high at 1. Meanwhile, the number of stages of a unit formed by the register circuit and the adder circuit can be flexibly adjusted according to the number of pulse cycles, and the increase of the number of stages enables the counting range to be increased in2 exponential stages, so that the number of cycles is assumed to be more, and large hardware resources are not consumed. This example illustrates the measurement principle with a count of 1 and a count of 2. Because reset is carried out before measurement, Reg <0> and Reg <1> can be 0 as described above, two inputs of the first-stage adder are 1 and 0 at the moment, the sum S of the adder is 1, and C is 0 when the carry is carried out; the two inputs of the second stage adder are 0 and 0, the sum of the adder is 0, and the carry of C is 0. At this time, INPUT of the first level register becomes 1, but Reg <0> is still 0 because its clock signal is 0, while INPUT of the second level register is 0.

At the end of the reset operation, when a pulse is cycled once in a cyclic structure and input to the CLK terminal, after the rising edge of the pulse arrives, Reg <0> is 1, and Reg <1> is still 0, if the width of the pulse is attenuated to 0 (time measurement) at the second time of the cycle, the measurement result of the pulse width is 1 times the attenuation width of the pulse cycled once in the cyclic structure. If the pulse is not attenuated to 0 after the second cycle, and is not transmitted to the CLK terminal, since Reg <0> is 1, S of the first-stage adder is 0, that is, the INPUT of the register circuit of the first stage is 0, and the carry terminal C of the first-stage adder is 1, that is, the sum of the second-stage adder and S is 1, the INPUT of the register of the second stage is 1.

When the attenuated pulse is INPUT to the CLK terminal of the register for the second time, the value of the first stage INPUT is output to Reg <0> when the rising edge of CLK comes, so that Reg <0> is 0 while the value of the second stage INPUT is output to Reg <1> so that Reg <1> is 1. In this case, Reg <1:0> is 10, and this binary number is converted to decimal number 2. If the pulse decays to 0 (time scale) in its width at the third cycle, the pulse width measurement is then 2 times the decay width of the pulse once it has cycled through the cycle (time scale). By analogy, the pulse width of the pulse circulating three times to N times can be conveniently calculated.

Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art. Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various changes or modifications within the scope of the appended claims.

Claims

1. A circuit structure for measuring the width of a single-particle transient pulse is characterized by comprising a control circuit (101), an attenuation unit (102), a delay unit (103), a drive Buffer (104) and a counting circuit (105), wherein a cycle structure formed by the control circuit (101), the attenuation unit (102), the delay unit (103) and the drive Buffer (104) is multiplexed, and the circuit measurement precision is determined by the delay of two stages of inverters;

an input end In1 of the control circuit (101) is connected with an original pulse signal, the output of the control circuit (101) is used as the input of the first-stage attenuation unit (102), the different functions of inverters with different stages on a signal to be detected are utilized to control the process that the pulse is firstly input into the attenuation unit (102) and the attenuated pulse circulates In a circulating structure;

the attenuation unit (102) is used for attenuating a certain width of the unit pulse every time when the unit pulse passes once;

the attenuation unit (102) comprises a NAND gate and inverters, the delay time of the inverter at intervals between two inputs of the NAND gate is the attenuation amount of a pulse passing through each attenuation unit, the number of the inverters at the part is even, the number of the inverters connected after the output of the NAND gate is odd, and the output of the last stage of attenuation unit (102) is the input of the first stage of delay unit (103);

the delay unit (103) is used for enabling the delay of the circulating structure to be larger than the pulse width to be measured;

the delay unit (103) is composed of inverters, the width-to-length ratio of MOS (metal oxide semiconductor) transistors forming the inverters is adjusted according to different ranges of pulse widths to be detected, and the output of the last-stage delay unit (103) is used as the input of a driving Buffer (104);

the driving Buffer (104) is used for driving pulse signals passing through the control circuit (101), the attenuation units (102) and the delay unit (103);

signals of pulses passing through a plurality of attenuation units (102), delay units (103) and driving buffers (104) are connected to a register CLK end in a counting circuit, and clock signals are provided for the register;

the output of the driving Buffer (104) is connected to the CLK terminal of the counting circuit and the input port In2 of the control circuit, and the transmission gate TG2 In the control circuit (101) is turned on after the falling edge of the pulse signal which has not been attenuated initially arrives, so that the pulse signal input from the input port In2 circulates In the circulation structure.

2. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, characterized in that the control circuit (101) is used for controlling the pulse to be transmitted to the attenuation unit (102) after the pulse is firstly input into the control circuit and controlling the pulse to be input into the attenuation unit (102) again after the pulse is circulated once in a circulating structure.

3. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, characterized in that the control circuit (101) is used for controlling the pulse to be transmitted to the attenuation unit (102) after the pulse is firstly input into the control circuit: using a transmission gate TG1, wherein an NMOS gate constituting a transmission gate TG1 connects the output of the inverter of the even-numbered stage after the pulse is input to the input terminal In1 of the control circuit; the PMOS gate constituting the transmission gate TG1 is connected to the output of the inverter of the odd-numbered stage after the pulse is input to the input terminal In1 of the control circuit.

4. The circuit structure for measuring the width of the single-event transient pulse according to claim 1, characterized in that the control circuit (101) controls the pulse to be input into the attenuation unit (102) again after one cycle in the cycle structure: a transmission gate TG2 is utilized, wherein an NMOS gate forming TG2 is connected with a PMOS gate of TG 1; the PMOS gate constituting TG2 is connected to the NMOS gate of TG 1.

5. The circuit structure for measuring the transient pulse width of the single event according to claim 1, wherein the attenuation of the pulse width is realized by using a nand gate and an inverter, two inputs of the nand gate logic are connected with signals with the same polarity, namely both are connected with 0 or 1, a plurality of even-numbered inverter units are arranged between one input and the other input, and the number of the inverters connected with the output of the nand gate is odd.

6. The circuit structure for measuring the width of the single-event transient pulse according to claim 1, wherein a cyclic structure consisting of the control circuit (101), the attenuation unit (102), the delay unit (103) and the driving Buffer (104) is utilized, and the pulse to be measured is input from the In1 end of the control circuit, passes through the attenuation unit (102), the delay unit (103) and the driving Buffer (104), and then is connected to the In2 end of the control circuit (101), and then is input into the attenuation unit (102) again, so that the pulse is circulated In the cyclic structure.

7. The circuit structure for measuring the width of the single-event transient pulse according to claim 1, wherein ResetB is an inverted signal of a Reset signal Reset, ResetB is connected to a gate of a Reset MOS transistor in a register circuit, an input of the register circuit is connected to a transmission gate controlled by Reset and ResetB, the transmission gate controlled by Reset and ResetB is added to a master-slave Latch structure in the register circuit, and the structure is used for setting the data stored in the register to 0 when the Reset signal Reset is 0.

8. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, wherein the number of driving buffers (104) is an even number.

9. The circuit structure for measuring the width of a single-event transient pulse according to claim 1, wherein the control circuit (101) is used for controlling an original pulse signal which is not attenuated to be input into the attenuation unit (102), and the original pulse signal is connected to the control circuit (101) as an input signal after passing through the attenuation unit (102), the delay unit (103) and the drive Buffer (104).