CN108233904B - Anti-transient effect gate - Google Patents
Anti-transient effect gate Download PDFInfo
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- CN108233904B CN108233904B CN201810018806.1A CN201810018806A CN108233904B CN 108233904 B CN108233904 B CN 108233904B CN 201810018806 A CN201810018806 A CN 201810018806A CN 108233904 B CN108233904 B CN 108233904B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Abstract
The application discloses anti-transient effect's gate relates to digital electronics technical field, the gate includes: the logic and operation unit receives the gating signal SEL and the delay signal, performs logic and operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sends a SEL1 signal to a grid electrode of the transistor M3; the logic OR operation unit receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a grid electrode of the transistor M6; an inverter that receives the SEL1 signal and the SEL2 signal, and sends the SEL1B signal that is a SEL1 inverted signal and the SEL2B signal that is a SEL2 inverted signal, and sends the SEL1B signal to the gate of transistor M5; the SEL2B signal is sent to the gate of transistor M4. The technical problem that if an error signal is captured by a storage unit in a circuit, soft errors are caused, and system failure is caused in the prior art is solved.
Description
Technical Field
The application relates to the technical field of digital electronics, in particular to a transient effect resistant gating device.
Background
The gate MUX is an important digital circuit structure and is also based on the main constituent unit of the SRAM type FPGA.
However, in the process of implementing the technical solution in the embodiment of the present application, the applicant of the present application finds that the above prior art has at least the following technical problems:
in the prior art, as the gating signal of the gating device is easily influenced by the radiation of space particles, a single-particle transient SET is generated, and an error signal is selected by the MUX to be output. If the error signal is captured by a memory cell in the circuit, a soft error may be caused, which may cause a technical problem of system failure.
Content of application
The embodiment of the application provides a transient effect resistant gate, and the technical problems that in the prior art, if an error signal is captured by a storage unit in a circuit, a soft error is caused and a system fails are solved through the gate, so that the technical effect of avoiding outputting the error signal when a selection signal SEL is influenced on the premise of keeping the circuit area small is achieved.
The embodiment of the application provides a transient effect resistant gating device, wherein the collecting device comprises: the delay unit receives a gating signal SEL, delays the gating signal SEL and obtains a delay signal; the logic AND operation unit receives the gating signal SEL and the delay signal, performs logic AND operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sends a SEL1 signal to a grid electrode of the transistor M3; the logic OR operation unit receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a grid electrode of the transistor M6; an inverter that receives the SEL1 signal and the SEL2 signal, and sends the SEL1B signal that is a SEL1 inverted signal and the SEL2B signal that is a SEL2 inverted signal, and sends the SEL1B signal to the gate of transistor M5; sending the SEL2B signal to the gate of transistor M4; wherein, the inverted signal of the first signal a is used as the gates of the transistor M1 and the transistor M7; the inverted signal of the second signal B serves as the gates of the transistor M2 and the transistor M8.
Preferably, the gate further includes: the delay unit is composed of four phase inverters connected end to end.
Preferably, the gate further includes: the logic output of the gate is: OUT is A (! SEL) + B.SEL; when SEL is equal to 1, selecting a B signal to output to OUT; when SEL is 0, the selection a signal is output to OUT, where a denotes a first signal a and B denotes a first signal B.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
the embodiment of the application provides an anti-transient effect gate, which comprises: the delay unit receives a gating signal SEL, delays the gating signal SEL and obtains a delay signal; the logic AND operation unit receives the gating signal SEL and the delay signal, performs logic AND operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sends a SEL1 signal to a grid electrode of the transistor M3; the logic OR operation unit receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a grid electrode of the transistor M6; an inverter that receives the SEL1 signal and the SEL2 signal, and sends the SEL1B signal that is a SEL1 inverted signal and the SEL2B signal that is a SEL2 inverted signal, and sends the SEL1B signal to the gate of transistor M5; sending the SEL2B signal to the gate of transistor M4; wherein, the inverted signal of the first signal a is used as the gates of the transistor M1 and the transistor M7; the inverted signal of the second signal B serves as the gates of the transistor M2 and the transistor M8. The technical problem that soft errors can be caused and a system fails due to the fact that error signals are captured by a storage unit in a circuit in the prior art is solved, and the technical effect that when a selection signal SEL is influenced, the output of the error signals is avoided on the premise that the circuit area is kept small is achieved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a transient effect resistant gate provided in the present application;
description of reference numerals: 1-delay unit, 2-logical AND operation unit, 3-logical OR operation unit, 4-inverter.
Detailed Description
The embodiment of the application provides a transient effect resistant gate, and solves the technical problem that in the prior art, if an error signal is captured by a storage unit in a circuit, a soft error is caused, and a system fails.
The technical scheme in the embodiment of the application has the following general structure: the delay unit receives a gating signal SEL, delays the gating signal SEL and obtains a delay signal; the logic AND operation unit receives the gating signal SEL and the delay signal, performs logic AND operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sends a SEL1 signal to a grid electrode of the transistor M3; the logic OR operation unit receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a grid electrode of the transistor M6; an inverter that receives the SEL1 signal and the SEL2 signal, and sends the SEL1B signal that is a SEL1 inverted signal and the SEL2B signal that is a SEL2 inverted signal, and sends the SEL1B signal to the gate of transistor M5; sending the SEL2B signal to the gate of transistor M4; wherein, the inverted signal of the first signal a is used as the gates of the transistor M1 and the transistor M7; the inverted signal of the second signal B serves as the gates of the transistor M2 and the transistor M8. The technical effect of avoiding outputting wrong signals when the selection signal SEL is influenced on the premise of keeping the circuit area small is achieved.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
An embodiment of the present application provides a transient effect resistant gate, please refer to fig. 1, the gate includes:
the delay unit 1 receives a gating signal SEL, delays the gating signal SEL and obtains a delay signal; the delay unit 1 is composed of four phase inverters connected end to end.
Specifically, the delay unit 1 may be composed of four inverters connected end to end, and the delay unit is configured to delay an input signal, and may delay the input signal by one period or delay the input signal by a corresponding period according to an actual situation, so as to delay the received signal, thereby obtaining the delayed signal.
The logic and operation unit 2 is used for receiving the gating signal SEL and the delay signal, performing logic and operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sending a SEL1 signal to a grid electrode of the transistor M3;
in particular, logical operators (logical operators) are commonly used to test for false and true values. The most common logical operation is the processing of a loop to determine whether the instruction leaves the loop or continues to execute within the loop. In the logical and operation, the symbol is and. Only true if both are true. In the embodiment of the present application, the and logic unit 2 receives the gate signal and the delay signal, performs an and logic operation on the gate signal and the delay signal to obtain an SEL1 signal, where the SEL1 signal is a signal obtained by performing an and logic operation on the gate signal and the delay signal, and then sends the SEL1 signal to the gate of the transistor M3.
The logic OR operation unit 3 receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a gate of the transistor M6;
specifically, in a logical Or operation, the symbol is represented as Or. In the embodiment of the present application, the or logic unit 3 receives the gating signal and the delay signal, performs a logical or operation on the gating signal and the delay signal to obtain a SEL2 signal, where the SEL2 signal is a signal obtained by performing a logical or operation on the gating signal and the delay signal, and then sends the SEL2 signal to the gate of the transistor M6.
An inverter 4 receiving the SEL1 signal and the SEL2 signal, and sending a SEL1B signal that is a SEL1 inverted signal and a SEL2B signal that is a SEL2 inverted signal, and sending the SEL1B signal to the gate of transistor M5; sending the SEL2B signal to the gate of transistor M4;
specifically, the inverter 4 may invert the phase of the input signal by 180 degrees, for example, if the signal level of the input signal to the inverter 4 is 1, the output signal changes from 1, which is originally input, to 0 after passing through the inverter 4, and if the input signal is 0, the output signal from the inverter 4 changes to 1. In the embodiment of the present application, the output ends of the or unit 2 and the or unit 3 are respectively connected to an inverter 4, the inverter 4 inverts the SEL1 signal and the SEL2 signal to obtain a SEL1B signal and a SEL2B signal, wherein the SEL1B signal is an inverted signal of a SEL1 signal, the SEL2B signal is an inverted signal of a SEL2 signal, and then the SEL1B signal is sent to the gate of the transistor M5; the SEL2B signal is sent to the gate of transistor M4.
Wherein, the inverted signal of the first signal a is used as the gates of the transistor M1 and the transistor M7; the inverted signal of the second signal B serves as the gates of the transistor M2 and the transistor M8. The logic output of the gate is: OUT is A (! SEL) + B.SEL; when SEL is equal to 1, selecting a B signal to output to OUT; when SEL is 0, the selection a signal is output to OUT, where a denotes a first signal a and B denotes a first signal B.
Specifically, the logic output realized by the scheme of the invention is as follows:
OUT＝A·(！SEL)+B·SEL
when SEL is 1, selecting the B signal to output to OUT; when SEL is equal to 0, selecting the A signal and outputting the A signal to OUT;
the invention can process the influence of the SEL signal on the single event transient, and can be divided into the following conditions in total:
SEL is 1, and is not influenced by single-event transient. SEL1 and SEL2 are both 1, M3 and M5 are both off, and M4 and M6 are both on. If B is logic 0, M8 is turned on and M2 is turned off, OUT is pulled down to the ground through a path formed by M6 and M8, and the logic value of B is output as 0; if B is 1, M2 is turned on and M7 is turned off, OUT is pulled up to VDD through the path formed by M2 and M4, and B is output with a logic value of 1. The ERROR signal obtained by XOR of the inverse signals SEL1B and SEL2B of SEL1 and SEL2 is 0, so that M9, M10 and M11 are conducted, and the operation of the whole multiplexer is not influenced.
SEL is 0 and is not affected by single event transients. SEL1 and SEL2 are both 0, M4 and M6 are both off, and M3 and M5 are both on. If A is logic 0, M7 is turned on and M1 is turned off, OUT is pulled down to the ground through a path formed by M5 and M7, and the logic value of A is output as 0; if the logic of A is 1, M1 is turned on and M7 is turned off, and OUT is pulled up to VDD through the path formed by M1 and M3, and the logic value of A is output as 1. The ERROR signal obtained by XOR of the inverse signals SEL1B and SEL2B of SEL1 and SEL2 is 0, so that M9, M10 and M11 are conducted, and the operation of the whole multiplexer is not influenced.
SEL is 1, and the jump becomes 0 due to the single event transient. The SEL signal passing through Delay module Delay is still 1, so the SEL1 signal is 0 and the SEL2 signal is 1. The ERROR signal obtained by the exclusive-or operation is 1, M9, M10 and M11 are turned off, and the OUTPUT becomes a floating state and keeps the original logic state in a short time. After the transient effect is over, SEL1 and SEL2 restore to the same logic value, and OUT ends the floating state. In the transient effect, because the logic values of the SEL1 and SEL2 signals are opposite, the ERROR signal is high, so that the path from VDD to GND of the MUX does not exist, and the increase of power consumption is avoided.
When SEL1B and SEL2B are affected by a single event transient, resulting in different logic values for the two, this situation is similar to when SEL1 or SEL2 are affected. The ERROR signal obtained by the XOR gate XOR is 1, M9, M10 and M11 are turned off, and the OUTPUT becomes a floating state and maintains the original logic state in a short time. After the transient effect is over, SEL1B and SEL2B restore to the same logic value, and OUT ends the floating state.
SEL is 0, and the transition to 1 is affected by a single-event transient. The analysis can be made with reference to the above case.
When the selected signal a or B is affected, OUTPUT produces a transient pulse, after which the correct level is restored. The stability of the signals a and B should be taken into account by the combinational logic circuit generating these two signals and is not the focus of the inventive solution.
According to the embodiment of the application, the technical problem that soft errors can be caused and the system fails due to the fact that error signals are captured by the storage unit in the circuit in the prior art is solved through the technical scheme, and the technical effect that when the selection signal SEL is influenced, the output of the error signals is avoided on the premise that the circuit area is small is achieved.
The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages:
the embodiment of the application provides an anti-transient effect gate, which comprises: the delay unit receives a gating signal SEL, delays the gating signal SEL and obtains a delay signal; the logic AND operation unit receives the gating signal SEL and the delay signal, performs logic AND operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sends a SEL1 signal to a grid electrode of the transistor M3; the logic OR operation unit receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a grid electrode of the transistor M6; an inverter that receives the SEL1 signal and the SEL2 signal, and sends the SEL1B signal that is a SEL1 inverted signal and the SEL2B signal that is a SEL2 inverted signal, and sends the SEL1B signal to the gate of transistor M5; sending the SEL2B signal to the gate of transistor M4; wherein, the inverted signal of the first signal a is used as the gates of the transistor M1 and the transistor M7; the inverted signal of the second signal B serves as the gates of the transistor M2 and the transistor M8. The technical problem that soft errors can be caused and a system fails due to the fact that error signals are captured by a storage unit in a circuit in the prior art is solved, and the technical effect that when a selection signal SEL is influenced, the output of the error signals is avoided on the premise that the circuit area is kept small is achieved.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.
Claims (1)
1. An anti-transient effect gate, comprising:
the delay unit receives a gating signal SEL, delays the gating signal SEL and obtains a delay signal;
the logic AND operation unit receives the gating signal SEL and the delay signal, performs logic AND operation on the gating signal SEL and the delay signal to obtain a SEL1 signal, and sends a SEL1 signal to a grid electrode of the transistor M3;
the logic OR operation unit receives the gating signal SEL and the delay signal, performs logic OR operation on the gating signal SEL and the delay signal to obtain a SEL2 signal, and sends a SEL2 signal to a grid electrode of the transistor M6;
an inverter that receives the SEL1 signal and the SEL2 signal, and sends the SEL1B signal that is a SEL1 inverted signal and the SEL2B signal that is a SEL2 inverted signal, and sends the SEL1B signal to the gate of transistor M5; sending the SEL2B signal to the gate of transistor M4;
wherein, the inverted signal of the first signal a is used as the gates of the transistor M1 and the transistor M7; the inverted signal of the second signal B serves as the gates of the transistor M2 and the transistor M8;
the delay unit consists of four phase inverters connected end to end;
wherein the gate further comprises:
the logic output of the gate is:
(ii) a Wherein the content of the first and second substances,
when SEL =1, the B signal is selected to be output to OUT; selecting an a signal to output to OUT when SEL =0, wherein a represents a first signal a and B represents a first signal B;
when the SEL is equal to 1 and is influenced by a single-particle transient, the SEL jumps to 0, the SEL signal passing through the Delay module Delay is still 1, therefore, the SEL1 signal is 0, the SEL2 signal is 1, the inverse signals SEL1B and SEL2B of SEL1 and SEL2 are input into an exclusive-or operation unit, the ERROR signal obtained by exclusive-or operation is 1, the ERROR signal is sent to the M9, M10 and M11 transistors, M9, M10 and M11 are turned off, the OUTPUT becomes a floating state and keeps the original logic state in a short time, after the transient effect is finished, the SEL1 and SEL2 recover to the same logic value, the OUT finishes the floating state, and when the transient effect is finished, because the logic values of the SEL1 and SEL2 signals are opposite, the ERROR signal is high level, so that a path from a power supply terminal VDD to a ground terminal is not existed in the MUX, and GND (GND) is prevented from being increased.
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