CN102818939A - Measuring circuit for single-event transient pulse width - Google Patents
Measuring circuit for single-event transient pulse width Download PDFInfo
- Publication number
- CN102818939A CN102818939A CN2011101522310A CN201110152231A CN102818939A CN 102818939 A CN102818939 A CN 102818939A CN 2011101522310 A CN2011101522310 A CN 2011101522310A CN 201110152231 A CN201110152231 A CN 201110152231A CN 102818939 A CN102818939 A CN 102818939A
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- output
- bistable
- particle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a measuring circuit for single-event transient pulse width. The measuring circuit for single-event transient pulse width comprises a single-event pulse signal generating circuit (103) and at least one measuring circuit. Primary stage of the measuring circuit consists of a bistable circuit. From the second stage, each stage of the measuring circuit comprises a delay circuit, a logic gate circuit and a bistable circuit. In the second stage, input signal of the delay circuit is signal to be measured, input signal of the logic gate circuit serves as output signal of the delay circuit and output signal of the first-stage bistable circuit, and output signal of the logic gate circuit serves as input signal of the bistable circuit in the second stage. From the third stage, the input signal of the delay circuit in each stage serves as the output signal of the logic gate circuit in the previous stage, the input signal of the logic gate circuit serves as the output signal of the current-stage delay circuit and the output signal of the previous bistable circuit, and the output signal of the current-stage logic gate circuit serves as the input signal of the current-stage bistable circuit. The measuring circuit is capable of measuring within a wide pulse width range and is high in measuring precision.
Description
Technical field
The present invention relates to the electronic pulse width field of measuring technique, particularly a kind of single-particle transient pulse width measure circuit.
Background technology
Along with the development of art such as space flight, military affairs, increasing integrated circuit need be worked under radiation environment.Radiation mainly is divided into two big types to the effect of integrated circuit: single particle effect and total dose effect; Total dose effect is that integrated circuit is in the radiation environment for a long time; The effect that the radiation effect accumulation is produced; Single particle effect is after the emittance particle gets into integrated circuit, the effect that the radiation effect instant effect is produced.Wherein single particle effect can be subdivided into three types:
1, single-particle soft error effects: comprise the single-particle reversal effect, the single-event transients effect, the single-particle effect etc. of overturning produces circuit node and disturbs at short notice.
2, the effect that has potential danger property:,, may cause chip generation single-particle to burn as not controlling like the single event latch-up effect.
3, single hard error effect like displacement damage etc., can make that the transistor in the chip thoroughly can not be worked.
Wherein, the single-event transients effect is the common principal element that influences chip performance, when chip is placed in the environment of radiation; The ambient energy particle can be injected into chip internal; Electronics, hole through producing some on the movement locus of energy ionizing radiation particle are right, and they are absorbed by circuit node under effect of electric field, change the node level; If there is not backfeed loop; After the time of single-particle effect finished, this node level can recover back original value again, thereby in circuit, produces a pulse signal so.
Study and reinforce for single particle effect, must build effective test environment, characteristics such as the transient pulse deration of signal are accurately measured.Wherein test environment is often selected the ground irradiation experiment, produces cosmic-ray particle through simulation and chip to be measured is bombarded test, cosmic space that is virtually reality like reality radiation environment.When the pulse signals width was measured, according to differences such as incident particle kind energy, the single-particle pulse signal level of generation was held time also different, and pulse width can be from more than tens ps to, thousand ps.If adopt checkout equipments such as traditional oscillograph or logic analyser to measure single-particle transient pulse width, very high to the frequency requirement of equipment, domestic often can not production and forbid output abroad, testing cost is high, realizes that difficulty is very big.If adopting on-chip circuit tests; Existing pulse width measuring method is often sampled through outside input high-frequency signal pulse signals and is measured; Therefore catch frequency and the performance impact that precision receives sampled signal, also be difficult to provide very high frequency in the actual test, the sampled signal that the waveform characteristics are very good again; It is little to survey scope, and measuring accuracy is low.
Summary of the invention
One of the object of the invention provides a kind of single-particle transient pulse signal pulse width that is used to measure; Need not add sampling clock in the test process; And can be directed against the measured signal characteristics; Through change circuit size and progression, confirm the single-particle transient pulse width measure circuit of suitable sampling precision and output figure place.
According to an aspect of the present invention, a kind of single-particle transient pulse width measure circuit is provided, comprises that single-particle pulse signal generating circuit (103) reaches one-level metering circuit at least; Said single-particle pulse signal generating circuit (103) produces single-particle pulse signal to be measured; Wherein, the bistable circuit (100) that is directly driven by single-particle pulse signal to be measured constitutes the first order of metering circuit; Begin from the second level of metering circuit, each grade circuit comprises delay circuit (101), logic gates (102) and bistable circuit (100) respectively;
Wherein in the circuit of the second level, the input signal of delay circuit (101) is a measured signal; The input signal of logic gates (102) is the output signal of this delay circuit (101) and the output signal of first order bistable circuit (100); The output signal of logic gates (102) is the input signal of bistable circuit at the corresponding levels (100);
Begin from tertiary circuit: the source of said delay circuits at different levels (101) input signal is the output signal of upper level logic gates (102); The input signal of said logic gates (102) is the output signal of delay circuit at the corresponding levels (101) and the output signal of upper level bistable circuit (100); The output signal of logic gates at the corresponding levels (102) is the input signal of bistable circuit at the corresponding levels (100).
Further; Said bistable circuit (100) has two steady state (SS)s, and before single-particle pulse signal to be measured was measured, output can be in a definite steady state (SS); When importing single-particle pulse signal to be measured and measure; As long as input signal upset takes place and keeps the sufficiently long time, bistable circuit can be turned to another steady state (SS) from a steady state (SS), and output signal level changes.
Further; When said delay circuit (101) input signal is a pulse signal; Output also is pulse signal; And the zero hour that output pulse signal changes, in the variation of output signals moment of higher level's bistable circuit (100), the variation of output signals that is later than higher level's bistable circuit (100) finish time that output pulse signal changes constantly in advance.
Further, when said logic gates (102) all changed at the output signal of the output signal of delay circuit at the corresponding levels (101) and upper level bistable circuit (100), the output signal just changed.
Further, the structure of the bistable circuits of selecting for use at different levels (100), delay circuit (101) and logic gates (102) is identical or different.
Further, the output terminal of said bistable circuit (100) only has an output terminal to draw or draw simultaneously two complementary output ends;
When bistable circuit had only an output terminal to draw, this end is metering circuit input end of output terminal (out end) and next stage logic gates (102) as a result simultaneously;
When bistable circuit has two complementary output ends to draw, with two output terminals respectively as the metering circuit input end of output terminal (out end) and next stage logic gates (102) as a result.
Can control every grade of output result respectively according to the sum of series circuit structure of single-particle transient pulse width measure circuit provided by the invention through changing circuit, size etc.; Can regulate the measuring accuracy of test figure place and every grade of comparison; The characteristics that better are fit to the single-particle transient pulse of surveying; It is big to survey pulse width range, and measuring accuracy is high.
Description of drawings
Fig. 1 is the single-particle transient pulse width measure electrical block diagram that the embodiment of the invention provides.
The bistable circuit that Fig. 2 provides for the embodiment of the invention is the structural representation of RS latch.
Fig. 3 is the structural representation of two-stage phase inverter cascade for the delay circuit 101 that the embodiment of the invention provides.
The synoptic diagram of the delay circuit working condition that Fig. 4 provides for the embodiment of the invention.
The logic gates that Fig. 5 provides for the embodiment of the invention for the synoptic diagram of door.
The waveform synoptic diagram of the single-particle transient pulse width measure circuit overall operation that Fig. 6 provides for the embodiment of the invention.
Embodiment
Single-particle transient pulse width measure circuit as shown in Figure 1, that the embodiment of the invention provides comprises that single-particle pulse signal generating circuit (103) reaches one-level metering circuit (for example, can be made up of 4 grades of circuit, according to the needs of measuring, be not limited thereto certainly) at least.
Wherein, constitute the first order of metering circuit by measured signal single-particle pulse (this single-particle pulse signal to be measured is produced by the single-particle pulse signal generating circuit 103) bistable circuit 100 that directly drives.Begin from the second level of metering circuit, each grade circuit comprises delay circuit 101, logic gates 102 and bistable circuit 100 respectively; Wherein, in the circuit of the second level: the input signal of delay circuit 101 is measured signals.The input signal of logic gates 102 is the output signal of this delay circuit 101 and the output signal of first order bistable circuit 100.The output signal of logic gates 102 is input signals of bistable circuit 100 at the corresponding levels.
Begin from tertiary circuit: the source of delay circuit 101 input signals at different levels is output signals of upper level logic gates 102.The input signal of logic gates 102 is the output signal of delay circuit 101 at the corresponding levels and the output signal of upper level bistable circuit 100.The output signal of logic gates 102 at the corresponding levels is input signals of bistable circuit 100 at the corresponding levels.
When said delay circuit 101 input signals are pulse signal; Output also is pulse signal; And the zero hour that output pulse signal changes, in the variation of output signals moment of higher level's bistable circuit 100, the variation of output signals that is later than higher level's bistable circuit 100 finish time that output pulse signal changes constantly in advance.
The output terminal of bistable circuit 100 can only have an output terminal to draw or draw simultaneously two complementary output ends; When bistable circuit had only an output terminal to draw, this end was simultaneously as the metering circuit input end of output terminal (out end) and next stage logic gates 102 as a result; When bistable circuit has two complementary output ends to draw, can be with two output terminals respectively as the metering circuit input end of output terminal out end and next stage logic gates 102 as a result.
The structure of the bistable circuit of selecting for use at different levels 100, delay circuit 101 and logic gates 102 can be the same or different.
Wherein, bistable circuits 100 at different levels are chosen as basic RS latch.Fig. 2 is a RS latch synoptic diagram, before the single-particle pulse signal changes, can keep a stable status in order to guarantee the RS latch, and the R input end of latchs at different levels is connected on the unified reset signal.With the S signal input part of RS latch, as the input signal end, out1, out2 ... wait the Q output terminal that connects corresponding latch respectively, this end offers logic gates simultaneously and makes input end.
Referring to Fig. 3, delay circuit 101 is that the cascade of two-stage phase inverter constitutes, and wherein PMOS pipe breadth length ratio is 1.5/0.18, and NMOS pipe breadth length ratio is 0.5/0.18.Delay circuits 101 at different levels should be selected suitable circuit size according to the level duration of input pulse, make the output signal of delay circuit 101 at the corresponding levels change the output signal variation early than upper level bistable circuit 100.In the side circuit design process; Can be according to the level duration of input pulse to be measured; Adopt emulation mode,, make the output switching activity situation of latchs at different levels adhere to specification more with the corresponding relation between the pulse width through attempting different circuits size and circuit structure.
Referring to Fig. 4; Input is the input signal of delay circuit at the corresponding levels, and a1 is the output signal of delay circuit at the corresponding levels, and out1 is higher level's latch output signal; The zero hour of the variation of the output signal a1 of delay circuit, promptly the rising edge of a1 shifts to an earlier date in the variation of the output out1 of higher level's latch; The finish time that a1 changes, promptly the negative edge of a1 is later than the variation of out1, adheres to specification.This moment is through the operation of logic gates at the corresponding levels; The output deration of signal of logic gates is the width of a1 when being high level with out1; This width is shorter than the width of input signal, thereby makes the input signal that inputs to RS latchs at different levels shorten step by step, for given input pulse width; When test circuit progression was abundant, the input pulse width of what latch should be short to and is not enough to drive this latch and overturns at last.The pulse width of input is wide more, and the latch progression that can drive upset is many more, and the measurement result of input pulse width can compare through the latch number of upset.
Referring to Fig. 5, logic gates 102 is and door.Adopt Sheffer stroke gate to constitute with the form of not gate cascade with door, wherein PMOS pipe breadth length ratio is 1.5/0.18, and NMOS pipe breadth length ratio is 0.5/0.18.Input signal is respectively input1 and input2, and the output signal is out.Only when the output signal of the output signal of delay circuit 101 at the corresponding levels and upper level bistable circuit 100 all changed, the output signal just changed logic gates 102 at different levels.
Referring to Fig. 6, the signal of the waveform of single-particle transient pulse width measure circuit overall operation situation of the present invention, wherein input is output single-particle pulse signal to be measured; The high level width is 150ps, and reset is a reset signal, out1; Out2, out3, out4 are respectively the output signal of first to fourth grade of circuit; In the course of the work, RS latchs at different levels at first reset under unified reset control signal; The initial output of Q end is 0, if input signal overturns afterwards, and keeps the long enough time (time is to guarantee to make that the time of overturning takes place in latch output); Then can make the output signal of latch take place to overturn and keep, make output return to original state up to importing the set/reset signal again.
When pulse width is 150ps, can drive the two stage latch upset.
Repeat to change input pulse width, can make pulse width with the corresponding form of upset number, as shown in table 1, in view of the above can be according to actual latch upset situation, the anti-pulse width of surveying of releasing.
Table 1
The foregoing description is a preferred implementation of the present invention; But embodiment of the present invention is not restricted to the described embodiments; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (6)
1. single-particle transient pulse width measure circuit is characterized in that:
Comprise that single-particle pulse signal generating circuit (103) reaches one-level metering circuit at least;
Said single-particle pulse signal generating circuit (103) produces single-particle pulse signal to be measured;
Wherein, the bistable circuit (100) that is directly driven by single-particle pulse signal to be measured constitutes the first order of metering circuit; Begin from the second level of metering circuit, each grade circuit comprises delay circuit (101), logic gates (102) and bistable circuit (100) respectively;
Wherein in the circuit of the second level, the input signal of delay circuit (101) is a measured signal; The input signal of logic gates (102) is the output signal of this delay circuit (101) and the output signal of first order bistable circuit (100); The output signal of logic gates (102) is the input signal of bistable circuit at the corresponding levels (100);
Begin from tertiary circuit: the source of said delay circuits at different levels (101) input signal is the output signal of upper level logic gates (102); The input signal of said logic gates (102) is the output signal of delay circuit at the corresponding levels (101) and the output signal of upper level bistable circuit (100); The output signal of logic gates at the corresponding levels (102) is the input signal of bistable circuit at the corresponding levels (100).
2. single-particle transient pulse width measure circuit according to claim 1 is characterized in that:
Said bistable circuit (100) has two steady state (SS)s; Before single-particle pulse signal to be measured is measured; Output can be in a definite steady state (SS), when importing single-particle pulse signal to be measured and measure, as long as input signal upset takes place and keeps the sufficiently long time; Bistable circuit can be turned to another steady state (SS) from a steady state (SS), and output signal level changes.
3. single-particle transient pulse width measure circuit according to claim 1 is characterized in that:
When said delay circuit (101) input signal is a pulse signal; Output also is pulse signal; And the zero hour that output pulse signal changes, in the variation of output signals moment of higher level's bistable circuit (100), the variation of output signals that is later than higher level's bistable circuit (100) finish time that output pulse signal changes constantly in advance.
4. single-particle transient pulse width measure circuit according to claim 1 is characterized in that:
When said logic gates (102) all changed at the output signal of the output signal of delay circuit at the corresponding levels (101) and upper level bistable circuit (100), the output signal just changed.
5. single-particle transient pulse width measure circuit according to claim 1 is characterized in that:
The structure of the bistable circuits of selecting for use at different levels (100), delay circuit (101) and logic gates (102) is identical or different.
6. single-particle transient pulse width measure circuit according to claim 1 is characterized in that:
The output terminal of said bistable circuit (100) only has an output terminal to draw or draw simultaneously two complementary output ends;
When bistable circuit had only an output terminal to draw, this end is metering circuit input end of output terminal (out end) and next stage logic gates (102) as a result simultaneously;
When bistable circuit has two complementary output ends to draw, with two output terminals respectively as the metering circuit input end of output terminal (out end) and next stage logic gates (102) as a result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110152231.0A CN102818939B (en) | 2011-06-08 | 2011-06-08 | Measuring circuit for single-event transient pulse width |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110152231.0A CN102818939B (en) | 2011-06-08 | 2011-06-08 | Measuring circuit for single-event transient pulse width |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102818939A true CN102818939A (en) | 2012-12-12 |
| CN102818939B CN102818939B (en) | 2014-12-03 |
Family
ID=47303174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110152231.0A Active CN102818939B (en) | 2011-06-08 | 2011-06-08 | Measuring circuit for single-event transient pulse width |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102818939B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104678188A (en) * | 2014-12-22 | 2015-06-03 | 中国科学院微电子研究所 | Single-particle transient pulse width measurement circuit |
| CN104808073A (en) * | 2015-04-20 | 2015-07-29 | 中国科学院微电子研究所 | Circuit for measuring width of single-particle transient pulse |
| CN103983834B (en) * | 2014-05-16 | 2017-01-04 | 中国科学院微电子研究所 | A kind of single-particle transient amplitude measurement circuitry |
| CN106443202A (en) * | 2016-08-31 | 2017-02-22 | 西北核技术研究所 | On-chip self-triggering single event transient pulse width measurement method and system |
| CN106569040A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569041A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single-particle transient pulse width measurement circuit, integrated circuit and electronic apparatus |
| CN106774775A (en) * | 2017-02-22 | 2017-05-31 | 许继集团有限公司 | It is a kind of to prevent the opening into trip method and system of single-particle inversion misoperation |
| CN104808073B (en) * | 2015-04-20 | 2018-02-09 | 中国科学院微电子研究所 | Single event transient pulse width measure circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811929A (en) * | 2016-03-09 | 2016-07-27 | 中国人民解放军国防科学技术大学 | Low-area overhead anti-single event transient delay unit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080183409A1 (en) * | 2007-01-31 | 2008-07-31 | Mcgill University | Embedded time domain analyzer for high speed circuits |
| CN101499788A (en) * | 2009-02-19 | 2009-08-05 | 上海交通大学 | Single particle upset and single particle transient pulse resisiting D trigger |
| CN101551421A (en) * | 2009-02-27 | 2009-10-07 | 北京时代民芯科技有限公司 | A structure of SET collecting and detecting circuit |
| CN101964005A (en) * | 2009-07-22 | 2011-02-02 | 中国科学院微电子研究所 | Modeling method of CMOS circuit single-ion transient state |
-
2011
- 2011-06-08 CN CN201110152231.0A patent/CN102818939B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080183409A1 (en) * | 2007-01-31 | 2008-07-31 | Mcgill University | Embedded time domain analyzer for high speed circuits |
| CN101499788A (en) * | 2009-02-19 | 2009-08-05 | 上海交通大学 | Single particle upset and single particle transient pulse resisiting D trigger |
| CN101551421A (en) * | 2009-02-27 | 2009-10-07 | 北京时代民芯科技有限公司 | A structure of SET collecting and detecting circuit |
| CN101964005A (en) * | 2009-07-22 | 2011-02-02 | 中国科学院微电子研究所 | Modeling method of CMOS circuit single-ion transient state |
Non-Patent Citations (1)
| Title |
|---|
| P. EATON ETAL: "Single Event Transient Pulsewidth Measurements Using a Variable Temporal Latch Technique", 《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103983834B (en) * | 2014-05-16 | 2017-01-04 | 中国科学院微电子研究所 | A kind of single-particle transient amplitude measurement circuitry |
| CN104678188A (en) * | 2014-12-22 | 2015-06-03 | 中国科学院微电子研究所 | Single-particle transient pulse width measurement circuit |
| CN104678188B (en) * | 2014-12-22 | 2017-12-12 | 中国科学院微电子研究所 | Single event transient pulse width measure circuit |
| CN104808073A (en) * | 2015-04-20 | 2015-07-29 | 中国科学院微电子研究所 | Circuit for measuring width of single-particle transient pulse |
| CN104808073B (en) * | 2015-04-20 | 2018-02-09 | 中国科学院微电子研究所 | Single event transient pulse width measure circuit |
| CN106443202A (en) * | 2016-08-31 | 2017-02-22 | 西北核技术研究所 | On-chip self-triggering single event transient pulse width measurement method and system |
| CN106443202B (en) * | 2016-08-31 | 2018-11-23 | 西北核技术研究所 | A kind of on piece is from triggering single event transient pulse method for measuring width and system |
| CN106569040A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569041A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single-particle transient pulse width measurement circuit, integrated circuit and electronic apparatus |
| CN106569040B (en) * | 2016-10-31 | 2019-07-26 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569041B (en) * | 2016-10-31 | 2019-07-26 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106774775A (en) * | 2017-02-22 | 2017-05-31 | 许继集团有限公司 | It is a kind of to prevent the opening into trip method and system of single-particle inversion misoperation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102818939B (en) | 2014-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102818939B (en) | Measuring circuit for single-event transient pulse width | |
| CN102621401B (en) | Circuit for measuring width of single-particle transient pulse | |
| Eaton et al. | Single event transient pulsewidth measurements using a variable temporal latch technique | |
| CN103063933B (en) | Single-particle pulse width measurement circuit | |
| CN104678188A (en) | Single-particle transient pulse width measurement circuit | |
| CN104461808B (en) | A kind of FPGA single particle soft error impact evaluation method by mistake | |
| CN101499788A (en) | Single particle upset and single particle transient pulse resisiting D trigger | |
| US10644683B2 (en) | Clock driving circuit resistant to single-event transient | |
| DE60319104T2 (en) | METERING CIRCUIT FOR COUNTER-COUNTER-GENERATION | |
| Cha et al. | A fast and accurate gate-level transient fault simulation environment | |
| Devarapalli et al. | SEU-hardened dual data rate flip-flop using C-elements | |
| US10585143B2 (en) | Flip flop of a digital electronic chip | |
| CN106569040B (en) | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment | |
| CN109361387B (en) | Low-cost triple-modular redundancy latch | |
| Berg et al. | An analysis of single event upset dependencies on high frequency and architectural implementations within actel RTAX-S family field programmable gate arrays | |
| CN113723045A (en) | Design method of digital integrated circuit | |
| CN103812472A (en) | Trigger resistant to single event transient effect | |
| CN104502750B (en) | Trigger unit single event upset effect experimental verification circuit | |
| CN104541330A (en) | System and method to perform scan testing using a pulse latch with a blocking gate | |
| CN106569042B (en) | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment | |
| Agustin et al. | Efficient mitigation of SET induced harmonic errors in ring oscillators | |
| CN106998198B (en) | Self-adaptive trigger reinforcing circuit | |
| CN106569041B (en) | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment | |
| Singh et al. | A low power 8× 2 7-1 PRBS generator using Exclusive-OR gate merged D flip-flops | |
| CN205566246U (en) | Circuit is consolidated to adaptive trigger |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170717 Address after: 100029 Beijing city Chaoyang District Beitucheng West Road No. 11 building 4 layer Institute of Microelectronics Patentee after: Beijing Zhongke Newmicrot Technology Development Co., Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Institute of Microelectronics Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right |