CN104808073A - Circuit for measuring width of single-particle transient pulse - Google Patents
Circuit for measuring width of single-particle transient pulse Download PDFInfo
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- CN104808073A CN104808073A CN201510188826.XA CN201510188826A CN104808073A CN 104808073 A CN104808073 A CN 104808073A CN 201510188826 A CN201510188826 A CN 201510188826A CN 104808073 A CN104808073 A CN 104808073A
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Abstract
The invention discloses a circuit for measuring width of a single-particle transient pulse. The circuit includes a control signal generation circuit and at least one grade of dual-delay comparison circuit, wherein the control signal generation circuit is provided with a reset input end, a single-particle pulse receiving end, a pulse start output end and a pulse end output end; each grade of dual-delay comparison circuit is provided with a reset input end, a first delay input end, a second delay input end, a first delay output end, a second delay output end and a comparison output end. The first delay input end in the first grade is connected with the pulse start output end while the second delay input end is connected with the pulse end output end, and from the second grade, the first delay input end in each grade is connected with the first delay output end of the previous grade while the second delay input end is connected with the second delay output end of the previous grade. The measuring circuit realized according to the invention can measure the high level pulse width of single-particle transient pulse, and is wide in measurement range and high in measurement accuracy.
Description
Technical field
The present invention relates to electric pulse width measurement technical field, particularly a kind of high-level pulse width metering circuit of single-particle transient.
Background technology
Along with improving constantly of aerospace electron device integration, space radiation has become the key factor affecting spacecraft reliability and operation life.Radiation is mainly divided into two large classes to the impact of integrated circuit: single particle effect and total dose effect.Total dose effect is that integrated circuit is in radiation environment for a long time, and radiation effect accumulates the effect produced; Single particle effect is after emittance particle enters integrated circuit, the effect that radiation effect instant effect produces.Wherein single particle effect can be subdivided into three classes:
1, single-particle soft error effects: comprise Single event upset effecf, single-event transients effect, single-particle many upsets effect etc., produce interference to circuit node at short notice.
2, there is the effect of potentially danger: as single event latch-up effect, if do not controlled, chip generation single event burnout may be caused.
3, single hard error effect, as displacement damage etc., can make the transistor in chip thoroughly can not work.
Wherein, single-event transients effect is the common principal element affecting chip performance, when chip is placed in radiation environment, ambient energy particle can be injected into chip internal, on the movement locus of energy particle, electronics, the hole pair of some is produced by ionising radiation, these electronics, hole are to being absorbed by circuit node under the effect of electric field, concept transfer level, if there is no backfeed loop, so after the time of single-particle effect terminates, this node level can recover back again original value, thus produces a pulse signal in circuit.
In order to further investigate genesis mechanism, the rule of single particle effect, measure the radiosensitive parameter of various spaceborne electronic devices and components and integrated circuit, evaluate level and the failure risk of its anti-single particle effect, for parts selection and radiation hardening measure provide foundation, need to build effective measurement environment, Measurement accuracy is carried out to features such as transient pulse signal width.Wherein measurement environment often selects ground irradiation experiment, produces cosmic-ray particle carry out bombardment test to chip to be measured, cosmic space that is virtually reality like reality radiation environment by simulation.When pulse signals width is measured, according to differences such as incident particle kind, energy, the single-particle pulse signal level of generation is held time also different, pulse width can from tens psecs to 1,000 psecs more than.If adopt the checkout equipments such as traditional oscillograph or logic analyser to measure single event transient pulse width, require that the frequency of measuring equipment must be very high, such high-frequency apparatus is often domestic can not be produced, and abroad also forbids exporting, it is very high that this makes to measure cost, realizes difficulty large.If adopt on-chip circuit to measure, existing pulse width measuring method is measured often through outside input high-frequency signal pulse signals sampling, therefore acquisition accuracy is subject to frequency and the waveform influence of sampled signal, also be difficult in actual measurement provide very high frequency, the sampled signal that wave characteristics is very excellent again, make circuit to survey scope little, measuring accuracy is low.
Summary of the invention
The invention provides a kind of single event transient pulse width measure circuit, by changing circuit progression, circuit measuring scope can be changed, by changing the difference of the delay of two delay circuits in two delay comparison circuit, measuring accuracy can be regulated.
According to one embodiment of present invention, single event transient pulse width measure circuit comprises:
Control signal produces circuit, has reset signal input end, single-particle reception of impulse end, start-of-pulsing signal output terminal and end-of-pulsing signal output terminal.Wherein single-particle reception of impulse end connects 010 type single-particle pulse signal to be measured.
At least one-level dual-delay comparator circuit, every grade of dual-delay comparator circuit has the RESET input, the first time delay input end, the second time delay input end, the first time delay output terminal, the second time delay output terminal and compare output terminal.First time delay input end connection control signal of first order dual-delay comparator circuit produces the start-of-pulsing signal output terminal of circuit, and the second time delay input end connection control signal produces the pulse signal ends output terminal of circuit.From the dual-delay comparator circuit of the second level, the first time delay input end of every grade of dual-delay comparator circuit connects the first time delay output terminal of upper level dual-delay comparator circuit, and the second time delay input end connects the second time delay output terminal of upper level dual-delay comparator circuit.
Control signal produces circuit and is all connected reset signal with the RESET input of dual-delay comparator circuit at different levels, and control signal produces the comparison output terminal out2/ of start-of-pulsing signal output terminal out1 with dual-delay comparator circuit at different levels of circuit ... / out3 forms the output signal of single-particle pulse width measurement circuit jointly.Can according to out1 in actual measurement ..., the output level of outn is counter releases single-particle signal pulse width to be measured.
Adopt the single-particle pulse width measurement circuit that the present invention realizes, its measuring principle is as follows:
Circuit generates pulses commencing signal out1 is produced, end-of-pulsing signal end by control signal.When measuring beginning, reset signal reset is high level, and make out1 be low level, end is high level, out2 ..., outn is low level; When single-particle pulse signal input to be measured becomes high level from low level, out1 signal will be made to become high level from low level, end signal keeps high level constant.Then when input becomes low level from high level, out1 signal high level remains unchanged, and end signal becomes low level from high level; It can thus be appreciated that end signal to become from high level the moment that the low level moment becomes high level than out1 signal from low level late, this mistiming (namely end signal is the time of high level with out1 signal) approximates input pulse width.And at different levels pairs of delay comparison circuits, postponed step by step by delay circuit 1 pair of out1 signal, postponed step by step by delay circuit 2 pairs of end signals, due in circuit design process, require when input signal is identical, the time delay of delay circuit 2 must be greater than the time delay of delay circuit 1, therefore the two delay comparison circuit of one-level is often added, the time that this grade first delay output terminal is high level time with the second delay output terminal is high level than this grade first delay input end with the second delay input end is short, and short numerical value approximates t1-t2.
It can thus be appreciated that, for the single-particle pulse signal of fixed width, after the two delay circuit of some levels, the time that first delay output terminal is high level with the second delay output terminal will be zero, though or be on the occasion of, but this value too small (time being all high level is too short), thus be not enough to driving three input rejection gate RS latch upset.In summary, single-particle pulse signal pulse width to be measured is wider, and the latch count that can overturn is more, i.e. out1 ..., in outn, the number of high level is more.Therefore can according to out1 ..., the output situation of outn is counter releases single-particle pulse width to be measured.
Adopt its measuring accuracy of this method to approximate the difference of delay circuit 1 with the delay ability of delay circuit 2, namely deduct the time delay of delay circuit 2 time delay of delay circuit 1.But from actual use angle, for reducing the impact of other factors, improve measuring accuracy, preferably prior according to simulation scenarios or the test case applying Other Instruments, list out1, outn exports situation with the corresponding form of input pulse width scope, when actual measurement, exports situation according to reality, find this kind of corresponding input pulse width scope of output situation in this form, realize the object measured.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
The single event transient pulse width measure electrical block diagram that Fig. 1 provides for one embodiment of the present of invention;
The control signal that Fig. 2 provides for one embodiment of the present of invention produces electrical block diagram;
The three input rejection gate RS latch structure schematic diagram that Fig. 3 provides for one embodiment of the present of invention;
The control signal generation circuit working waveform schematic diagram that Fig. 4 provides for one embodiment of the present of invention;
The structural representation of the time delay comparator circuit that Fig. 5 provides for one embodiment of the present of invention;
The work wave schematic diagram of the time delay comparator circuit that Fig. 6 provides for one embodiment of the present of invention;
The overall work waveform schematic diagram of the single event transient pulse width measure circuit measuring single event transient pulse that Fig. 7 provides for one embodiment of the present of invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
Figure 1 shows that the single event transient pulse width measure electrical block diagram that one embodiment of the present of invention provide, comprise control signal and produce circuit 101 and at least one-level time delay comparator circuit 102.The comparator circuit of time delay shown in Fig. 1 102 has n level (such as, can be made up of 8 grades of circuit).Hereinafter when measuring the single-particle pulse signal of specific width scope, adopting 8 grades of time delay comparator circuits, certainly according to measurement needs, being not limited thereto.
Adopt one embodiment of the present of invention, its control signal produces circuit (101), there is reset signal input end, single-particle reception of impulse end, start-of-pulsing signal output terminal (out1) and end-of-pulsing signal output terminal (end).Wherein single-particle reception of impulse end connects 010 type single-particle pulse signal (input) to be measured.
Adopt one embodiment of the present of invention, it has 8 grades of dual-delay comparator circuits (102), every grade of dual-delay comparator circuit (102) has the RESET input, the first time delay input end, the second time delay input end, the first time delay output terminal, the second time delay output terminal and compare output terminal (out2/ ... / outn).First time delay input end connection control signal of first order dual-delay comparator circuit produces the start-of-pulsing signal output terminal (out1) of circuit (101), and the second time delay input end connection control signal produces the pulse signal ends output terminal (end) of circuit (101).From the dual-delay comparator circuit of the second level, the first time delay input end of every grade of dual-delay comparator circuit connects the first time delay output terminal of upper level dual-delay comparator circuit, and the second time delay input end connects the second time delay output terminal of upper level dual-delay comparator circuit.
Control signal produces circuit and is all connected reset signal (reset) with the RESET input of dual-delay comparator circuit at different levels, and control signal produces the comparison output terminal (out2/ of start-of-pulsing signal (out1) with dual-delay comparator circuit at different levels of circuit ... / out3) the common output signal forming single-particle pulse width measurement circuit.According to out1/ in actual measurement ... the output level of/outn is counter releases single-particle signal pulse width to be measured.
In the present embodiment, the control signal devised as shown in Figure 2 produces circuit, and comprise the basic RS latch 201 of rejection gate, phase inverter 202, band inputs RS latch 203 with three of door function.
Wherein three input rejection gate RS latchs comprise R input end, S1 input end and S2 input end and Q output terminal and
output terminal.Reset signal (reset) connects the R input end of the basic RS latch of rejection gate and the R input end of three input rejection gate RS latchs.010 type single-particle pulse signal (input) to be measured connects the S input end of the basic RS latch of rejection gate, the Q output terminal of the basic RS latch of rejection gate is the start-of-pulsing signal output terminal (out1) that control signal produces circuit, Q output terminal connects the S1 input end of three input rejection gate RS latchs simultaneously, input connects the input end of reverser simultaneously, the output terminal of reverser connects the S2 input end of three input rejection gate RS latchs, three input rejection gate RS latchs
output terminal is the end-of-pulsing signal output terminal (end) that control signal produces circuit.
In an embodiment of the present invention, as shown in Figure 3, this circuit is made up of cmos circuit the circuit structure of three input rejection gate RS latchs 203 used, and its S1 input end is interchangeable with S2 input end.Wherein 301,302,305,306,307 is PMOS, and substrate all connects power supply, and PMOS width/length is 2.3 microns/0.18 micron; 303,304,308,309,310 is NMOS tube, and the equal ground connection of substrate, NMOS tube width/length is 0.89 micron/0.18 micron.
Wherein 301 grid terminations three input rejection gate RS latch R input end, 301 source termination powers, and drain terminal connects 302 sources; 302 grid terminations three input rejection gate RS latch
output terminal, drain terminal connects three input rejection gate RS latch Q output terminals; The source of 303 and 304 all connects three input rejection gate RS latch Q output terminals, grid end connect respectively R input end and
output terminal, the equal ground connection of drain terminal; The source of 305 and 306 all connects power supply, and grid end connects three input rejection gate RS latch S1 input end and S2 input ends respectively, and drain terminal all connects 307 sources; 307 grid termination Q output terminals, drain terminal connects
output terminal; 308 drain terminals connect Q output terminal, grid termination Q output terminal, source ground connection; 309 drain terminals connect
output terminal, grid termination S1 input end, source connects 310 drain terminals; 310 grid termination S2 input ends, source ground connection.
The basic RS latch of three input rejection gates, when R end is high level, when S1 and S2 end is not high level entirely, Q holds output low level,
end exports high level; When R end is for low level, when S1 and S2 is high level, Q end exports high level,
end output low level; When R end is for low level, and when S1 and S2 be high level entirely, Q end with
end output remains unchanged.
Control signal produces circuit working waveform schematic diagram as shown in Figure 4, finds out that waveform changes, single-particle pulse signal input pulse width to be measured is set to 5 nanoseconds (actual single-particle pulse signal was often no more than for 1 nanosecond) herein for ease of clear.When a measurement is started, during 2 nanosecond, reset signal reset becomes high level, and single-particle pulse to be measured is low level, now RS latch reset, and start-of-pulsing signal out1 is low level, and end-of-pulsing signal end is high level; During 6 nanosecond, reset signal becomes low level, and now single-particle pulse signal to be measured is also low level, and start-of-pulsing signal keeps low level, and end-of-pulsing signal keeps high level; During 10 nanosecond, when single-particle pulse signal to be measured becomes high level from low level, start-of-pulsing signal becomes as high level from low level, and end-of-pulsing signal keeps high level constant; When 15 nanosecond, when single-particle pulse signal to be measured reverts to low level by high level, start-of-pulsing signal keeps high level, and end-of-pulsing signal becomes low level from high level.
In the present embodiment, time delay comparator circuit at different levels all adopts identical circuit structure size, and as shown in Figure 5, wherein 401,402,403,404 is phase inverter, and 203 is three input rejection gate RS latchs.The input end of 401 connects first of two delay comparison circuit and postpones input end (b_in_1), and the output terminal of 401 connects the input end of 402, and the output terminal of 402 is first of two delay comparison circuit and postpones output terminal (b_out_1); The input end of 403 connects second of two delay comparison circuit and postpones input end (b_in_2), and the output terminal of 403 connects the input end of 404, and the output terminal of 404 is second of two delay comparison circuit and postpones output terminal (b_out_2); 402 with 404 output terminal be connected S1 input end and the S2 input end of three input rejection gate RS latchs 203 respectively, the R input end of 203 connects the RESET input (reset) of two delay comparison circuit, and the Q output terminal of 203 connects the comparison output terminal (out) of two delay comparison circuit (as out2/out3/ ... / outn); In 401, PMOS width/length is 6.9 microns/0.18 micron, and NMOS tube width/length is 2.67 microns/0.18 micron.402,403, in 404, PMOS width/length is 2.3 microns/0.18 micron, and NMOS tube width/length is 0.89 micron/0.18 micron.Namely 401 and 402 form the first delay circuits, and 403 and 404 form the second delay circuits, due to PMOS in 401 and NMOS tube width and length comparatively large, known by emulating, be greater than the time delay of the second delay circuit the time delay of the first delay circuit.
In the present embodiment, time delay comparator circuit work wave schematic diagram as shown in Figure 6, be followed successively by the output signal b_out_2 of the second time delay output terminal from top to bottom, the input signal b_in_2 of the second time delay input end, the output signal b_out_1 of the first time delay output terminal, the input signal b_in_1 of the first time delay input end, reset signal reset, the voltage waveform of the output signal out of upset output terminal.Composition graphs 5 is known, and when emulating 2 nanosecond of moment, reset signal becomes high level, and b_in_1 signal is low level, and b_in_2 signal is high level, and now 203 reset, and out signal is low level.When 5.64 nanosecond, b_in_1 signal becomes high level from low level, when 5.76 nanosecond (after 5.76-5.64=0.12 nanosecond), b_out_1 signal becomes high level, when 5.77 nanosecond, b_in_2 signal becomes low level from high level, when 5.87 nanosecond (after 0.1 nanosecond), b_out_2 signal becomes low level, namely b_out_2 signal delay time (5.87-5.77=0.1 nanosecond) is greater than the time delay (5.76-5.64=0.12 nanosecond) of b_out_1 signal, in this course, the time that b_out_1 signal and b_out_2 signal are all high level is about (5.87-5.76)=0.11 nanosecond, 503 upsets can be driven, out signal is made to become high level.Every grade of measuring accuracy approximates 0.12-0.1=0.02 nanosecond.
Delay time due to b_out_1 signal is longer than the delay time of b_out_2 signal, therefore the time making output b_out_1 signal at different levels be high level with b_out_2 signal successively decreases step by step, for the single-particle pulse signal of fixed width, after the two delay circuit of some levels, the time that first delay output terminal is high level with the second delay output terminal will be zero, though or be on the occasion of, but this value too small (time being all high level is too short), thus be not enough to driving three input rejection gate RS latch upset.As long as therefore the number of time delay comparator circuit is abundant, single-particle pulse to be measured just can only drive limited time delay comparator circuit upset.And single-particle pulsewidth is wider, drives the time delay comparator circuit number of upset more, therefore can push away single-particle pulsewidth to be measured according to the output level of output terminal at different levels is counter.
In actual application, according to the feature of single-particle pulsewidth to be measured, can increase or reduce size or the progression of impact damper at different levels, regulate the difference of the delay time of delay circuit 1 and delay circuit 2, control the measuring accuracy of every grade.Also by increasing the progression of dual-delay comparator circuit, test specification can be expanded.
Be illustrated in figure 7 the overall work waveform signal of a single event transient pulse width measure circuit measuring single event transient pulse in the present embodiment, be followed successively by time delay comparator circuit at different levels upset output terminal output signal out9/ from top to bottom ... / out1, end-of-pulsing signal end, the voltage waveform of single-particle pulse signal input and reset signal reset.Wherein out2/ ... / out9, be respectively the 1st to the 8th grade of time delay comparator circuit upset output terminal output signal.In the present embodiment, supply voltage is 1.8V, and input signal high-level pulse width to be measured is 240ps.
During emulation 2 nanosecond of moment, reset signal becomes 1 (0 represents low level, and 1 represents high level), and control signal produces circuit and time delay comparator circuit at different levels resets, and end signal is 1, and output signal out1 to out9 is 0.During emulation 4 nanosecond of moment, reset signal becomes 0, measures and starts.During emulation 5 nanosecond of moment, input signal produces the high level pulse that a pulse width was 0.24 nanosecond, the time being high level with d_out_2 due to d_out_1 shortens step by step, therefore as shown by the simulation results, when being input as 240ps, out2/ can be driven ... / out5 overturns, and out6/ ... / out9 cannot overturn.
As can be seen from above-mentioned measuring process, input pulse width is wider, and the time delay comparator circuit number of upset can be driven more.When design circuit, by repeating to change input pulse width, pulse width can be obtained and overturns the corresponding form of number with time delay comparator circuit, as shown in the table, wherein 0 represents output low level, namely exports and does not overturn, 1 represents output high level, namely exports and overturns.Situation can be exported according to actual time delay comparator circuit output terminal accordingly, anti-release survey the scope of pulse width.
In side circuit design process, can according to measurement range and measuring accuracy requirement, by attempting different circuit sizes and circuit progression makes the output switching activity situation of time delay comparator circuit at different levels more meet designing requirement with the corresponding relation between pulse width.
Above-described embodiment is the present invention's preferably embodiment; but embodiments of the present invention are not restricted to the described embodiments; change, the modification done under other any does not deviate from Spirit Essence of the present invention and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (4)
1. a single event transient pulse width measure circuit, comprising:
Control signal produces circuit (101), has reset signal input end, single-particle reception of impulse end, start-of-pulsing signal output terminal (out1) and end-of-pulsing signal output terminal (end).Wherein single-particle reception of impulse end connects 010 type single-particle pulse signal (input) to be measured.
At least one-level dual-delay comparator circuit (102), every grade of dual-delay comparator circuit (102) has the RESET input, the first time delay input end, the second time delay input end, the first time delay output terminal, the second time delay output terminal and compare output terminal (out2/ ... / outn).First time delay input end connection control signal of first order dual-delay comparator circuit produces the start-of-pulsing signal output terminal (out1) of circuit (101), and the second time delay input end connection control signal produces the pulse signal ends output terminal (end) of circuit (101).From the dual-delay comparator circuit of the second level, the first time delay input end of every grade of dual-delay comparator circuit connects the first time delay output terminal of upper level dual-delay comparator circuit, and the second time delay input end connects the second time delay output terminal of upper level dual-delay comparator circuit.
Control signal produces circuit and is all connected reset signal (reset) with the RESET input of dual-delay comparator circuit at different levels, and control signal produces the comparison output terminal (out2/ of start-of-pulsing signal output terminal (out1) with dual-delay comparator circuit at different levels of circuit ... / out3) the common output signal forming single-particle pulse width measurement circuit.According to out1 in actual measurement ..., the output level of outn is counter releases single-particle signal pulse width to be measured.
2. single event transient pulse width measure circuit according to claim 1, wherein said control signal produces circuit (101) and comprises a basic RS latch of rejection gate, a reverser and one three input rejection gate RS latch.Wherein three input rejection gate RS latchs comprise R input end, S1 input end and S2 input end and Q output terminal and
output terminal.Reset signal (reset) connects the R input end of the basic RS latch of rejection gate and the R input end of three input rejection gate RS latchs.010 type single-particle pulse signal (input) to be measured connects the S input end of the basic RS latch of rejection gate, the Q output terminal of the basic RS latch of rejection gate is the start-of-pulsing signal output terminal (out1) that control signal produces circuit, Q output terminal connects the S1 input end of three input rejection gate RS latchs simultaneously, input connects the input end of reverser simultaneously, the output terminal of reverser connects the S2 input end of three input rejection gate RS latchs, three input rejection gate RS latchs
output terminal is the end-of-pulsing signal output terminal (end) that control signal produces circuit.
Single-particle pulse signal (input) to be measured is 010 type pulse signal, when a measurement is started, reset signal (reset) is high level, single-particle pulse to be measured is low level, now start-of-pulsing signal (out1) is low level, and end-of-pulsing signal (end) is high level; Then reset signal becomes low level, and now single-particle pulse signal to be measured is also low level, and start-of-pulsing signal keeps low level, and end-of-pulsing signal keeps high level.Afterwards when single-particle pulse signal to be measured becomes high level from low level, start-of-pulsing signal becomes as high level from low level, and end-of-pulsing signal keeps high level; When single-particle pulse signal to be measured reverts to low level by high level, start-of-pulsing signal keeps high level, and end-of-pulsing signal becomes low level from high level.
3. single event transient pulse width measure circuit according to claim 1, wherein said pair of delay comparison circuit comprises first delay circuit, second delay circuit and one three input rejection gate RS latch.Wherein the input end of the first delay circuit is the first time delay input end of two delay comparison circuit, and the output terminal of the first delay circuit is the first time delay output terminal of two delay comparison circuit.The input end of the second delay circuit is the second time delay input end of two delay comparison circuit, and the output terminal of the second delay circuit is the second time delay output terminal of two delay comparison circuit.First time delay output terminal connects the S1 input end of three input rejection gate RS latchs simultaneously, second delay output terminal connects the S2 input end of three input rejection gate RS latchs simultaneously, reset signal (reset) connects the R input end of three input rejection gate RS latchs, and the Q output terminal of three input rejection gate RS latchs is the comparison output terminal of two delay comparison circuit.
Wherein the first delay circuit and all available even number reverser of the second delay circuit are in series, but need both adjustments circuit size or circuit progression, must ensure that the delay ability of the first delay circuit is greater than the delay ability of the second delay circuit.Namely, when the input signal of the two is identical, the output signal of the first delay circuit is greater than the output signal time delay of the second delay circuit time delay.
4. single event transient pulse width measure circuit according to claim 1, in wherein said single-particle pulse width measurement circuit in the basic RS latch of three input rejection gate used, when R end is high level, when S1 and S2 end is not high level entirely, Q holds output low level
end exports high level; When R end is for low level, when S1 and S2 is high level, Q end exports high level,
end output low level; When R end is for low level, and when S1 and S2 be high level entirely, Q end with
end output remains unchanged.
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| CN201510188826.XA CN104808073B (en) | 2015-04-20 | Single event transient pulse width measure circuit |
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| CN201510188826.XA CN104808073B (en) | 2015-04-20 | Single event transient pulse width measure circuit |
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| CN106569040A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569041A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single-particle transient pulse width measurement circuit, integrated circuit and electronic apparatus |
| CN106569042A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single-particle transient pulse width measuring circuit, integrated circuit and electronic equipment |
| CN106569041B (en) * | 2016-10-31 | 2019-07-26 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569040B (en) * | 2016-10-31 | 2019-07-26 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569042B (en) * | 2016-10-31 | 2019-07-26 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
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