CN104808073A - Single-particle transient pulse width measuring circuit - Google Patents

Abstract

The invention discloses a single-event transient pulse width measurement circuit, which includes a control signal generating circuit and at least one stage of double-delay comparison circuit; wherein the control signal generating circuit has a reset input end, a single-event pulse receiving end, and a pulse start output end and pulse end output terminals; each stage of double-delay comparison circuit has a reset input terminal, a first delay input terminal, a second delay input terminal, a first delay output terminal, a second delay output terminal and a comparison output terminal. In the first stage, the first delay input terminal is connected to the pulse start output terminal, and the second delay input terminal is connected to the pulse end output terminal. From the second stage, the first delay input terminal in each stage is connected to the first delay output terminal of the previous stage, The second delay input terminal is connected to the second delay output terminal of the upper stage. The measurement circuit realized by the invention can measure the high-level pulse width of the single particle transient pulse, has a large measurable range and high measurement precision.

Description

Single Event Transient Pulse Width Measurement Circuit

technical field

The invention relates to the technical field of electric pulse width measurement, in particular to a high-level pulse width measurement circuit of a single-event transient pulse signal.

Background technique

With the continuous improvement of the integration of aerospace electronic devices, space radiation has become an important factor affecting the reliability and operating life of spacecraft. The effects of radiation on integrated circuits fall into two main categories: single event effects and total dose effects. The total dose effect is the effect produced by the accumulation of radiation effects after the integrated circuit has been in the radiation environment for a long time; the single event effect is the effect produced by the immediate radiation effect after the radiation energy particles enter the integrated circuit. Single event effects can be subdivided into three categories:

1. Single event soft error effect: including single event flip effect, single event transient effect, single event multiple flip effect, etc., which will interfere with circuit nodes in a short time.

2. Potentially dangerous effects: such as single event latch-up effect, if not controlled, may lead to single event burning of the chip.

3. The single event hard error effect, such as displacement damage, will completely disable the transistors in the chip.

Among them, the single event transient effect is a common main factor affecting the performance of the chip. When the chip is placed in a radiation environment, the surrounding energy particles will be injected into the chip, and a certain number of electrons will be generated on the trajectory of the energy particles through ionizing radiation. Hole pairs, these electron and hole pairs will be absorbed by the circuit nodes under the action of the electric field, changing the node level, if there is no feedback loop, then when the time of single particle action ends, the node level will return to the original value, thus generating a pulse signal in the circuit.

In order to study the occurrence mechanism and law of single event effects in depth, measure the radiation sensitive parameters of various spaceborne electronic components and integrated circuits, evaluate their anti-single event effect level and failure risk, and provide support for device type selection and anti-radiation hardening measures Based on this, it is necessary to build an effective measurement environment to accurately measure characteristics such as the width of transient pulse signals. Among them, the measurement environment often chooses the ground irradiation experiment, and the bombardment test of the chip to be tested is performed by simulating cosmic ray particles to simulate the real space radiation environment. When measuring the width of the pulse signal, depending on the type and energy of the incident particle, the level maintenance time of the generated single-particle pulse signal is also different, and the pulse width can range from tens of picoseconds to more than a thousand picoseconds. If a traditional oscilloscope or logic analyzer is used to measure the transient pulse width of a single event, the frequency of the measurement equipment must be very high. Such high-frequency equipment is often not produced in China, and its output is prohibited abroad, which makes the measurement cost very high. , it is very difficult to realize. If the on-chip circuit is used for measurement, the existing pulse width measurement method often samples the pulse signal through an external input high-frequency signal, so the capture accuracy is affected by the frequency and waveform of the sampling signal, and it is difficult to provide extremely high frequency in actual measurement. , The waveform characteristics are very good sampling signals, which makes the circuit measurable range small and the measurement accuracy low.

Contents of the invention

The invention provides a single-event transient pulse width measurement circuit, which can change the circuit measurement range by changing the circuit stages, and can adjust the measurement accuracy by changing the delay difference between two delay circuits in a double-delay comparison circuit.

According to an embodiment of the present invention, the single event transient pulse width measurement circuit includes:

The control signal generating circuit has a reset signal input terminal, a single event pulse receiving terminal, a pulse start signal output terminal and a pulse end signal output terminal. The single event pulse receiving end is connected to the 010 type single event pulse signal to be tested.

At least one stage of double-delay comparison circuit, each stage of double-delay comparison circuit has a reset input terminal, a first delay input terminal, a second delay input terminal, a first delay output terminal, a second delay output terminal and a comparison output. The first delay input terminal of the first-stage double-delay comparison circuit is connected to the pulse start signal output terminal of the control signal generation circuit, and the second delay input terminal is connected to the pulse signal end output terminal of the control signal generation circuit. Starting from the second-stage double-delay comparison circuit, the first delay input terminal of each double-delay comparison circuit is connected to the first delay output terminal of the upper-stage double-delay comparison circuit, and the second delay input terminal is connected to the The second delay output terminal of the first-stage double delay comparison circuit.

The control signal generation circuit and the reset input terminals of the double-delay comparison circuits at all levels are connected to the reset signal, and the pulse start signal output terminal out1 of the control signal generation circuit is in common with the comparison output terminals out2/.../out3 of the double-delay comparison circuits at all levels. Constitutes the output signal of the single event pulse width measurement circuit. In the actual measurement, the pulse width of the single event signal to be tested can be inversely deduced according to the output levels of out1, ..., outn.

Adopt the single event pulse width measuring circuit realized by the present invention, its measuring principle is as follows:

The pulse start signal out1 and the pulse end signal end are generated by the control signal generating circuit. At the beginning of the measurement, the reset signal reset is high level, so that out1 is low level, end is high level, out2,..., outn are low level; when the single event pulse signal input to be measured changes from low level to When the level is high, the out1 signal will change from low level to high level, and the end signal will remain high level. Then when the input changes from high level to low level, the high level of the out1 signal remains unchanged, and the end signal changes from high level to low level; it can be seen that the end signal changes from high level to low level The time is later than the time when the out1 signal changes from low level to high level, and the time difference (that is, the time when the end signal and the out1 signal are both high level) is approximately equal to the input pulse width. In the dual-delay comparison circuits at all levels, the out1 signal is delayed step by step through the delay circuit 1, and the end signal is delayed step by step through the delay circuit 2. Since the circuit design process requires that when the input signals are the same, the delay time of the delay circuit 1 must be greater than the delay time of the delay circuit 2, so each time a double-delay comparison circuit is added, the time when the first delay output terminal and the second delay output terminal of the stage are both high is higher than the first delay input terminal of the stage and the second delay input terminal The time that the delay input terminals are all high level is short, and the shortest value is approximately equal to t1-t2.

It can be seen that, for a single-event pulse signal with a fixed width, after several stages of double-delay circuits, the time when the first delay output terminal and the second delay output terminal are both high will be zero, or although it is a positive value, but This value is too small (the same high level time is too short), so that it is not enough to drive the three-input NOR gate RS latch to flip. It can be seen from the above that the wider the pulse width of the single event pulse signal to be tested, the more the number of latches that can be flipped, that is, the more the number of high levels in out1,..., outn. Therefore, the pulse width of the single event to be measured can be inversely deduced according to the output of out1, ..., outn.

Using this method, the test accuracy is approximately equal to the difference between the delay capabilities of the delay circuit 1 and the delay circuit 2, that is, the delay time of the delay circuit 1 minus the delay time of the delay circuit 2. But from the point of view of actual use, in order to reduce the influence of other factors and improve the measurement accuracy, it is best to list out1,..., outn output conditions corresponding to the input pulse width range according to the simulation situation or the test situation of other instruments in advance. In the actual measurement, according to the actual output situation, find the input pulse width range corresponding to the output situation in the table to achieve the purpose of measurement.

Description of drawings

Other characteristics, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

Fig. 1 is a schematic structural diagram of a single event transient pulse width measurement circuit provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a control signal generation circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a three-input NOR gate RS latch provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a working waveform of a control signal generating circuit provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a delay comparison circuit provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of working waveforms of a delay comparison circuit provided by an embodiment of the present invention;

FIG. 7 is a schematic diagram of the overall working waveform of a single event transient pulse measured by the single event transient pulse width measurement circuit provided by an embodiment of the present invention.

The same or similar reference numerals in the drawings represent the same or similar components.

Detailed ways

FIG. 1 is a schematic structural diagram of a single event transient pulse width measurement circuit provided by an embodiment of the present invention, including a control signal generation circuit 101 and at least one stage of delay comparison circuit 102 . It is shown in FIG. 1 that the delay comparison circuit 102 has n stages (for example, it may be composed of 8 stages). In the following, when measuring the single event pulse signal with a specific width range, an 8-stage delay comparison circuit is used, of course, according to the measurement requirements, it is not limited thereto.

According to an embodiment of the present invention, the control signal generating circuit (101) has a reset signal input terminal, a single event pulse receiving terminal, a pulse start signal output terminal (out1) and a pulse end signal output terminal (end). The single event pulse receiving end is connected to the 010 type single event pulse signal (input) to be tested.

Adopt an embodiment of the present invention, it has 8 stages of double time-delay comparison circuits (102), every stage of double-delay comparison circuits (102) has reset input terminals, the first time delay input end, the second time delay input end, The first delayed output terminal, the second delayed output terminal and the comparison output terminal (out2/.../outn). The first delay input terminal of the first stage double delay comparison circuit is connected to the pulse start signal output terminal (out1) of the control signal generation circuit (101), and the second delay input terminal is connected to the pulse signal of the control signal generation circuit (101). End the output terminal (end). Starting from the second-stage double-delay comparison circuit, the first delay input terminal of each double-delay comparison circuit is connected to the first delay output terminal of the upper-stage double-delay comparison circuit, and the second delay input terminal is connected to the The second delay output terminal of the first-stage double delay comparison circuit.

The control signal generation circuit and the reset input terminals of the double-delay comparison circuits at all levels are connected to the reset signal (reset), and the pulse start signal (out1) of the control signal generation circuit is the same as the comparison output terminals (out2/ .../out3) together constitute the output signal of the single event pulse width measurement circuit. In the actual measurement, the pulse width of the single event signal to be tested is deduced according to the output level of out1/.../outn.

In this embodiment, a control signal generation circuit as shown in FIG. 2 is designed, including a basic NOR gate RS latch 201, an inverter 202, and a three-input RS latch 203 with an AND gate function.

The three-input NOR gate RS latch includes R input, S1 input and S2 input, and Q output and output. The reset signal (reset) is connected to the R input terminal of the basic RS latch of the NOR gate and the R input terminal of the three-input NOR gate RS latch. The 010-type single-event pulse signal (input) to be tested is connected to the S input terminal of the basic RS latch of the NOR gate, and the Q output terminal of the basic RS latch of the NOR gate is the pulse start signal output terminal of the control signal generating circuit ( out1), the Q output terminal is connected to the S1 input terminal of the three-input NOR gate RS latch at the same time, the input is connected to the input terminal of the inverter at the same time, and the output terminal of the inverter is connected to the S2 of the three-input NOR gate RS latch Inputs of the three-input NOR gate RS latch The output terminal is the pulse end signal output terminal (end) of the control signal generating circuit.

In the embodiment of the present invention, the circuit structure of the used three-input NOR gate RS latch 203 is shown in FIG. 3 , the circuit is composed of a CMOS circuit, and its S1 input terminal is interchangeable with the S2 input terminal. Among them, 301, 302, 305, 306, and 307 are PMOS tubes, and the substrates are all connected to the power supply. The width/length of the PMOS tubes are both 2.3 microns/0.18 microns; 303, 304, 308, 309, and 310 are NMOS tubes, and the substrates are all grounded. , NMOS tube width/length are both 0.89 microns/0.18 microns.

Among them, the gate terminal of 301 is connected to the R input terminal of the three-input NOR gate RS latch, the source terminal of 301 is connected to the power supply, and the drain terminal is connected to the source terminal of 302; the gate terminal of 302 is connected to the three-input NOR gate RS latch The output terminal and the drain terminal are connected to the Q output terminal of the three-input NOR gate RS latch; the sources of 303 and 304 are connected to the Q output terminal of the three-input NOR gate RS latch, and the gate terminals are respectively connected to the R input terminal and Both the output terminal and the drain terminal are grounded; the source terminals of 305 and 306 are connected to the power supply, the gate terminal is respectively connected to the three-input NOR gate RS latch S1 input terminal and the S2 input terminal, and the drain terminal is connected to the 307 source terminal; 307 grid terminal Connect to Q output terminal, drain terminal Output terminal; 308 drain terminal is connected to Q output terminal, gate terminal is connected to Q output terminal, source terminal is grounded; 309 drain terminal is connected The output terminal, the gate terminal is connected to the S1 input terminal, the source terminal is connected to the drain terminal of 310; the gate terminal of 310 is connected to the S2 input terminal, and the source terminal is grounded.

The basic RS latch of the three-input NOR gate, when the R terminal is high, and the S1 and S2 terminals are not all high, the Q terminal outputs a low level, Terminal output high level; when R terminal is low level, when both S1 and S2 are high level, Q terminal output high level, terminal output low level; when R terminal is low level, and S1 and S2 are not all high level, Q terminal and The terminal output remains unchanged.

The schematic diagram of the working waveform of the control signal generation circuit is shown in Figure 4. In order to clearly see the waveform changes, the input pulse width of the single event pulse signal to be tested is set to 5 nanoseconds here (the actual single event pulse signal is often not more than 1 nanosecond ). When the measurement starts, at 2 nanoseconds, the reset signal reset becomes high level, the single event pulse to be tested is low level, at this time the RS latch is reset, the pulse start signal out1 is low level, and the pulse end signal end is high level; the reset signal becomes low level at 6 nanoseconds, at this time the single event pulse signal to be tested is also low level, the pulse start signal remains low level, and the pulse end signal remains high level; 10 nanoseconds , when the single event pulse signal to be tested changes from low level to high level, the pulse start signal changes from low level to high level, and the pulse end signal remains high level; when it is 15 nanoseconds, the When the single event pulse signal is restored from high level to low level, the pulse start signal remains high level, and the pulse end signal changes from high level to low level.

In this embodiment, the delay comparison circuits at all levels adopt the same circuit structure size, as shown in Figure 5, wherein 401, 402, 403, 404 are inverters, and 203 is a three-input NOR gate RS latch . The input end of 401 is connected to the first delay input end (b_in_1) of the double delay comparison circuit, the output end of 401 is connected to the input end of 402, and the output end of 402 is the first delay output end (b_out_1) of the double delay comparison circuit; 403 The input end of 403 is connected to the second delay input end (b_in_2) of the double delay comparison circuit, the output end of 403 is connected to the input end of 404, and the output end of 404 is the second delay output end (b_out_2) of the double delay comparison circuit; 402 and The output terminal of 404 is respectively connected to the S1 input terminal and the S2 input terminal of the three-input NOR gate RS latch 203, the R input terminal of 203 is connected to the reset input terminal (reset) of the double-delay comparison circuit, and the Q output terminal of 203 is connected to the dual delay comparison circuit. The comparison output terminal (out) of the delay comparison circuit (such as out2/out3/.../outn); the PMOS tube width/length in 401 is 6.9 microns/0.18 microns, and the NMOS tube width/length is 2.67 microns/0.18 microns. In 402, 403, and 404, the width/length of the PMOS tubes are both 2.3 microns/0.18 microns, and the width/length of the NMOS tubes are both 0.89 microns/0.18 microns. That is, 401 and 402 constitute the first delay circuit, and 403 and 404 constitute the second delay circuit. Since the width and length of the PMOS transistor and the NMOS transistor in 401 are relatively large, it can be known through simulation that the delay time of the first delay circuit is longer than that of the second delay circuit. delay.

In this embodiment, the schematic diagram of the working waveform of the delay comparison circuit is shown in Figure 6. From top to bottom, it is the output signal b_out_2 of the second delay output terminal, the input signal b_in_2 of the second delay input terminal, and the first delay output signal b_in_2. The output signal b_out_1 of the terminal, the input signal b_in_1 of the first delay input terminal, the reset signal reset, and the voltage waveform of the output signal out of the output terminal are reversed. Combining with Figure 5, it can be seen that at the simulation time of 2 nanoseconds, the reset signal becomes high level, the b_in_1 signal is low level, and the b_in_2 signal is high level, at this time 203 is reset, and the out signal is low level. At 5.64 nanoseconds, the b_in_1 signal changes from low level to high level, at 5.76 nanoseconds (5.76-5.64=0.12 nanoseconds later), the b_out_1 signal becomes high level, and at 5.77 nanoseconds, the b_in_2 signal From high level to low level, at 5.87 nanoseconds (after 0.1 nanoseconds), the b_out_2 signal becomes low level, that is, the delay time of the b_out_1 signal (5.76-5.64=0.12 nanoseconds) is greater than the b_out_2 signal delay Time (5.87-5.77=0.1 nanoseconds), in this process, the b_out_1 signal and the b_out_2 signal are at the same high level time is about (5.87-5.76)=0.11 nanoseconds, which can drive 503 to flip, so that the out signal becomes is high level. Each level of test accuracy is approximately equal to 0.12-0.1=0.02 nanoseconds.

Since the delay time of the b_out_1 signal is longer than the delay time of the b_out_2 signal, the time at which the b_out_1 signal and the b_out_2 signal are both high at all levels is gradually reduced. For a fixed-width single-event pulse signal, after several stages of double delay After the circuit, the time when the first delay output terminal and the second delay output terminal are both high level will be zero, or although it is a positive value, the value is too small (the time for the same high level is too short), so that it is not enough To drive the three-input NOR gate RS latch to flip. Therefore, as long as the number of delay comparison circuits is large enough, the single event pulse to be tested can only drive a limited number of delay comparison circuits to flip. And the wider the pulse width of the single event, the more the number of delay comparison circuits for driving the reversal, so the pulse width of the single event to be measured can be inversely deduced according to the output levels of the output terminals of each level.

In the actual application process, according to the characteristics of the pulse width of the single event to be measured, the size or number of stages of the buffers at each level can be increased or decreased, the delay time difference between the delay circuit 1 and the delay circuit 2 can be adjusted, and the delay time of each stage can be controlled. measurement accuracy. It is also possible to expand the test range by increasing the number of stages of the double-delay comparison circuit.

As shown in Figure 7, it is a schematic diagram of the overall working waveform of a single-event transient pulse measured by the single-event transient pulse width measurement circuit in this embodiment. From top to bottom, the output signals out9/ …/out1, voltage waveforms of pulse end signal end, single event pulse signal input and reset signal reset. Wherein out2/.../out9 are the output signals of the inversion output terminals of the first to eighth stage delay comparison circuits respectively. In this embodiment, the power supply voltage is 1.8V, and the high-level pulse width of the input signal to be tested is 240 ps.

When the simulation time is 2 nanoseconds, the reset signal becomes 1 (0 represents low level, 1 represents high level), the control signal generation circuit and the delay comparison circuits at all levels are reset, the end signal is 1, and the output signals out1 to out9 are 0. When the simulation time is 4 nanoseconds, the reset signal becomes 0, and the measurement starts. When the simulation time is 5 nanoseconds, the input signal generates a high-level pulse with a pulse width of 0.24 nanoseconds. Since the time when d_out_1 and d_out_2 are both high-level gradually becomes shorter, as shown in the simulation results, when the input is 240ps , it can drive out2/…/out5 to flip, but out6/…/out9 cannot flip.

It can be seen from the above measurement process that the wider the input pulse width, the more the number of delay comparison circuits that can be driven to flip. When designing the circuit, you can obtain the corresponding table of the pulse width and the number of inversions of the delay comparison circuit by repeatedly changing the input pulse width, as shown in the following table, where 0 means the output is low, that is, the output is not inverted, and 1 means the output is high Flat, that is, the output is flipped. Accordingly, the range of the measured pulse width can be inversely deduced according to the actual delay comparison circuit output condition.

In the actual circuit design process, according to the measurement range and measurement accuracy requirements, by trying different circuit sizes and circuit stages, the corresponding relationship between the output reversal of the delay comparison circuits at all levels and the pulse width can be more in line with the design requirements.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, Simplifications should be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (4)

1. a single event transient pulse width measure circuit, comprising:

Control signal produces circuit (101), has reset signal input end, single-particle reception of impulse end, start-of-pulsing signal output terminal (out1) and end-of-pulsing signal output terminal (end).Wherein single-particle reception of impulse end connects 010 type single-particle pulse signal (input) to be measured.

At least one-level dual-delay comparator circuit (102), every grade of dual-delay comparator circuit (102) has the RESET input, the first time delay input end, the second time delay input end, the first time delay output terminal, the second time delay output terminal and compare output terminal (out2/ ... / outn).First time delay input end connection control signal of first order dual-delay comparator circuit produces the start-of-pulsing signal output terminal (out1) of circuit (101), and the second time delay input end connection control signal produces the pulse signal ends output terminal (end) of circuit (101).From the dual-delay comparator circuit of the second level, the first time delay input end of every grade of dual-delay comparator circuit connects the first time delay output terminal of upper level dual-delay comparator circuit, and the second time delay input end connects the second time delay output terminal of upper level dual-delay comparator circuit.

Control signal produces circuit and is all connected reset signal (reset) with the RESET input of dual-delay comparator circuit at different levels, and control signal produces the comparison output terminal (out2/ of start-of-pulsing signal output terminal (out1) with dual-delay comparator circuit at different levels of circuit ... / out3) the common output signal forming single-particle pulse width measurement circuit.According to out1 in actual measurement ..., the output level of outn is counter releases single-particle signal pulse width to be measured.

2. single event transient pulse width measure circuit according to claim 1, wherein said control signal produces circuit (101) and comprises a basic RS latch of rejection gate, a reverser and one three input rejection gate RS latch.Wherein three input rejection gate RS latchs comprise R input end, S1 input end and S2 input end and Q output terminal and output terminal.Reset signal (reset) connects the R input end of the basic RS latch of rejection gate and the R input end of three input rejection gate RS latchs.010 type single-particle pulse signal (input) to be measured connects the S input end of the basic RS latch of rejection gate, the Q output terminal of the basic RS latch of rejection gate is the start-of-pulsing signal output terminal (out1) that control signal produces circuit, Q output terminal connects the S1 input end of three input rejection gate RS latchs simultaneously, input connects the input end of reverser simultaneously, the output terminal of reverser connects the S2 input end of three input rejection gate RS latchs, three input rejection gate RS latchs output terminal is the end-of-pulsing signal output terminal (end) that control signal produces circuit.

Single-particle pulse signal (input) to be measured is 010 type pulse signal, when a measurement is started, reset signal (reset) is high level, single-particle pulse to be measured is low level, now start-of-pulsing signal (out1) is low level, and end-of-pulsing signal (end) is high level; Then reset signal becomes low level, and now single-particle pulse signal to be measured is also low level, and start-of-pulsing signal keeps low level, and end-of-pulsing signal keeps high level.Afterwards when single-particle pulse signal to be measured becomes high level from low level, start-of-pulsing signal becomes as high level from low level, and end-of-pulsing signal keeps high level; When single-particle pulse signal to be measured reverts to low level by high level, start-of-pulsing signal keeps high level, and end-of-pulsing signal becomes low level from high level.

3. single event transient pulse width measure circuit according to claim 1, wherein said pair of delay comparison circuit comprises first delay circuit, second delay circuit and one three input rejection gate RS latch.Wherein the input end of the first delay circuit is the first time delay input end of two delay comparison circuit, and the output terminal of the first delay circuit is the first time delay output terminal of two delay comparison circuit.The input end of the second delay circuit is the second time delay input end of two delay comparison circuit, and the output terminal of the second delay circuit is the second time delay output terminal of two delay comparison circuit.First time delay output terminal connects the S1 input end of three input rejection gate RS latchs simultaneously, second delay output terminal connects the S2 input end of three input rejection gate RS latchs simultaneously, reset signal (reset) connects the R input end of three input rejection gate RS latchs, and the Q output terminal of three input rejection gate RS latchs is the comparison output terminal of two delay comparison circuit.

Wherein the first delay circuit and all available even number reverser of the second delay circuit are in series, but need both adjustments circuit size or circuit progression, must ensure that the delay ability of the first delay circuit is greater than the delay ability of the second delay circuit.Namely, when the input signal of the two is identical, the output signal of the first delay circuit is greater than the output signal time delay of the second delay circuit time delay.

4. single event transient pulse width measure circuit according to claim 1, in wherein said single-particle pulse width measurement circuit in the basic RS latch of three input rejection gate used, when R end is high level, when S1 and S2 end is not high level entirely, Q holds output low level end exports high level; When R end is for low level, when S1 and S2 is high level, Q end exports high level, end output low level; When R end is for low level, and when S1 and S2 be high level entirely, Q end with end output remains unchanged.