CN103983834A - Single-particle transient pulse signal amplitude measuring circuit - Google Patents
Single-particle transient pulse signal amplitude measuring circuit Download PDFInfo
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- CN103983834A CN103983834A CN201410209130.6A CN201410209130A CN103983834A CN 103983834 A CN103983834 A CN 103983834A CN 201410209130 A CN201410209130 A CN 201410209130A CN 103983834 A CN103983834 A CN 103983834A
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Abstract
A single-particle transient pulse signal amplitude measuring circuit comprises a pre-processing circuit and at least one level of detecting circuit. The pre-processing circuit is provided with a single-particle pulse receiving end, a reset input end, a pre-processing signal output end, a detecting signal output end and a true-false signal output end, produces a pre-processing signal and a first level detecting signal according to the input pulse, and gives a true-false signal to judge whether the input pulse width meets the testing requirement or not. Each level of detecting circuit is composed of a buffer and a NOR gate basic RS latch, and comprises a buffer input end, a buffer output end, a reset signal input end and a detecting signal output end, and buffer input signals are attenuated through the buffers. The buffer input end of the first level of detecting circuit is connected with the pre-processing signal, and the buffer input ends of the other levels of detecting circuits are connected with the previous level of buffer output end. The single-particle transient pulse signal amplitude measuring circuit can measure single-particle transient pulse signal amplitude and detect whether the input pulse width is in the testing range or not, the input load is small, and the measuring range and precision can be adjusted.
Description
Technical field
The present invention relates to Space Radiation Effects field of detecting and high frequency electric pulse fields of measurement, specifically, the present invention relates to a kind of single event transient pulse signal pulse amplitude metering circuit.
Background technology
Spationautics is to weigh the important symbol of a modernization of the country level and overall national strength, and integrated circuit is as the core of spacecraft, and oneself becomes one of main indexes of various spacecraft performances its performance and function.
Single particle effect, refers to the high energy particle existing in the radiation environments such as space flight and ground, causes the radiation damage effect that ionising radiation produces in chip internal sensitizing range.Ionising radiation produces intensive electrons pair on Particles Moving track, when these electrons are when being collected by circuit node, may change circuit normal operating conditions, causes error in data, works not normal, and chip such as burns at the serious consequence.
Along with constantly reducing of integrated circuit characteristic dimension, the continuous quickening of travelling speed, the continuous decline of operating voltage, circuit is more and more responsive to single particle effect.Single particle effect has become the safety and one of reliable hot issue of serious threat spacecraft.
Under radiation environment, particle will produce electrons pair to the bombardment of circuit on its movement locus, this electrons is to being absorbed by circuit node, to produce an instantaneous narrow pulse signal, be single event transient pulse signal, if this signal is propagated along C-path, reach the timing unit of latch or other types downwards, to cause single-particle inversion, thereby produce circuit mistake.And enough pulse widths and pulse height are the necessary conditions that single event transient pulse signal is able to propagate in C-path, therefore, the measurement of the single event transient pulse deration of signal, amplitude will be conducive to further investigate the genesis mechanism rule of single particle effect, measure the radiosensitive parameter of various spaceborne electronic devices and components and integrated circuit, evaluate the level of its anti-single particle effect, to the safety of guaranteeing spacecraft with reliable, significant.
Because single event transient pulse signal pulse width is very narrow, adopt the equipment such as oscillograph or logic analyser directly to measure, to device bandwidth and precision etc., require very high, single-particle research is the secret field of external emphasis, forbid this kind equipment outlet, home products is often difficult to meet measurement demand, measures difficulty large.
Summary of the invention
For this present situation, the invention provides a kind of transient pulse amplitude measurement circuit, comprising:
Pre-process circuit, there is single-particle reception of impulse end, the RESET input, preprocessed signal output terminal, detection signal output terminal and the signal output part of correcting errors, according to input pulse, produce preprocessed signal, and first order detection signal, and provide positive error signal and judge whether input pulse width meets test request; Level detection circuitry at least, every grade of testing circuit consists of impact damper and the basic RS latch of rejection gate, there is impact damper input end, buffer output end, reset signal input end and detection signal output terminal, decay to impact damper input signal by impact damper, when after decay, signal is enough to drive latch, detection signal output high level, when input signal is not enough to drive latch, detection signal output low level.
Wherein in first order testing circuit, impact damper input end connects preprocessed signal, and in all the other testing circuits at different levels, impact damper input end connects upper level buffer output end.
Wherein, described metering circuit is characterised in that, when signal pulse width to be detected is enough, the preprocessed signal that pre-process circuit produces and input signal pulse width are irrelevant, and only relevant with pulse height, and signal pulse amplitude to be detected is higher, and preprocessed signal pulse height is higher, pulse width is wider, and driving force is stronger.
Wherein, whether described positive error signal meets and measures required minimum pulse width for detection of pwm input signal, and detection signal is that high level explanation pwm input signal is enough, and measurement result is correct, detection signal is that low level shows that pwm input signal is not enough, measurement result mistake.
Wherein, the impact damper in this circuit consists of even number of inverters cascade, and wherein impact damper output signal pulses width is less than impact damper input signal pulse width.
Wherein, in every grade of testing circuit, the basic RS latch of rejection gate S end connects buffer output end at the corresponding levels, and R end connects the RESET input, and Q end connects detection signal output terminal.
Described testing circuit at different levels adopts identical physical dimension.According to the signal level of described positive error signal and testing circuit at different levels output, the anti-pulse amplitude of surveying of releasing.By structure, the size of impact damper in regulating power source voltage, testing circuit, regulate measurement range and measuring accuracy.
According to single event transient pulse signal amplitude metering circuit provided by the invention, can measure single event transient pulse signal amplitude, can automatically detect input pulse width whether in test specification, circuit input load is little, structure by impact damper used in regulating power source voltage or testing circuit, size etc., can regulate measurement range and measuring accuracy.
Accompanying drawing explanation
Fig. 1 is the pulse amplitude metering circuit structural representation in one embodiment of the invention;
Fig. 2 is the preliminary treatment circuit structure schematic diagram in one embodiment of the invention;
The output voltage adjustable phase inverter of Fig. 3 (a) for adopting in the pre-process circuit in one embodiment of the invention, the three input RS latch structure schematic diagram of Fig. 3 (b) for adopting in the pre-process circuit in one embodiment of the invention;
Fig. 4 is the pre-process circuit work wave schematic diagram in one embodiment of the invention;
Fig. 5 is buffer structure schematic diagram in the testing circuit in one embodiment of the invention;
Fig. 6 is the testing circuit work wave schematic diagram in one embodiment of the invention;
Fig. 7 is the overall work waveform schematic diagram that the single event transient pulse signal amplitude metering circuit in one embodiment of the invention is measured a single event transient pulse.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Figure 1 shows that the single event transient pulse signal amplitude metering circuit structural representation that one embodiment of the present of invention provide.According to embodiments of the invention, this circuit comprises pre-process circuit 101 and 16 grades of testing circuits; Pre-process circuit 101, for generation of preprocessed signal in, detection signal out1 and positive error signal right; Pre-process circuit pulse input end connects single event transient pulse signal input to be measured, and the RESET input connects reset signal reset, output preprocessed signal in, detection signal out1 and positive error signal right; 16 grades of testing circuits, every grade of testing circuit consists of impact damper and the basic RS latch of rejection gate, wherein buffer output end connects latch S input end, and reset signal reset connects latch R input end, and latch Q output terminals at different levels are detection signal out2 to outn output terminal.Except impact damper input end in first order testing circuit connects preprocessed signal in, in all the other testing circuits at different levels, impact damper input end connects upper level buffer output end.
The preliminary treatment circuit structure schematic diagram that Fig. 2 provides for one embodiment of the present of invention, this circuit comprises the basic RS latch 201 of rejection gate, delay circuit 202 and 206, Sheffer stroke gate 203, phase inverter 205, the output adjustable phase inverter 204 of high level and three input RS latchs 207.Wherein 201 R input end connects reset signal reset, and 201 S input end connects single event transient pulse signal input, and 201 Q output terminal is detection signal out1.201
output terminal
the output signal that connects delay circuit 202,202
two input ends (interchangeable) with out1 as NAND gate circuit 203,203 output signal in1 is as the input signal of phase inverter 204 and 205, wherein export the adjustable phase inverter of high level 204, its voltage input end connects input signal input, and 204 output signals are preprocessed signal in.The output signal o1_d that 205 output signal o1 connects phase inverter 206,206 connects respectively the S1 of three input RS latchs 207 with input, S2 input end (interchangeable), and o1 connects 207 R input end, and 207 Q end output signal is positive error signal right.
Fig. 3 (a) is adjustable phase inverter 204 circuit diagrams of output high level, and Fig. 3 (b) is three input RS latch 207 circuit diagrams.Wherein 204 input end is in, and output terminal is out, and voltage input end is in_vdd., when in is low level, out output amplitude is identical with in_vdd, and when in is high level, out is low level.Latch 207 is 1 as input signal S1 and S2, and input signal R is 0 o'clock, and output Q is 1,
be 0.When S1 and S2 are not 1 entirely, if R is 1, output Q is 0,
be 1, if R is 0, output remains unchanged.
In pre-process circuit, delay circuit 202 consists of 8 phase inverter cascades, delay circuit 206 consists of 4 phase inverter cascades, the pmos pipe breadth length ratio that wherein connects Q and S signal except grid in 201 is 0.89 micron/0.35 micron, in Sheffer stroke gate 203, pmos pipe breadth length ratio is 0.89 micron/0.35 micron, all the other pmos pipe breadth length ratios are 2.3 microns/0.35 micron, and all nmos pipe breadth length ratios are 0.89 micron/0.35 micron.
The pre-process circuit 101 working waveform figure schematic diagram that Fig. 4 provides for one embodiment of the present of invention, supply voltage 3.3V, in figure, be followed successively by from top to bottom output signal right, M signal o1_d M signal o1, output signal in, M signal in1, output signal out1, M signal q1_d, M signal q1_, input signal input, input signal reset.
When 370 nanosecond nanosecond to 372 of the emulation moment, reset signal is high level, and latch 201 resets, and out1 is low level, q1_ is high level, and q1_d is high level, and in1 is high level, and in is low level, o1 is low level, and o1_d is low level, and right signal remains unchanged.
When 375 nanosecond of the emulation moment, input signal output pulse width was 1.5 nanoseconds, amplitude is the high level signal of 3.3V, these signal driver 201 set, make out1 signal become high level, q1_ signal becomes low level, through 202 output q1_d, produces in signal and M signal o1 that pulsewidth is about 470 psecs.O1 signal is through 206 delay output o1_d, the two generates right signal with input effect, because the negative edge of input and o1_d is all later than the negative edge of o1, therefore when o1 signal is after high level becomes low level, existing a period of time to meet o1 is low level, o1_d and input are high level, make Output rusults right become high level.O1_d and input become low level afterwards, and right keeps high level constant.
Obviously, when input pulsewidth is not enough, input negative edge, early than o1 negative edge, after now input finishes, exists a period of time to meet, and input is that 0, o1_d and o1 are 1, makes right output low level, and then o1_d and o1 become 0, right maintenance low level.That is to say, if when input pulsewidth is enough wide, output right is high level, if input pulsewidth deficiency, exporting right is low level.By right signal, whether narrowly can detect when input signal pulse width, whether measurement result is correct.
The width and the amplitude emulation that change input are known, and when the input deration of signal is enough, the preprocessed signal in of generation is irrelevant with input pulse width, and only relevant with input pulse height.And input pulse height is higher, in pulse height is higher, and pulse width is wider; For example, input amplitude is 3.3V, and width was 1.5 nanoseconds, and output in signal amplitude is 3.3V, and width is 475 psecs; Input amplitude is 3.3V, and width was 2.5 nanoseconds, and output in signal amplitude is 3.3V, and width is 475 psecs; Input amplitude is 2V, and when width was 1.5 nanosecond, output in signal amplitude is 2V, and width is 327 psecs.
In the present embodiment, testing circuits at different levels all adopt identical physical dimension.In testing circuit, impact damper used consists of two different phase inverters of size, structure as shown in Figure 5, the breadth length ratio of the pmos pipe 401 being wherein connected with impact damper input signal delay_in is 2.1 microns/0.35 micron, and the breadth length ratio of nmos pipe 402 is 2 microns/0.35 micron.It is 2 microns/0.35 micron that the pmos being connected with impact damper output signal delay_out manages 403 breadth length ratios, and the breadth length ratio of nmos pipe 404 is 2.1 microns/0.35 micron.In testing circuit, in RS latch 302 used, pmos pipe breadth length ratio is 2.3 microns/0.35 micron, and nmos pipe breadth length ratio is 0.89 micron/0.35 micron.
Fig. 6, for the testing circuit work wave schematic diagram that one embodiment of the present of invention provide, is followed successively by from top to bottom, reset signal reset, impact damper input signal delay_in, impact damper output signal delay_out, result output signal out.Supply voltage 3.3V, when delay_in pulse width is 500 psec, output signal delay_out pulse width is about 480 psecs, and output signal pulses width is less than input signal pulse width.Delay_out drives the upset of RS latch, and Q end output signal out becomes 1.
The propagation of pulse signal in combinational circuit, is subject to pulse width and pulse amplitude joint effect, and pulse width is wider, and pulse height is higher, and driving force is stronger.Because the driving force of in is determined by input pulse height, therefore can be according to the driven situation of out1 to outn signal, the anti-input pulse height of releasing.
Fig. 7 shows the overall work waveform schematic diagram of a transient pulse of transient pulse signal amplitude measurement circuit measuring in one embodiment of the present of invention.Be respectively from top to bottom: detect output signal out17, out16 ..., out1, positive error signal right, single event transient pulse input signal input, the voltage waveform of reset signal reset.Supply voltage 3.3V, reset is since 10 nanoseconds, every through a pulse that width was 2 nanoseconds of 20 nanoseconds output, pulse height 3.3V, input is since 15 nanoseconds, every through a pulse that width was 1.5 nanoseconds of 20 nanoseconds output, pulse height is from 1.9V, step-length 0.1V, is increased to 3.3V, and simulation result is as shown in table 1.
At right, be 1 o'clock, according to the output level of out1 to out17, can instead release surveyed pulse height.When exporting right, be for example 1, and out1 to out12 is 1, out13 to out17 is 0 o'clock, and input voltage is 2.7V.Structure by impact damper in regulating power source voltage, testing circuit, size etc., can regulate measurement range and measuring accuracy.
Table 1
Above-described embodiment is preferably embodiment of the present invention; but embodiments of the present invention are not restricted to the described embodiments; other any do not deviate from change, the modification done under Spirit Essence of the present invention and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection scope of the present invention.
Claims (8)
1. a transient pulse amplitude measurement circuit, comprising:
Pre-process circuit (101), there is single-particle reception of impulse end, the RESET input, preprocessed signal output terminal, detection signal output terminal and the signal output part of correcting errors, according to input pulse, produce preprocessed signal, and first order detection signal, and provide positive error signal and judge whether input pulse width meets test request;
Level detection circuitry (102) at least, every grade of testing circuit consists of impact damper and the basic RS latch of rejection gate, there is impact damper input end, buffer output end, reset signal input end and detection signal output terminal, decay to impact damper input signal by impact damper, when after decay, signal is enough to drive latch, detection signal output high level, when input signal is not enough to drive latch, detection signal output low level;
Wherein in first order testing circuit, impact damper input end connects preprocessed signal, and in all the other testing circuits at different levels, impact damper input end connects upper level buffer output end.
2. metering circuit according to claim 1, it is characterized in that, when signal pulse width to be detected is enough, the preprocessed signal that pre-process circuit (101) produces and input signal pulse width are irrelevant, and only relevant with pulse height, and signal pulse amplitude to be detected is higher, and preprocessed signal pulse height is higher, pulse width is wider, and driving force is stronger.
3. metering circuit according to claim 1, it is characterized in that, whether positive error signal described in pre-process circuit meets and measures required minimum pulse width for detection of pwm input signal, detection signal is that high level explanation pwm input signal is enough, measurement result is correct, detection signal is that low level shows that pwm input signal is not enough, measurement result mistake.
4. metering circuit according to claim 1, is characterized in that, the impact damper in testing circuit consists of even number of inverters cascade, and wherein impact damper output signal pulses width is less than impact damper input signal pulse width.
5. metering circuit according to claim 1, is characterized in that, in every grade of testing circuit, the basic RS latch of rejection gate S end connects buffer output end at the corresponding levels, and R end connects the RESET input, and Q end connects detection signal output terminal.
6. metering circuit according to claim 1, is characterized in that, described testing circuits at different levels adopt identical physical dimension.
7. metering circuit according to claim 1, is characterized in that, according to the signal level of described positive error signal and testing circuit at different levels output, and the anti-pulse amplitude of surveying of releasing.
8. metering circuit according to claim 1, is characterized in that, by structure, the size of impact damper in regulating power source voltage, testing circuit, regulates measurement range and measuring accuracy.
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| CN201410209130.6A CN103983834B (en) | 2014-05-16 | 2014-05-16 | A kind of single-particle transient amplitude measurement circuitry |
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| CN201410209130.6A CN103983834B (en) | 2014-05-16 | 2014-05-16 | A kind of single-particle transient amplitude measurement circuitry |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105675984A (en) * | 2016-01-19 | 2016-06-15 | 中国科学院上海微系统与信息技术研究所 | Pulse waveform testing circuit |
| CN106569040A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN110208608A (en) * | 2019-05-10 | 2019-09-06 | 中国人民解放军国防科技大学 | Low-power-consumption miniaturized single-particle transient parameter testing device and method |
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| SU678434A1 (en) * | 1974-12-24 | 1979-08-05 | Предприятие П/Я Р-6303 | Device for measuring single and repeated impact pulses |
| JPS63227115A (en) * | 1987-03-16 | 1988-09-21 | Mitsubishi Electric Corp | Pulse converter |
| JPH0219772A (en) * | 1988-07-07 | 1990-01-23 | Mitsubishi Electric Corp | Pulse amplitude data sampling circuit |
| LV13662B (en) * | 2007-11-06 | 2008-02-20 | Elektronikas Un Datorzinatnu I | Device for measuring amplitudes of short single pulses |
| CN102818939B (en) * | 2011-06-08 | 2014-12-03 | 中国科学院微电子研究所 | Measuring circuit for single-event transient pulse width |
| CN103063933B (en) * | 2011-10-20 | 2015-08-05 | 中国科学院微电子研究所 | Single-particle pulse width measurement circuit |
| CN102565545A (en) * | 2011-12-30 | 2012-07-11 | 中国科学院微电子研究所 | System for detecting single-particle transient current pulse |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105675984A (en) * | 2016-01-19 | 2016-06-15 | 中国科学院上海微系统与信息技术研究所 | Pulse waveform testing circuit |
| CN105675984B (en) * | 2016-01-19 | 2019-03-29 | 中国科学院上海微系统与信息技术研究所 | A kind of impulse waveform test circuit |
| CN106569040A (en) * | 2016-10-31 | 2017-04-19 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN106569040B (en) * | 2016-10-31 | 2019-07-26 | 中国科学院微电子研究所 | Single event transient pulse width measurement circuit, integrated circuit and electronic equipment |
| CN110208608A (en) * | 2019-05-10 | 2019-09-06 | 中国人民解放军国防科技大学 | Low-power-consumption miniaturized single-particle transient parameter testing device and method |
| CN110208608B (en) * | 2019-05-10 | 2021-05-14 | 中国人民解放军国防科技大学 | Low-power-consumption miniaturized single-particle transient parameter testing device and method |
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Effective date of registration: 20170711 Address after: 100029 Beijing city Chaoyang District Beitucheng West Road No. 11 building 4 layer Institute of Microelectronics Patentee after: Beijing Zhongke Newmicrot Technology Development Co., Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |