CN106549047A - 一种纳米线无结晶体管及其制备方法 - Google Patents

一种纳米线无结晶体管及其制备方法 Download PDF

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CN106549047A
CN106549047A CN201610957456.6A CN201610957456A CN106549047A CN 106549047 A CN106549047 A CN 106549047A CN 201610957456 A CN201610957456 A CN 201610957456A CN 106549047 A CN106549047 A CN 106549047A
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nano
dielectric
active layer
drain region
source region
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CN106549047B (zh
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梁博
李骏
王威
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201610957456.6A priority Critical patent/CN106549047B/zh
Priority to PCT/CN2016/106039 priority patent/WO2018082118A1/zh
Priority to US15/314,057 priority patent/US10192954B2/en
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Abstract

本发明公开了一种纳米线无结晶体管及其制备方法，该晶体管内设置的多条纳米沟道线的各两端分别连接源区、漏区，且与源区、漏区属于同种类型掺杂的半导体材料，不仅增加了晶体管的开态电流，而且提高了晶体管的均一性，同时将该多条纳米沟道线以堆叠方式设置于有源层上，提高了晶体管的集成度。

Description

一种纳米线无结晶体管及其制备方法
技术领域
本发明涉及半导体器件领域，特别是涉及一种纳米线无结晶体管及其制备方法。
背景技术
传统PN结互补金属氧化物半导体晶体管的均一性易受半导体的尺寸差异、掺杂导致的阻抗差异及实际有效沟道的差异等因素的影响，对由此类晶体管构成的元器件的集成化、小型化不利。
发明内容
本发明主要解决的技术问题是提供一种纳米线无结晶体管及其制备方法，以改善晶体管均一性和提高晶体管集成度。
本发明提供一种纳米线无结晶体管，所述纳米线无结晶体管包括：有源层、源区、源电极、漏区、漏电极、栅电极、第一绝缘介质及至少两条纳米沟道线；
其中，所述源区、所述漏区设置于所述有源层上，所述至少两条纳米沟道线以堆叠方式设置于所述有源层上，且各两端分别连接所述源区、所述漏区；所述源区、所述漏区及所述纳米沟道线为同一掺杂材料；所述源电极、漏电极分别设置于所述源区、所述漏区上；所述第一绝缘介质设置于所述纳米沟道线与所述栅电极之间。
其中，所述第一绝缘介质包围所述纳米沟道线；所述栅电极完全包裹所述第一绝缘介质。
其中，所述纳米线无结晶体管还进一步包括第二绝缘介质，所述第二绝缘介质铺设于所述有源层及所述栅电极两侧。
其中，所述源电极、所述漏电极及所述栅电极为同一材料制作。
其中，所述纳米线无结晶体管还进一步包括阻挡层，所述阻挡层位于所述有源层背对所述源区、所述漏区的一侧。
本发明提供一种纳米线无结晶体管的制备方法，包括以下步骤：
准备基体；
刻蚀所述基体以形成有源层、源区、漏区及至少两条纳米沟道线，其中，所述源区、所述漏区设置于所述有源层上，所述至少两条纳米沟道线以堆叠方式设置于所述有源层上，且各两端分别连接所述源区、所述漏区；
在所述源区、所述漏区上分别形成源电极、漏电极，所述纳米沟道线外依次形成第一绝缘介质、栅电极，使得所述第一绝缘介质设置于所述纳米沟道线与所述栅电极之间。
其中，在所述准备基体步骤之前，进一步包括；
形成阻挡层，所述阻挡层位于所述有源层背对所述源区、所述漏区的一侧。
其中，所述刻蚀所述基体以形成有源层、源区、漏区及至少两条纳米沟道线步骤之后，在所述源区、所述漏区上分别形成源电极、漏电极，所述纳米沟道线外依次形成第一绝缘介质、栅电极，使得所述第一绝缘介质设置于所述纳米沟道线与所述栅电极之间步骤之前，进一步包括：
除去刻蚀保护层；
形成第二绝缘介质，将所述第二绝缘介质铺设于所述有源层及所述栅电极两侧。
其中，在所述准备基体步骤之后，所述刻蚀所述基体以形成有源层、源区、漏区及至少两条纳米沟道线步骤之前，进一步包括：
形成所述刻蚀保护层。
其中，刻蚀所述基体的循环次数决定了所述纳米沟道线的数量。
本发明的有益效果是：区别于现有技术，本发明纳米线无结晶体管及其制备方法通过设置多条纳米沟道线来增加晶体管的开态电流；通过设置多条纳米沟道线的各两端分别连接源区、漏区，且与源区、漏区属于同种类型掺杂的半导体材料来减少半导体的尺寸差异、掺杂导致的阻抗差异及实际有效沟道的差异等对晶体管均一性的影响。同时，通过将多条纳米沟道线以堆叠方式设置于有源层上来缩小晶体管的体积，从而提高晶体管的集成度。
附图说明
图1是本发明纳米线无结晶体管一实施例的结构示意图；
图2是图1实施例中纳米线无结晶体管工作时纳米沟道线内电子分布情况示意图；
图3是图1实施例纳米线无结晶体管制备方法的流程示意图；
图4是图1实施例中有源层被刻蚀之前纳米线无结晶体管的结构示意图；
图5是图1实施例中ONO结构包围纳米沟道线的结构截面示意图；
图6是图1实施例纳米线无结晶体管另一制备方法的流程示意图；
图7是图6实施例中步骤S61的具体步骤流程示意图；
图8是图6实施例中步骤S62的具体步骤流程示意图；
图9是图6实施例中步骤S64的具体步骤流程示意图；
图10是图1实施例中刻蚀第二绝缘介质后的纳米线无结晶体管的结构示意图。
具体实施方式
参阅图1，本实施例纳米线无结晶体管包括有源层102、源区104、源电极105、漏区106、漏电极107、至少两条纳米沟道线108、109、113、栅电极110及第一绝缘介质111(未标出)。
其中，源区104、漏区106设置于有源层102上，至少两条纳米沟道线108、109、113以堆叠方式设置于有源层102上，且各两端分别连接源区104、漏区106；所述源区104、漏区106及至少两条纳米沟道线108、109、113为同一掺杂材料；源电极105、漏电极107分别设置于源区104、漏区106上；第一绝缘介质111设置于至少两条纳米沟道线108、109、113与栅电极110之间。
进一步，在本实施例中源电极105、漏电极107及栅电极110为同一材料制作；第一绝缘介质111包围至少两条纳米沟道线108、109、113。
在一个应用场景中，栅电极110完全包裹第一绝缘介质111。在其它应用场景中，可根据晶体管具体功能需求设置栅电极110的铺设方式。
此外，本实施例还包括阻挡层101及第二绝缘介质103、1031、1032；其中，阻挡层101位于玻璃或PI等基板上，主要用于阻挡有源层102离子注入时的漏电；且有源层102位于阻挡层101上；第二绝缘介质103、1031、1032分别铺设于有源层102上及栅电极110两侧。
本实施例纳米线无结晶体管利用栅电极110电压的大小来控制纳米沟道线108的电流大小。具体原理请参阅图2，当栅电极110电压小于阈值电压时，纳米沟道线108的沟道处于电子耗尽状态，此时，只要源电极105、漏电极107之间的电压差不超过击穿电压，该晶体管都处于断开状态；当栅电极110电压等于阈值电压时，纳米沟道线108的沟道中心位置有电子浓度，若此时源电极105、漏电极107之间有电压差，则该晶体管处于导通状态，具有电流；当栅电极110电压大于阈值电压时，纳米沟道线108的沟道变宽，电流变大；而当栅电极110电压远大于阈值电压时，纳米沟道线108的沟道如同简单电阻器，电流达到峰值。
参阅图3，上述实施例纳米线无结晶体管可以采用如下方法制备：
步骤S31：准备基体401。
如图4所示，第一半导体材料上层经过掺杂形成基体401，基体401在高温下退火处理，进行离子活化。
在一个应用场景中，基体401的掺杂类型是N型，在其它应用场景中，可以根据纳米线无结晶体管制备的具体需求而使用P型，具体不做限定。
步骤S32：刻蚀基体401以形成有源层102、源区104、漏区106及至少两条纳米沟道线108、109、113，其中，源区104、漏区103设置于有源层102上，至少两条纳米沟道线108、109、113以堆叠方式设置于有源层上102，且各两端分别连接源区104、漏区106。
具体的，如图4所示，用与聚合物403对应的刻蚀气体刻蚀基体401，以得到源区104、漏区106及至少两条纳米沟道线108、109、113。
其中，刻蚀基体401的循环次数决定了得到纳米沟道线的数量，纳米沟道线的数量越大，晶体管的开态电流越大。
在一个应用场景中，刻蚀基体401的循环次数为3，得到3条纳米沟道线108、109、113，在其它应用场景中，刻蚀有源层102的循环次数根据纳米线无结晶体管制备的具体需求可变。
步骤S33：在源区104、漏区106上分别形成源电极105、漏电极107，至少两条纳米沟道线108、109、113外依次形成第一绝缘介质(未标出)、栅电极110，使所述第一绝缘介质设置于至少两条纳米沟道线108、109、113与栅电极110之间。
在一个应用场景中，化学气相沉淀沉积(CVD)ONO(氧化物501-氮化物502-氧化物503)结构(如图5所示)为第一绝缘介质504，并包围纳米沟道线108、109、113，图5为第一绝缘介质504包围纳米沟道线108的情况；然后CVD沉积第二半导体材料作栅电极110、源电极105、漏电极107，其中，栅电极110完全包裹第一绝缘介质504，源电极105、漏电极107分别设置在源区104、漏区106上。
在另一个应用场景中，栅电极110、源电极105、漏电极107的制作步骤同步进行。在其他应用场景中，也可非同步进行，具体不做限定。
参阅图6，可选地，在步骤S31之前，进一步包括；
步骤S61：形成阻挡层101，阻挡层101位于有源层102背对源区104、漏区106的一侧。
可选地，参阅图7，步骤S61进一步包括：
步骤S71：在玻璃或者PI等基板上CVD沉积第二半导体材料。
步骤S72：第二半导体材料经过准分子激光晶化(ELA)得到第一半导体材料。
步骤S73：第一半导体材料下层经过掺杂作为阻挡层101，主要用于阻挡第一半导体材料上层离子注入时的漏电。
参阅图6，可选地，在步骤S31之后，步骤S32之前，进一步包括：
步骤S62：形成刻蚀保护层402，如图4所示，该刻蚀保护层402包括图案化的刻蚀阻挡层404及聚合物403。
可选地，参阅图8，步骤S62进一步包括：
步骤S81：CVD沉积刻蚀阻挡层404，刻蚀阻挡层404经过光刻、干刻形成图案化的刻蚀阻挡层404，图案化的刻蚀阻挡层404覆盖在基体401上将要形成源区104、漏区106及纳米线108的位置。
步骤S82：再将聚合物403覆盖于图案化的刻蚀阻挡层404，形成刻蚀保护层402。
其中，图案化的刻蚀阻挡层404是第一半导体材料的氧化物。
在一个应用场景中，聚合物402是C4F8，在其它应用场景中，也可以是其它聚合物。
参阅图6，可选地，在步骤S32之后，在步骤S33之前，进一步包括：
步骤S63：除去刻蚀保护层402。
步骤S64：形成第二绝缘介质103，将第二绝缘介质103铺设于有源层102及栅电极110两侧。
可选地，参阅图9，步骤S64进一步包括：
步骤S91：CVD沉积第二绝缘介质103，并对第一绝缘介质103进行化学机械抛光，平坦化。
步骤S92：挖孔第二绝缘介质103，经光刻、干刻露出堆叠式纳米沟道线108、109、113及源区104、漏区106，如图10所示。
其中，第二绝缘介质103是第二半导体材料的氧化物；源区104、漏区106及纳米线108、109、113都是上述第一半导体材料通过同种元素掺杂而形成的，因此没有PN结存在。
其中，第一半导体材料随第二半导体材料而定。
在一个应用场景中，第二半导体材料是非晶硅(a-Si)，在其它应用场景中，第二半导体材料可以是其它半导体材料，具体不做限定。
区别于现有技术，上述实施例通过设置多条纳米沟道线来增加晶体管的开态电流；通过将多条纳米沟道线以堆叠方式设置于有源层上来缩小晶体管的体积；通过设置多条纳米沟道线的各两端分别连接源区、漏区，且与源区、漏区属于同种类型掺杂的半导体材料来提高晶体管的均一性问题。通过上述方式，本发明纳米线无结晶体管及其制备方法能够在保证满足晶体管开态电流大小需求的同时，进一步提高晶体管的集成度，而且晶体管的均一性也得到了提高。
区别于现有技术，上述实施例中，利用第一绝缘介质包围纳米沟道线，利用栅电极完全包裹第一绝缘介质，通过这种结构能够增强栅电极对纳米沟道线电子浓度的控制能力，有利于增大晶体管开态电流、提高晶体管的集成度。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种纳米线无结晶体管，其特征在于，包括：
有源层、源区、源电极、漏区、漏电极、栅电极、第一绝缘介质及至少两条纳米沟道线；
其中，所述源区、所述漏区设置于所述有源层上，所述至少两条纳米沟道线以堆叠方式设置于所述有源层上，且各两端分别连接所述源区、所述漏区；
所述源区、所述漏区及所述纳米沟道线为同一掺杂材料；
所述源电极、漏电极分别设置于所述源区、所述漏区上；
所述第一绝缘介质设置于所述纳米沟道线与所述栅电极之间。
2.根据权利要求1所述的晶体管，其特征在于，
所述第一绝缘介质包围所述纳米沟道线；
所述栅电极完全包裹所述第一绝缘介质。
3.根据权利要求1所述的晶体管，其特征在于，
进一步包括第二绝缘介质，所述第二绝缘介质铺设于所述有源层及所述栅电极两侧。
4.根据权利要求1至3任一项所述的晶体管，其特征在于，
所述源电极、所述漏电极及所述栅电极为同一材料制作。
5.根据权利要求1至3任一项所述的晶体管，其特征在于，
进一步包括阻挡层，所述阻挡层位于所述有源层背对所述源区、所述漏区的一侧。
6.一种纳米线无结晶体管的制备方法，其特征在于，包括以下步骤：
准备基体；
刻蚀所述基体以形成有源层、源区、漏区及至少两条纳米沟道线，其中，所述源区、所述漏区设置于所述有源层上，所述至少两条纳米沟道线以堆叠方式设置于所述有源层上，且各两端分别连接所述源区、所述漏区；
在所述源区、所述漏区上分别形成源电极、漏电极，所述纳米沟道线外依次形成第一绝缘介质、栅电极，使得所述第一绝缘介质设置于所述纳米沟道线与所述栅电极之间。
7.根据权利要求6所述的晶体管制备方法，其特征在于，
在所述准备基体步骤之前，进一步包括；
形成阻挡层，所述阻挡层位于所述有源层背对所述源区、所述漏区的一侧。
8.根据权利要求6所述的晶体管制备方法，其特征在于，
在所述刻蚀所述基体以形成有源层、源区、漏区及至少两条纳米沟道线步骤之后，在所述源区、所述漏区上分别形成源电极、漏电极，所述纳米沟道线外依次形成第一绝缘介质、栅电极，使得所述第一绝缘介质设置于所述纳米沟道线与所述栅电极之间步骤之前，进一步包括：
除去刻蚀保护层；
形成第二绝缘介质，将所述第二绝缘介质铺设于所述有源层及所述栅电极两侧。
9.根据权利要求6所述的晶体管制备方法，其特征在于，
在所述准备基体步骤之后，在所述刻蚀所述基体以形成有源层、源区、漏区及至少两条纳米沟道线步骤之前，进一步包括：
形成所述刻蚀保护层。
10.根据权利要求6至8任一项所述的晶体管制备方法，其特征在于，
刻蚀所述基体的循环次数决定了所述纳米沟道线的数量。
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