CN106531206B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN106531206B
CN106531206B CN201610704791.5A CN201610704791A CN106531206B CN 106531206 B CN106531206 B CN 106531206B CN 201610704791 A CN201610704791 A CN 201610704791A CN 106531206 B CN106531206 B CN 106531206B
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China
Prior art keywords
word line
coupled
voltage
semiconductor device
end portion
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CN201610704791.5A
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English (en)
Chinese (zh)
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CN106531206A (zh
Inventor
石井雄一郎
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN106531206A publication Critical patent/CN106531206A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
CN201610704791.5A 2015-09-11 2016-08-22 半导体器件 Active CN106531206B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-179683 2015-09-11
JP2015179683A JP6469554B2 (ja) 2015-09-11 2015-09-11 半導体装置

Publications (2)

Publication Number Publication Date
CN106531206A CN106531206A (zh) 2017-03-22
CN106531206B true CN106531206B (zh) 2022-05-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610704791.5A Active CN106531206B (zh) 2015-09-11 2016-08-22 半导体器件

Country Status (3)

Country Link
US (3) US9721647B2 (cg-RX-API-DMAC10.html)
JP (1) JP6469554B2 (cg-RX-API-DMAC10.html)
CN (1) CN106531206B (cg-RX-API-DMAC10.html)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6469554B2 (ja) * 2015-09-11 2019-02-13 ルネサスエレクトロニクス株式会社 半導体装置
US9786363B1 (en) * 2016-11-01 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM
US10943645B2 (en) * 2018-07-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd Memory device with a booster word line
JP7270451B2 (ja) * 2019-04-26 2023-05-10 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の駆動方法
CN112750479A (zh) * 2019-10-30 2021-05-04 台湾积体电路制造股份有限公司 字线驱动装置
US11189336B2 (en) * 2019-10-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Word line driving device for minimizing RC delay
JP2021108307A (ja) * 2019-12-27 2021-07-29 キオクシア株式会社 半導体記憶装置
US11170830B2 (en) * 2020-02-11 2021-11-09 Taiwan Semiconductor Manufacturing Company Limited Word line driver for low voltage operation
US11211113B1 (en) * 2020-08-18 2021-12-28 Micron Technology, Inc. Integrated assemblies comprising wordlines having ends selectively shunted to low voltage for speed transitioning
KR102963948B1 (ko) 2020-10-30 2026-05-11 삼성전자주식회사 워드 라인 보조 셀을 갖는 셀 어레이를 포함하는 집적 회로
US11521670B2 (en) * 2020-11-12 2022-12-06 Micron Technology, Inc. Word lines coupled to pull-down transistors, and related devices, systems, and methods
US12525261B2 (en) 2023-05-01 2026-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Memory devices with reduced bit line capacitance and methods of manufacturing thereof
KR20240173804A (ko) * 2023-06-07 2024-12-16 삼성전자주식회사 서브 워드라인 드라이버를 갖는 반도체 메모리 장치
CN122069710A (zh) * 2025-01-10 2026-05-19 台积电(南京)有限公司 具有隔开两个io功能电路的填充区的存储器单元

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1404147A (zh) * 2001-08-30 2003-03-19 株式会社东芝 电子电路以及半导体存储装置
CN1492445A (zh) * 2002-08-30 2004-04-28 ��ʽ���������Ƽ� 在内部产生内部数据读出时序的半导体存储器件
US7064981B2 (en) * 2004-08-04 2006-06-20 Micron Technology, Inc. NAND string wordline delay reduction
US7733686B2 (en) * 2006-12-30 2010-06-08 Texas Instruments Incorporated Pulse width control for read and write assist for SRAM circuits
US8014226B2 (en) * 2009-12-22 2011-09-06 Arm Limited Integrated circuit memory with word line driving helper circuits

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150189A (en) 1979-05-10 1980-11-21 Nec Corp Memory circuit
JPS60226095A (ja) * 1984-04-25 1985-11-11 Hitachi Micro Comput Eng Ltd 半導体記憶装置
JPS63276793A (ja) * 1987-05-07 1988-11-15 Nec Ic Microcomput Syst Ltd ワ−ド線駆動回路
JPH06203579A (ja) * 1993-01-08 1994-07-22 Fujitsu Ltd 出力回路及び記憶装置
JP4912016B2 (ja) 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4631743B2 (ja) 2006-02-27 2011-02-16 ソニー株式会社 半導体装置
US7379354B2 (en) * 2006-05-16 2008-05-27 Texas Instruments Incorporated Methods and apparatus to provide voltage control for SRAM write assist circuits
JP2014067942A (ja) * 2012-09-27 2014-04-17 Toshiba Corp 不揮発性半導体記憶装置
JP2014099225A (ja) 2012-11-14 2014-05-29 Renesas Electronics Corp 半導体装置
JP6469554B2 (ja) * 2015-09-11 2019-02-13 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1404147A (zh) * 2001-08-30 2003-03-19 株式会社东芝 电子电路以及半导体存储装置
CN1492445A (zh) * 2002-08-30 2004-04-28 ��ʽ���������Ƽ� 在内部产生内部数据读出时序的半导体存储器件
US7064981B2 (en) * 2004-08-04 2006-06-20 Micron Technology, Inc. NAND string wordline delay reduction
US7733686B2 (en) * 2006-12-30 2010-06-08 Texas Instruments Incorporated Pulse width control for read and write assist for SRAM circuits
US8014226B2 (en) * 2009-12-22 2011-09-06 Arm Limited Integrated circuit memory with word line driving helper circuits

Also Published As

Publication number Publication date
JP2017054570A (ja) 2017-03-16
US10255970B2 (en) 2019-04-09
CN106531206A (zh) 2017-03-22
US20170076785A1 (en) 2017-03-16
JP6469554B2 (ja) 2019-02-13
US9721647B2 (en) 2017-08-01
US20190035456A1 (en) 2019-01-31
US10354722B2 (en) 2019-07-16
US20170287553A1 (en) 2017-10-05

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