CN106502147B - The device of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA - Google Patents
The device of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA Download PDFInfo
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- CN106502147B CN106502147B CN201610865811.7A CN201610865811A CN106502147B CN 106502147 B CN106502147 B CN 106502147B CN 201610865811 A CN201610865811 A CN 201610865811A CN 106502147 B CN106502147 B CN 106502147B
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The device of pure-tone pulse detection and parameter Estimation, is related to Underwater Acoustics Engineering technical field, and in particular to a kind of underwater sound parameter estimation apparatus in a kind of underwater acoustic channel based on FPGA.In order to solve the problems, such as the detail programming for needing to re-design PCB when design carries out the underwater sound equipment of detection demand to underwater sound pure-tone pulse signal and carrying out corresponding language according to selected hardware.FPGA of the invention is connected to FPGA, E for completing pure-tone pulse detection and parameter Estimation, FLASH memory2Prom memory is connected to FPGA, and A/D Sampling Interface passes through 8 groups of A/D converters respectively and is connected to FPGA, and I/O input/output interface is connected to FPGA by I/O protection circuit for input and output；PC machine is also connected with DB9 plug connector by configuring cable connection DB9 plug connector, FPGA；FPGA passes through the interconnection of DB9 plug connector, realizes the communication with PC machine；Power supply interface is powered by power supply module.Corresponding AD conversion number of channels, sample rate and detection parameters etc. can be arranged according to the demand under different working conditions to pure-tone pulse detection in the present invention, have the characteristics that low-power consumption, compact and convenient for assigning, the present invention is suitable for hydrolocation and technical field of underwater acoustic communication.
Description
Technical field
The present invention relates to Underwater Acoustics Engineering technical fields, and in particular to a kind of underwater sound parameter estimation apparatus.
Background technique
No matter the development and utilization of ocean, or military safety and confrontation all be unable to do without a most basic problem, that
Exactly " position for how determining itself or other targets ".For this problem, various countries researcher begins to early in the 15th century
Very long and tortuous exploration, it has been found that in various form of energy, sound wave has optimal long-distance communications in ocean
Performance, sound wave are increasingly becoming the main carriers that information is propagated in ocean, and acoustics location and navigation technology also becomes submarine target positioning
With the powerful of navigation.
However, though which kind of hydrolocation method taken, Parameter Estimation Precision be all influence system accuracy it is decisive because
Element.For simple signal, method for parameter estimation be have been relatively mature, and be had in the complicated underwater acoustic channel for having Multi-path interference
Carry out the ability of parameter Estimation.However, hardware platform is also gradually updating, this just must with the development of embedded technology
The problem of being so related to algorithm transplanting.From the point of view of the exploitation actuality of underwater sound equipment, each HardwareUpgring can all redesign system
Make PCB, and carry out the detail programming of corresponding language according to selected hardware, does so and both elongated the development cycle, be also easy
Other problems are introduced during the transplantation process.And the device of pure-tone pulse detection and parameter Estimation is general in existing underwater acoustic channel
It is all based on DSP realization, DSP is suitble to serial algorithm, and multicomputer system is very expensive, and is only suitable for coarseness
Concurrent operation.So being faced with the challenge of performance, power consumption and the time that appears on the market, very great Cheng for tradition DSP is developed
The exploitation of the device of pure-tone pulse detection and parameter Estimation in underwater acoustic channel is limited on degree.
Summary of the invention
The present invention in order to solve design the underwater sound equipment of detection demand is carried out to the underwater sound pure-tone pulse signal when need weight
The problem of newly designing and producing PCB and carrying out the detail programming of corresponding language according to selected hardware is invented a based on FPGA
Underwater acoustic channel in pure-tone pulse detection and parameter Estimation device, can according under different working conditions to pure-tone pulse detection
Demand is arranged corresponding AD conversion number of channels, sample rate and detection parameters etc., which has low-power consumption, compact and just
In assign the characteristics of, it can be widely applied to the equipment such as hydrolocation and underwater images communication.
A kind of device of pure-tone pulse detection and parameter Estimation in the underwater acoustic channel based on FPGA, comprising: FPGA (Field-
Programmable Gate Array, field programmable gate array), 8 groups of A/D converter (Analog to
DigitalConverter, analog-digital converter), B2B connector, E2Prom memory (Electrically Erasable
ProgrammableRead-Only Memory, band electrically erasable programmable read-only memory), power supply module, FLASH storage
Device, DB9 plug connector (D type data interface connector)；
B2B connector includes I/O input/output interface, A/D Sampling Interface, power supply interface；
A/D Sampling Interface is separately connected 8 groups of A/D converters to FPGA；
FLASH memory is connected to FPGA, stores for parameter；
E2Prom memory is connected to FPGA, stores for program；
PC machine is also connected with DB9 plug connector by configuring cable connection DB9 plug connector, FPGA；FPGA passes through DB9 plug connector
Interconnection, realize and the communication of PC machine；
I/O input/output interface is connected to FPGA by I/O protection circuit for input and output；
Power supply interface is connected respectively to FPGA, 8 groups of A/D converters, E by power supply module2Prom memory, FLASH are deposited
Reservoir and DB9 plug connector, respectively FPGA, 8 groups of A/D converters, E2PROM, FLASH memory power supply；
The FPGA is for pure-tone pulse detection and parameter Estimation in underwater acoustic channel；Include:
Initialization unit guarantees that system is in the state that can be worked normally for the Initialize installation of system；
Communication control unit, for carrying out data exchange with PC machine or ppu, specifically include: parsing PC machine is logical
The instruction that serial ports is assigned is crossed, control FLASH read-write cell, A/D acquisition control unit and signal processing unit control I/O single
Member carries out parameter setting, analog-to-digital conversion, data and calculates and store, and frame is encoded and returned and carried out to parameter estimation result
The detection and forwarding of signal；
A/D acquisition control unit receives the output number of each road A/D converter for issuing A/D work clock and frame signal
According to, and each circuit-switched data is respectively written into the sampled data buffer area in this unit in case signal processing unit uses；A/D acquisition control
Unit processed can be changed acquisition channel quantity and sample rate by the management of communication control unit, and each channel A/D can be separately provided
Running parameter；
FLASH read-write cell, the parameter configuration assigned for storing PC machine specifically include that sample rate, the channel A/D
And corresponding sense channel quantity, preset signal feature and detection threshold value；
Signal processing unit, detection and parameter Estimation for underwater sound signal；
Whether I/O control unit has frame signal for real-time detection, and forwards frame signal when needed.
Preferably, signal processing unit carry out underwater sound signal detection and parameter estimation procedure the following steps are included:
Signal processing unit receives the pulse signal (noise-containing digital signal) of A/D converter output, believes pulse
It is number point-by-point to carry out Notch filtering processing, and noise estimation is carried out to pulse signal simultaneously, direct current biasing is estimated；
Pulse signal after Notch filtering processing is carried out taking envelope processing, and calculates instantaneous frequency variance, is calculated simultaneously
The amplitude threshold of pulse signal；
To effective impulse quantity, pulsewidth, time delay, instantaneous phase, weight and the envelope for taking the pulse signal after envelope processing
Row estimation, while carrying out envelope detector and the wide device cascading judgement that reflects, when pulse signal envelope forward position begins to exceed amplitude threshold,
And continuous sampling point is more than that (how many continuous sampled point is more than width to amplitude threshold depending on actual signal condition simultaneously
Spend thresholding), along being lower than amplitude threshold, and the instantaneous frequency of pulse signal in certain sampling timeframe after pulse signal envelope
Rate variance then determines that this signal is effective pulse signal lower than the instantaneous frequency variance threshold value of setting；Wherein envelope forward position
Respective amplitude is forward position energy threshold, after along respective amplitude be known as after along energy measuring thresholding, continuous sampling point number is that mirror is wide
Device width threshold.
Preferably, the signal processing unit is the instantaneous frequency variance that pulse signal is calculated by the way of sliding window
's.Since the instantaneous frequency variance of pulse signal is smaller, and noise and the variance of string leakage are larger, therefore by calculating the instantaneous of signal
Frequency variance carries out signal detection to assist envelope detector and examine wide device.
Preferably, noise estimation and the estimation of direct current biasing are all made of first order recursive algorithm.
Preferably, Notch filtering is iterated using LMS algorithm.
Notch filtering carries out point-by-point digital filtering to pulse signal using certain adaptive algorithm, to using LMS algorithm
Notch filtering for, it is necessary first to prestore two orthogonal reference signals, set up two variables to store weight,
It is secondary to go back the step-length it needs to be determined that a calculating；Entire filtering carries out under the iterative formula guidance of LMS algorithm, filter
Output reaches after a period of time has passed stablizes (entire estimation procedure must can be only achieved stable state by one section of learning time)；Filtering
While, utilize the envelope of continually changing two weight computing signals.
Preferably, described device is additionally provided with several extensions and is converted with A/D on the basis of being provided with 8 groups of A/D converters
Device；The B2B connector is additionally provided with several extension A/D Sampling Interfaces on the basis of being provided with A/D Sampling Interface；Described
Several extension A/D Sampling Interfaces are connected to FPGA with A/D converter by several extensions；Meanwhile power supply interface passes through power supply mould
Block is that several extensions are powered with A/D converter.
Preferably, the configuration cable embeds RS232 electrical level transferring chip；When FPGA passes through the mutual of DB9 plug connector
When the communication with PC machine is realized in connection, power supply interface powers to RS232 electrical level transferring chip by power supply module.
Preferably, the modulus conversion chip of the A/D converter is the AD7980 of Analog Devices company.It is most
High sampling rate is 1MSPS, supports SPI interface agreement.The circuit that FPGA controls A/D sampling in the present invention is exactly to utilize SPI interface
It realizes.
Preferably, the FLASH memory chip is the 39VF1601 of SST company production.Its capacity is 16Mbit, and
Only need 3.3V voltage just can work normally.User only needs control write enable signal, chip selection signal and output enable signal three
Signal wire just can complete the operation for being written or wiping FLASH data.Before a 16bit data are written to FLASH, it is necessary to
Three data of the write-in of sequence in specified address.Equally, before the data in erasing FLASH, it is also necessary to specified
Six data are sequentially written into address, to prevent accidentally delete operation.
Preferably, the B2B connector further includes ppu interface, the FPGA connection ppu interface.
FPGA in this way has the ability that data exchange is carried out with external embedded system.The purpose for reserving this ppu interface is
Communicated convenient for Function Extension in the future and with ppu, in this way other processors can output signal to the present apparatus into
The further processing of row.
The invention has the following advantages:
The device of the invention can be can be realized and be set to different parameters by the communication with PC machine for different operating conditions
It sets, i.e., parameter is configurable.Only estimated in this way using the parameter that a set of equipment can be realized as carrying out underwater sound signal for different operating conditions
Meter.The present invention does not need to re-design PCB for different operating conditions simultaneously, corresponding without carrying out according to selected hardware
The problem of detail programming of language.I.e. the present invention realizes modularization, easy to disassemble；Without making sheet again.
The present invention has carries out the detection of multichannel pure-tone pulse signal parallel and ginseng under underwater sound multi_path channel transmission conditions
The function of number estimation, the ability with good anti-channel string leakage and Multi-path interference.Signal processing algorithm is completed by FPGA, FPGA
Using the advantage of hardware concurrent, fine granularity, the operating structure of highly-parallel can be realized in piece.So permitting in FPGA resource
Perhaps under the premise of, the present invention can make full use of pipeline organization, can handle multiple signals simultaneously, and data throughout is high, place
It is fast to manage speed.Signal processing of the present invention includes noise estimation, direct current biasing estimation, Notch filtering, envelope detected, parameter
Estimation and VIFD string leakage inhibition etc., the processing result of output includes: noise background, direct current biasing, effective impulse quantity, side
Difference, pulsewidth, amplitude and time delay value etc..It is detected using the present invention, the minimum symbol spacing of detection is 200ms, maximum symbol
Width is 100ms；When sample rate is 100kSPS, the upper limit quantity for the treatment of channel is 20, when sample rate is 1MSPS, place
The upper limit quantity for managing channel is 2.
Detailed description of the invention
Fig. 1 is the device of the invention schematic diagram；
Fig. 2 is the schematic diagram of system in FPGA of the present invention.
Specific embodiment
Specific embodiment 1: illustrate present embodiment in conjunction with Fig. 1 and Fig. 2,
A kind of device of pure-tone pulse detection and parameter Estimation in the underwater acoustic channel based on FPGA, comprising: FPGA (Field-
Programmable Gate Array, field programmable gate array) 1,8 group of A/D converter (Analog to Digital
Converter, analog-digital converter) 2, B2B connector 6, E2Prom memory (Electrically Erasable
Programmable Read-Only Memory, band electrically erasable programmable read-only memory) 3, power supply module 4, FLASH deposit
Reservoir 5, DB9 plug connector (D type data interface connector) 9；
B2B connector 6 includes I/O input/output interface 610, A/D Sampling Interface 602, power supply interface 604；
A/D Sampling Interface 602 is connected to FPGA1 by 8 groups of A/D converters 2 respectively；
FLASH memory 5 is connected to FPGA1, stores for parameter；
E2Prom memory 3 is connected to FPGA1, stores for program；
PC machine 7 connects DB9 plug connector 9 by configuring cable 8, and FPGA1 is also connected with DB9 plug connector 9；FPGA1 passes through DB9
The communication with PC machine 7 is realized in the interconnection of plug connector；
I/O input/output interface 610 is connected to FPGA1 by I/O protection circuit for input and output 10；
Power supply interface 604 is connected respectively to FPGA1,8 groups of A/D converters 2, E by power supply module 42Prom memory 3,
FLASH memory 5 and DB9 plug connector 9, respectively FPGA1,8 groups of A/D converters 2, E2PROM3, FLASH memory 5 are powered；
Parameter Estimation of the FPGA1 for pure-tone pulse detection sum in underwater acoustic channel；Including
Initialization unit guarantees that system is in the state that can be worked normally for the Initialize installation of system；
Communication control unit, for carrying out data exchange with PC machine or ppu, specifically include: parsing PC machine is logical
The instruction that serial ports is assigned is crossed, control FLASH read-write cell, A/D acquisition control unit and signal processing unit control I/O single
Member carries out parameter setting, analog-to-digital conversion, data and calculates and store, and frame is encoded and returned and carried out to parameter estimation result
The detection and forwarding of signal；
A/D acquisition control unit；For issuing A/D work clock and frame signal, the output number of each road A/D converter is received
According to, and each circuit-switched data is respectively written into the sampled data buffer area in this unit in case signal processing unit uses；A/D acquisition control
Unit processed can be changed acquisition channel quantity and sample rate by the management of communication control unit, and each channel A/D can be separately provided
Running parameter；
FLASH read-write cell；The parameter configuration assigned for storing PC machine specifically includes that sample rate, the channel A/D
And corresponding sense channel quantity, preset signal feature and detection threshold value；
Signal processing unit, detection and parameter Estimation for underwater sound signal；
Whether I/O control unit has frame signal for real-time detection, and forwards frame signal when needed.
The present invention has carries out the detection of multichannel pure-tone pulse signal parallel and ginseng under underwater sound multi_path channel transmission conditions
The function of number estimation, the ability with good anti-channel string leakage and Multi-path interference.Signal processing algorithm therein is complete by FPGA
At under the premise of FPGA resource allows, the present invention makes full use of pipeline organization, can handle multiple signals, data simultaneously
Handling capacity is high, and processing speed is fast.The processing capacity being had are as follows: the minimum symbol spacing that can be detected is 200ms, and maximum symbol is wide
Degree is 100ms；It needs to carry out initial configuration before use in advance, i.e., running parameter is set using the special interface of PC machine, such as: adopting
Sample rate, the channel A/D and corresponding sense channel quantity, preset signal feature and detection threshold value, wherein preset signal characteristic is joined
Number includes: the centre frequency of signal to be detected, signal bandwidth；Preset detection threshold value includes: frequency difference thresholding, variance thresholding, width
Spend thresholding and width threshold.Then being configured cable 8 will need preset running parameter to be sent to FPGA1, by FPGA1 by work
Parameter is written in FLASH memory 5；The working procedure of device is stored in E2In prom memory 3, setting rear this system can
To be detached from PC machine work.When normal work, FPGA1 program reads the running parameter in FLASH memory 5 in initial phase,
Foundation as FPGA1 resource allocation and signal processing.Turned according to signal frequency to be detected and type setting sample rate and A/D
2 number of channels of parallel operation, selectable sample rate are 100kSPS, 400kSPS and 1MSPS, corresponding A/D2 and sense channel quantity
Respectively 20,8 and 2；Corresponding A/D converter 2 carries out analog-to-digital conversion under the timing control of FPGA.Number of the FPGA to input
Word signal carries out digital filtering, envelope detection and reflect wide device cascading judgement, the detection of instantaneous frequency variance and the parameter of multidiameter delay
Estimation, and output result is transmitted with certain coded format by RS232 serial ports, when the signal detection of a cycle is completed
Afterwards, signal processing results being transmitted in the initial phase in next period, the quantity according to preset treatment channel carries out data encoding,
It is followed successively by channel number, processing result data, parity check bit, with the submitting of RS232 serial mode.Serial ports output end is separately connected
B2B connector 6 and DB9 connector 9 can through B2B connector 6 when processing result needs to send to the processors such as DSP or ARM
Direct communication；If processing result needs to send PC machine to, by DB9 connector 9, it is configured cable 8 and is communicated with PC machine, configures
The inner design of cable 8 has electrical level transferring chip, which is powered by module through DB9 connector 9；Work between multidiameter delay channel
Independently of each other, the initial time benchmark of signal is determined that other running parameters can be separately provided by the lock-out pulse inputted.
Module of the present invention is based on modular design philosophy, can directly assign in other job platforms, has good suitable
Ying Xing.It is flat can directly to assign into other for powering, extending A/D2 interface and data exchange for the B2B connector 6 of module configuration
On platform, realized respectively by the line on other platforms and the connection of the output end of receiver and processing result receiving end.Power supply
Input voltage range are as follows: 5V~14V is furnished with DC-DC converter in module, completes to turn the supply voltage of each section in module
It changes.
Specific embodiment 2:
Signal processing unit described in present embodiment carries out the detection of underwater sound signal and parameter estimation procedure includes following step
It is rapid:
Signal processing unit receives the pulse signal (noise-containing digital signal) of A/D converter output, believes pulse
It is number point-by-point to carry out Notch filtering processing, and noise estimation is carried out to pulse signal simultaneously, direct current biasing is estimated；
Pulse signal after Notch filtering processing is carried out taking envelope processing, and calculates instantaneous frequency variance, is calculated simultaneously
The amplitude threshold of pulse signal；
To effective impulse quantity, pulsewidth, time delay, instantaneous phase, weight and the envelope for taking the pulse signal after envelope processing
Row estimation, while carrying out envelope detector and the wide device cascading judgement that reflects, when pulse signal envelope forward position begins to exceed amplitude threshold,
And continuous sampling point is more than that (how many continuous sampled point is more than width to amplitude threshold depending on actual signal condition simultaneously
Spend thresholding), along being lower than amplitude threshold, and the instantaneous frequency of pulse signal in certain sampling timeframe after pulse signal envelope
Rate variance then determines that this signal is effective underwater sound simple signal lower than the instantaneous frequency variance threshold value of setting；Wherein envelope
Forward position respective amplitude be forward position energy threshold, after along respective amplitude be known as after along energy measuring thresholding, continuous sampling point number is
The wide device width threshold of mirror.
Other structures and parameter are same as the specific embodiment one.
Specific embodiment 3:
Signal processing unit described in present embodiment is the instantaneous frequency that pulse signal is calculated by the way of sliding window
Variance.Since the instantaneous frequency variance of pulse signal is smaller, and noise and the variance of string leakage are larger, therefore by calculating signal
Instantaneous frequency variance carries out signal detection to assist envelope detector and examine wide device.
Other structures and parameter are the same as one or two specific embodiments.
Specific embodiment 4:
The estimation of noise described in present embodiment and the estimation of direct current biasing are all made of first order recursive algorithm.
Other structures and parameter are identical as one of specific embodiment one to three.
Specific embodiment 5:
The filtering of Notch described in present embodiment is carried out using LMS algorithm iteration.
Notch filtering carries out point-by-point digital filtering to pulse signal using certain adaptive algorithm, to using LMS algorithm
Notch filtering for, it is necessary first to prestore two orthogonal reference signals, set up two variables to store weight,
It is secondary to go back the step-length it needs to be determined that a calculating；Entire filtering carries out under the iterative formula guidance of LMS algorithm, filter
Output reaches after a period of time has passed stablizes (entire estimation procedure must can be only achieved stable state by one section of learning time)；Filtering
While, utilize the envelope of continually changing two weight computing signals.
Other structures and parameter are identical as one of specific embodiment one to four.
Specific embodiment 6:
Present embodiment described device is additionally provided with several extensions and is turned with A/D on the basis of being provided with 8 groups of A/D converters
Parallel operation 12；The B2B connector 6 is additionally provided with several extension A/D Sampling Interfaces on the basis of being provided with A/D Sampling Interface 602
612；Several extension A/D Sampling Interfaces 612 are connected to FPGA1 by several extension A/D converters 12；Meanwhile it supplying
Electrical interface is that several extension A/D converters 12 are powered by power supply module 4.
Other structures and parameter are identical as one of specific embodiment one to five.
Specific embodiment 7:
Configuration cable 8 described in present embodiment embeds RS232 electrical level transferring chip 11；When FPGA1 passes through DB9 plug connector
When the communication with PC machine 7 is realized in 9 interconnection, power supply interface 604 is by power supply module 4 to RS232 electrical level transferring chip 11
Power supply.
Other structures and parameter are identical as one of specific embodiment one to six.
Specific embodiment 8:
The modulus conversion chip of A/D converter 2 described in present embodiment is the AD7980 of Analog Devices company.
Its highest sample rate is 1MSPS, supports SPI interface agreement.The circuit that FPGA controls A/D sampling in the present invention is exactly to utilize SPI
What interface was realized.
Other structures and parameter are identical as one of specific embodiment one to seven.
Specific embodiment 9:
5 chip of FLASH memory described in present embodiment is the 39VF1601 of SST company production.Its capacity is
16Mbit, and 3.3V voltage is only needed just can to work normally.User only needs control write enable signal, chip selection signal and output enabled
Three signal wires of signal just can complete the operation for being written or wiping FLASH data.To FLASH be written 16bit data it
Before, it is necessary to three data of the write-in of sequence in specified address.Equally, before the data in erasing FLASH, it is also necessary to
Six data of the write-in of sequence in specified address, to prevent accidentally delete operation.
Other structures and parameter are identical as one of specific embodiment one to eight.
Specific embodiment 10:
B2B connector 6 described in present embodiment further includes ppu interface 601, the FPGA1 connection external treatment
Device interface 601.FPGA1 in this way has the ability that data exchange is carried out with external embedded system, will such as by way of bus
Data are transmitted to arm processor, or data are transmitted to DSP by McBSP interface.Reserve the purpose of this ppu interface
It is easy for Function Extension in the future and is communicated with ppu, other processors can be to the output signal of the present apparatus in this way
It is further processed.
There are two types of flow directions for processing result.If necessary to which data are uploaded to PC machine, then DB9 connector is accessed, FPGA passes through
It configures cable and data is transmitted to PC machine；If data will be transmitted to other processors, by B2B connector " with external treatment
Device interface " carries out, but is also carried out data transmission with the agreement of serial communication, i.e. data output routine inside FPGA is same
Program is covered, is all 232 serial port logics.
Other structures and parameter are identical as one of specific embodiment one to nine.
Claims (10)
1. the device of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA characterized by comprising
FPGA (1), 8 groups of A/D converters (2), B2B connector (6), E2Prom memory (3), power supply module (4), FLASH memory
(5), DB9 plug connector (9)；
B2B connector (6) includes that I/O input/output interface (610), A/D Sampling Interface (602), power supply interface (604), A/D are adopted
Sample interface (602) is connected to FPGA (1) by 8 groups of A/D converters (2) respectively；
FLASH memory (5) is connected to FPGA (1), stores for parameter；
E2Prom memory (3) is connected to FPGA (1), stores for program；
PC machine (7) is also connected with DB9 plug connector (9) by configuring cable (8) connection DB9 plug connector (9), FPGA (1)；FPGA
(1) interconnection for passing through DB9 plug connector, realizes the communication with PC machine (7)；
I/O input/output interface (610) is connected to FPGA (1) by I/O protection circuit for input and output (10)；
Power supply interface (604) is connected respectively to FPGA (1), 8 groups of A/D converters (2), E by power supply module (4)2Prom memory
(3), FLASH memory (5) and DB9 plug connector (9), respectively FPGA (1), 8 groups of A/D converters (2), E2PROM(3)、
FLASH memory (5) power supply；
The FPGA (1) is for pure-tone pulse detection and parameter Estimation in underwater acoustic channel；Including
Initialization unit guarantees that system is in the state that can be worked normally for the Initialize installation of system；
Communication control unit, for carrying out data exchange with PC machine or ppu, specifically include: parsing PC machine passes through string
The instruction assigned of mouth, control FLASH read-write cell, A/D acquisition control unit and signal processing unit, to I/O control unit into
Row parameter setting, analog-to-digital conversion, data calculate and storage, and frame signal is encoded and returned and carried out to parameter estimation result
Detection and forwarding；
A/D acquisition control unit receives the output data of each road A/D converter for issuing A/D work clock and frame signal,
And each circuit-switched data is respectively written into this unit in case signal processing unit uses；A/D acquisition control unit is by communication control list
The management of member, can change acquisition channel quantity and sample rate, the running parameter in each channel A/D can be separately provided；
FLASH read-write cell, the parameter configuration assigned for storing PC machine specifically include that sample rate, the channel A/D and right
The sense channel quantity answered, preset signal feature and detection threshold value；
Signal processing unit, detection and parameter Estimation for underwater sound signal；
Whether I/O control unit has frame signal for real-time detection, and forwards frame signal.
2. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 1
Set, which is characterized in that signal processing unit carry out underwater sound signal detection and parameter estimation procedure the following steps are included:
Signal processing unit receives the pulse signal of A/D converter output, carries out Notch filtering processing point by point to pulse signal,
And noise estimation, direct current biasing estimation are carried out to pulse signal simultaneously；
Pulse signal after Notch filtering processing is carried out taking envelope processing, and calculates instantaneous frequency variance, while calculating pulse
The amplitude threshold of signal；
The effective impulse quantity, pulsewidth, time delay, instantaneous phase, weight and the envelope that take the pulse signal after envelope processing are carried out
Estimation, while carrying out envelope detector and the wide device cascading judgement that reflects, when pulse signal envelope forward position begins to exceed amplitude threshold, and
Continuous sampling point is more than amplitude threshold simultaneously, and edge is lower than amplitude threshold, and the instantaneous frequency of pulse signal after pulse signal envelope
Rate variance then determines that this signal is effective underwater sound simple signal lower than the instantaneous frequency variance threshold value of setting；Wherein envelope
Forward position respective amplitude be forward position energy threshold, after along respective amplitude be known as after along energy measuring thresholding, continuous sampling point number is
The wide device width threshold of mirror.
3. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 2
It sets, which is characterized in that the signal processing unit is the instantaneous frequency variance that pulse signal is calculated by the way of sliding window
's.
4. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 3
It sets, which is characterized in that the noise estimation and the estimation of direct current biasing are all made of first order recursive algorithm.
5. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 4
It sets, which is characterized in that the Notch filtering is carried out using LMS algorithm iteration.
6. pure-tone pulse detection and parameter are estimated in a kind of underwater acoustic channel based on FPGA according to one of claims 1 to 5
The device of meter, which is characterized in that described device is additionally provided with several extensions and uses A/D on the basis of being provided with 8 groups of A/D converters
Converter (12)；The B2B connector (6) is additionally provided with several extension A/D on the basis of being provided with A/D Sampling Interface (602)
Sampling Interface (612)；Several extension A/D Sampling Interfaces (612) are connected to by several extensions with A/D converter (12)
FPGA(1)；Meanwhile power supply interface is several extensions A/D converter (12) power supply by power supply module (4).
7. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 6
It sets, which is characterized in that the configuration cable (8) embeds RS232 electrical level transferring chip (11)；When FPGA (1) passes through DB9 grafting
When the interconnection realization of part (9) and the communication of PC machine (7), power supply interface (604) is by power supply module (4) to RS232 level
Conversion chip (11) power supply.
8. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 1
It sets, which is characterized in that the modulus conversion chip of the A/D converter (2) is the AD7980 of Analog Devices company.
9. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 1
It sets, which is characterized in that FLASH memory (5) chip is the 39VF1601 of SST company production.
10. the dress of pure-tone pulse detection and parameter Estimation in a kind of underwater acoustic channel based on FPGA according to claim 1
It sets, which is characterized in that the B2B connector (6) further includes ppu interface (601), at FPGA (1) connection outside
It manages device interface (601).
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