CN106502147A - The device of pure-tone pulse detection and parameter estimation in a kind of underwater acoustic channel based on FPGA - Google Patents
The device of pure-tone pulse detection and parameter estimation in a kind of underwater acoustic channel based on FPGA Download PDFInfo
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- CN106502147A CN106502147A CN201610865811.7A CN201610865811A CN106502147A CN 106502147 A CN106502147 A CN 106502147A CN 201610865811 A CN201610865811 A CN 201610865811A CN 106502147 A CN106502147 A CN 106502147A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
In a kind of underwater acoustic channel based on FPGA, the device of pure-tone pulse detection and parameter estimation, is related to Underwater Acoustics Engineering technical field, and in particular to a kind of underwater sound parameter estimation apparatus.In order to solve the problems, such as to need the detail programming for re-designing PCB and carrying out corresponding language according to selected hardware when design carries out the underwater sound equipment of detection demand to underwater sound pure-tone pulse signal.The FPGA of the present invention is used for completing pure-tone pulse detection and parameter estimation, and FLASH memory is connected to FPGA, E2Prom memory is connected to FPGA, and A/D Sampling Interfaces are connected to FPGA by 8 groups of A/D converters respectively, and I/O input/output interfaces are connected to FPGA by I/O protection circuit for input and output;PC is also connected with DB9 plug connectors by configuring cable connection DB9 plug connector, FPGA;FPGA is connected with each other by DB9 plug connectors, realizes the communication with PC;Power supply interface is powered by supply module.The present invention according to corresponding AD conversion number of channels, sample rate is arranged under different working conditions to the demand that pure-tone pulse is detected and can detect parameter etc., there is low-power consumption, compact and be easy to the characteristics of assigning, the present invention is applied to hydrolocation and technical field of underwater acoustic communication.
Description
Technical field
The present invention relates to Underwater Acoustics Engineering technical field, and in particular to a kind of underwater sound parameter estimation apparatus.
Background technology
The no matter development and utilization of ocean, or the safety of military affairs and antagonism, all be unable to do without a most basic problem, that
Exactly " how to determine the position of itself or other targets ".For this problem, various countries' research worker is begun to early in the 15th century
The very long and exploration of complications, it has been found that in various form of energy, sound wave has optimal long-distance communications in ocean
Performance, sound wave are increasingly becoming the main carriers of Information Communication in ocean, and acoustics location and navigation technology also becomes submarine target positioning
Powerful with navigation.
Though however, take which kind of hydrolocation method, Parameter Estimation Precision be all affect system accuracy decisive because
Element.For simple signal, its method for parameter estimation is more ripe, possesses in having the complicated underwater acoustic channel of Multi-path interference
Carry out the ability of parameter estimation.However, with the development of embedded technology, hardware platform is also gradually updating, and this just must
So it is related to the problem of algorithm transplanting.From the point of view of the exploitation actuality of underwater sound equipment, each HardwareUpgring can all redesign system
Making PCB, and the detail programming of corresponding language being carried out according to selected hardware, do so had both elongated the construction cycle, also easily
Other problemses are introduced in migration process.And the device of pure-tone pulse detection and parameter estimation is general in existing underwater acoustic channel
DSP realizations are all based on, DSP is suitable for serial algorithm, and multicomputer system is very expensive, and is only suitable for coarseness
Concurrent operation.So for tradition DSP is developed, being faced with performance, power consumption and the challenge of the time that appears on the market, very great Cheng
The exploitation of the device of pure-tone pulse detection and parameter estimation in underwater acoustic channel is limited on degree.
Content of the invention
The present invention in order to solve design underwater sound pure-tone pulse signal is carried out detection demand underwater sound equipment when need weight
Newly design and produce PCB and the problem of the detail programming of corresponding language is carried out according to selected hardware, invent a based on FPGA
Underwater acoustic channel in pure-tone pulse detection and parameter estimation device, can according under different working conditions to pure-tone pulse detect
Demand arranges corresponding AD conversion number of channels, sample rate and detection parameter etc., and the device has low-power consumption, compact and just
The characteristics of assigning, the equipment such as hydrolocation and underwater images communication is can be widely applied to.
The device of pure-tone pulse detection and parameter estimation in a kind of underwater acoustic channel based on FPGA, including:FPGA(Field-
Programmable Gate Array, field programmable gate array), 8 groups of A/D converter (Analog to
DigitalConverter, analog-digital converter), B2B connectors, E2Prom memory (Electrically Erasable
ProgrammableRead-Only Memory, band EEPROM (Electrically Erasable Programmable Read Only Memo)), supply module, FLASH storage
Device, DB9 plug connectors (D type data interface connectors);
B2B connectors include I/O input/output interfaces, A/D Sampling Interfaces, power supply interface;
A/D Sampling Interfaces connect 8 groups of A/D converters respectively to FPGA;
FLASH memory is connected to FPGA, stores for parameter;
E2Prom memory is connected to FPGA, for program storage;
PC is also connected with DB9 plug connectors by configuring cable connection DB9 plug connector, FPGA;FPGA passes through DB9 plug connectors
Be connected with each other, realize and the communication of PC;
I/O input/output interfaces are connected to FPGA by I/O protection circuit for input and output;
Power supply interface is connected respectively to FPGA, 8 groups of A/D converters, E by supply module2Prom memory, FLASH are deposited
Reservoir and DB9 plug connectors, respectively FPGA, 8 groups of A/D converters, E2PROM, FLASH memory are powered;
Described FPGA is used for pure-tone pulse detection and parameter estimation in underwater acoustic channel;Including:
Initialization unit, for the Initialize installation of system, it is ensured that state of the system in energy normal work;
Communication control unit, for carrying out data exchange with PC or ppu, specifically includes:Parsing PC leads to
The instruction that serial ports is assigned is crossed, control FLASH read-write cells, A/D acquisition control units and signal processing unit are single to I/O controls
Unit carries out parameter setting, analog digital conversion, data and calculates and store, and parameter estimation result is encoded and is returned and carry out frame
The detection and forwarding of signal;
A/D acquisition control units, for sending A/D work clocks and frame signal, receive the output number of each road A/D converter
According to, and each circuit-switched data is respectively written into the sampled data buffer area in this unit in case signal processing unit is used;A/D collection controls
Unit processed is managed by communication control unit, can change acquisition channel quantity and sample rate, can be separately provided each A/D passages
Running parameter;
FLASH read-write cells, for storing the parameter configuration that PC is assigned, mainly include:Sample rate, A/D passages
And corresponding sense channel quantity, preset signal feature and detection threshold value;
Signal processing unit, the detection and parameter estimation for underwater sound signal;
Whether I/O control units, have frame signal for real-time detection, and forward frame signal when needed.
Preferably, signal processing unit carries out the detection of underwater sound signal and parameter estimation procedure is comprised the following steps:
Signal processing unit receives the pulse signal (containing noisy digital signal) of A/D converter output, and pulse is believed
Number pointwise carries out Notch Filtering Processing, and pulse signals carry out Noise Estimation, direct current biasing and estimate simultaneously;
Pulse signal after Notch Filtering Processing is carried out taking envelope processing, and calculates instantaneous frequency variance, while calculating
The amplitude threshold of pulse signal;
To taking effective impulse quantity, pulsewidth, time delay, instantaneous phase, weights and the envelope of the pulse signal after envelope processing
Row is estimated, while envelope detector and the wide device cascading judgement of mirror is carried out, when pulse signal envelope forward position begins to exceed amplitude threshold,
And continuous sampling point exceedes amplitude threshold (exceedes width according to how many continuous sampled point depending on actual RST simultaneously
Degree thresholding), pulse signal envelope tailing edge is less than amplitude threshold, and the instantaneous frequency of pulse signal in certain sampling timeframe
Less than the instantaneous frequency variance threshold value for setting, rate variance then judges that this signal is effective pulse signal;Wherein envelope forward position
Respective amplitude is forward position energy threshold, and tailing edge respective amplitude referred to as tailing edge energy measuring thresholding, continuous sampling point number are wide for mirror
Device width threshold.
Preferably, described signal processing unit is the instantaneous frequency variance for calculating pulse signal by the way of sliding window
's.As the instantaneous frequency variance of pulse signal is less, and the variance of noise and string leakage is larger, therefore by the instantaneous of signal calculated
Frequency variance, aids in envelope detector and the wide device of inspection to carry out signal detection.
Preferably, the estimation of described Noise Estimation and direct current biasing adopts first order recursive algorithm.
Preferably, described Notch filtering is iterated using LMS algorithm.
Notch filtering carries out pointwise digital filtering using certain adaptive algorithm pulse signals, to adopting LMS algorithm
Notch filterings for, it is necessary first to prestore two orthogonal reference signals, sets up two variables to store weights, its
The secondary step-length for also needing to determine a calculating;Whole filtering is carried out in the case where the iterative formula of LMS algorithm is instructed, wave filter
Output reaches stable (whole estimation procedure must can be only achieved stable state through one section of learning time) after a period of time has passed;Filtering
While, using the envelope of two weight computing signals being continually changing.
Preferably, described device on the basis of 8 groups of A/D converters are provided with are additionally provided with some extension A/D and change
Device;The B2B connectors are additionally provided with some extension A/D Sampling Interfaces on the basis of A/D Sampling Interfaces are provided with;Described
Some extension A/D Sampling Interfaces are connected to FPGA by some extension A/D converters;Meanwhile, power supply interface is by mould of powering
Block is powered with A/D converter for some extensions.
Preferably, the embedded RS232 electrical level transferring chips of described configuration cable;When FPGA is by the mutual of DB9 plug connectors
When the communication with PC is realized in connection, power supply interface is powered to RS232 electrical level transferring chips by supply module.
Preferably, AD7980 of the modulus conversion chip of described A/D converter for Analog Devices companies.Which is most
High sampling rate is 1MSPS, supports SPI interface agreement.In the present invention, the circuit of FPGA controls A/D samplings is exactly to utilize SPI interface
Realize.
Preferably, described FLASH memory chip is the 39VF1601 of SST companies production.Its capacity be 16Mbit, and
Only need the 3.3V voltages just being capable of normal work.User only needs to control write enable signal, chip selection signal and output enable signal three
Holding wire, just can complete the operation for writing or wiping FLASH data.Before 16bit data are write to FLASH, it is necessary to
Three data of the write of order in specified address.Equally, before the data in erasing FLASH, it is also necessary to specified
Six data are sequentially written in address, to prevent deletion action by mistake.
Preferably, the B2B connectors also include that ppu interface, the FPGA connect ppu interface.
So FPGA possesses the ability for carrying out data exchange with outside embedded system.Reserve this ppu interface purpose be
It is easy to Function Extension in the future and is communicated with ppu, so other processors can enters to the output signal of this device
Row is further to be processed.
The invention has the advantages that:
Assembly of the invention can be directed to different operating modes, by the communication with PC, can realize setting different parameters
Put, i.e., parameter can configure.The parameter that so only can be realized as carrying out underwater sound signal for different operating modes using a set of equipment is estimated
Meter.Simultaneously the present invention need not re-design PCB for different operating modes, without carrying out accordingly according to selected hardware
The problem of the detail programming of language.I.e. present invention achieves modularity, convenient dismounting;Without making sheet again.
The present invention possesses to be carried out the detection of multichannel pure-tone pulse signal parallel under underwater sound multi_path channel transmission conditions and joins
The function that number is estimated, the ability with good anti-passage string leakage and Multi-path interference.Signal processing algorithm is completed by FPGA, FPGA
Using the advantage of hardware concurrent, fine granularity, the operating structure of highly-parallel can be realized in piece.So, permit in FPGA resource
Perhaps on the premise of, the present invention can make full use of pipeline organization, can process multiple signals simultaneously, and data throughout is high, place
Reason speed is fast.Signal processing of the present invention includes Noise Estimation, direct current biasing estimation, Notch filtering, envelope detected, parameter
Estimate and VIFD strings leak suppression etc., its result for exporting includes:Noise background, direct current biasing, effective impulse quantity, side
Difference, pulsewidth, amplitude and time delay value etc..Detected using the present invention, the minimum symbol-spaced of detection is 200ms, maximum symbol
Width is 100ms;When sample rate is 100kSPS, the upper limit quantity for the treatment of channel is 20, when sample rate is 1MSPS, place
The upper limit quantity of reason passage is 2.
Description of the drawings
Fig. 1 is assembly of the invention schematic diagram;
Fig. 2 is the schematic diagram of system in FPGA of the present invention.
Specific embodiment
Specific embodiment one:In conjunction with Fig. 1 and Fig. 2 explanation present embodiments,
The device of pure-tone pulse detection and parameter estimation in a kind of underwater acoustic channel based on FPGA, including:FPGA(Field-
Programmable Gate Array, field programmable gate array) 1,8 groups of A/D converter (Analog to Digital
Converter, analog-digital converter) 2, B2B connectors 6, E2Prom memory (Electrically Erasable
Programmable Read-Only Memory, band EEPROM (Electrically Erasable Programmable Read Only Memo)) 3, supply module 4, FLASH deposits
Reservoir 5, DB9 plug connectors (D type data interface connectors) 9;
B2B connectors 6 include I/O input/output interfaces 610, A/D Sampling Interfaces 602, power supply interface 604;
A/D Sampling Interfaces 602 are connected to FPGA1 by 8 groups of A/D converters 2 respectively;
FLASH memory 5 is connected to FPGA1, stores for parameter;
E2Prom memory 3 is connected to FPGA1, for program storage;
PC 7 connects DB9 plug connectors 9 by configuring cable 8, and FPGA1 is also connected with DB9 plug connectors 9;FPGA1 passes through DB9
Being connected with each other for plug connector, realizes the communication with PC 7;
I/O input/output interfaces 610 are connected to FPGA1 by I/O protection circuit for input and output 10;
Power supply interface 604 is connected respectively to FPGA1,8 groups of A/D converters 2, E by supply module 42Prom memory 3,
FLASH memory 5 and DB9 plug connectors 9, respectively FPGA1,8 groups of A/D converters 2, E2PROM3, FLASH memory 5 are powered;
Described FPGA1 is used for the parameter estimation that pure-tone pulse in underwater acoustic channel detects sum;Including
Initialization unit, for the Initialize installation of system, it is ensured that state of the system in energy normal work;
Communication control unit, for carrying out data exchange with PC or ppu, specifically includes:Parsing PC leads to
The instruction that serial ports is assigned is crossed, control FLASH read-write cells, A/D acquisition control units and signal processing unit are single to I/O controls
Unit carries out parameter setting, analog digital conversion, data and calculates and store, and parameter estimation result is encoded and is returned and carry out frame
The detection and forwarding of signal;
A/D acquisition control units;For sending A/D work clocks and frame signal, the output number of each road A/D converter is received
According to, and each circuit-switched data is respectively written into the sampled data buffer area in this unit in case signal processing unit is used;A/D collection controls
Unit processed is managed by communication control unit, can change acquisition channel quantity and sample rate, can be separately provided each A/D passages
Running parameter;
FLASH read-write cells;For storing the parameter configuration that PC is assigned, mainly include:Sample rate, A/D passages
And corresponding sense channel quantity, preset signal feature and detection threshold value;
Signal processing unit, the detection and parameter estimation for underwater sound signal;
Whether I/O control units, have frame signal for real-time detection, and forward frame signal when needed.
The present invention possesses to be carried out the detection of multichannel pure-tone pulse signal parallel under underwater sound multi_path channel transmission conditions and joins
The function that number is estimated, the ability with good anti-passage string leakage and Multi-path interference.Signal processing algorithm therein is complete by FPGA
Into, on the premise of FPGA resource is allowed, the present invention makes full use of pipeline organization, can process multiple signals, data simultaneously
Handling capacity is high, and processing speed is fast.The disposal ability for being possessed is:Can detection minimum symbol-spaced be 200ms, maximum symbol width
Spend for 100ms;Using front needing to carry out initial configuration in advance, i.e., running parameter is set using the special interface of PC, such as:Adopt
Sample rate, A/D passages and corresponding sense channel quantity, preset signal feature and detection threshold value, wherein preset signal characteristic are joined
Number includes:The mid frequency of signal to be detected, signal bandwidth;Preset detection threshold value includes:Frequency difference thresholding, variance thresholding, width
Degree thresholding and width threshold.Then being configured cable 8 will need preset running parameter to be sent to FPGA1, by FPGA1 by work
In parameter read-in FLASH memory 5;The working procedure of device is stored in E2In prom memory 3, setting rear the system can
To depart from PC work.During normal work, FPGA1 programs read the running parameter in FLASH memory 5 in initial phase,
As FPGA1 resource allocations and the foundation of signal processing.Sample rate is arranged according to signal frequency to be detected and species and A/D turns
2 number of channels of parallel operation, selectable sample rate are 100kSPS, 400kSPS and 1MSPS, corresponding A/D2 and sense channel quantity
Respectively 20,8 and 2;Corresponding A/D converter 2 carries out analog digital conversion under the sequencing contro of FPGA..Numbers of the FPGA to input
Word signal carries out the digital filtering of multidiameter delay, envelope detection and the wide device cascading judgement of mirror, the detection of instantaneous frequency variance and parameter
Estimate, and output result is transmitted by RS232 serial ports with certain coded format, when the signal detection of a cycle is completed
Afterwards, in the initial period transmission signal processing results in next cycle, data encoding is carried out according to the quantity of preset treatment channel,
Channel number, result data, parity check bit is followed successively by, is sent with RS232 serial modes.Serial ports outfan is connected to respectively
B2B connectors 6 and DB9 connectors 9, when result needs to send to the processors such as DSP or ARM, can through B2B connectors 6
Direction communication;If result needs to send to PC, by DB9 connectors 9, it is configured cable 8 and communicates with PC, configures
Electrical level transferring chip is designed with cable 8, the chip is powered through DB9 connectors 9 by module;Work between multidiameter delay passage
Separate, the initial time benchmark of signal is determined that by the lock-out pulse being input into other running parameters can be separately provided.
Module of the present invention directly can be assigned in other job platforms based on modular design philosophy, fitted with good
Ying Xing.The B2B connectors 6 of module configuration, for power, extend A/D2 interfaces and data exchange, can directly assign into other and put down
On platform, the connection of outfan and result receiving terminal with receiver is realized by the line on other platforms respectively.Power supply
Input voltage range is:5V~14V, is furnished with DC-DC converter in module, complete the supply voltage to each several part in module and turn
Change.
Specific embodiment two:
Signal processing unit described in present embodiment carries out the detection of underwater sound signal and parameter estimation procedure includes following step
Suddenly:
Signal processing unit receives the pulse signal (containing noisy digital signal) of A/D converter output, and pulse is believed
Number pointwise carries out Notch Filtering Processing, and pulse signals carry out Noise Estimation, direct current biasing and estimate simultaneously;
Pulse signal after Notch Filtering Processing is carried out taking envelope processing, and calculates instantaneous frequency variance, while calculating
The amplitude threshold of pulse signal;
To taking effective impulse quantity, pulsewidth, time delay, instantaneous phase, weights and the envelope of the pulse signal after envelope processing
Row is estimated, while envelope detector and the wide device cascading judgement of mirror is carried out, when pulse signal envelope forward position begins to exceed amplitude threshold,
And continuous sampling point exceedes amplitude threshold (exceedes width according to how many continuous sampled point depending on actual RST simultaneously
Degree thresholding), pulse signal envelope tailing edge is less than amplitude threshold, and the instantaneous frequency of pulse signal in certain sampling timeframe
Less than the instantaneous frequency variance threshold value for setting, rate variance then judges that this signal is effective underwater sound simple signal;Wherein envelope
Forward position respective amplitude is forward position energy threshold, and tailing edge respective amplitude is referred to as tailing edge energy measuring thresholding, and continuous sampling point number is
The wide device width threshold of mirror.
Other structures and parameter are identical with specific embodiment one.
Specific embodiment three:
Signal processing unit described in present embodiment is the instantaneous frequency for calculating pulse signal by the way of sliding window
Variance.As the instantaneous frequency variance of pulse signal is less, and the variance of noise and string leakage is larger, therefore by signal calculated
Instantaneous frequency variance, aids in envelope detector and the wide device of inspection to carry out signal detection.
Other structures and parameter are identical with specific embodiment one or two.
Specific embodiment four:
The estimation of Noise Estimation and direct current biasing described in present embodiment adopts first order recursive algorithm.
One of other structures and parameter and specific embodiment one to three are identical.
Specific embodiment five:
Notch filtering described in present embodiment is carried out using LMS algorithm iteration.
Notch filtering carries out pointwise digital filtering using certain adaptive algorithm pulse signals, to adopting LMS algorithm
Notch filterings for, it is necessary first to prestore two orthogonal reference signals, sets up two variables to store weights, its
The secondary step-length for also needing to determine a calculating;Whole filtering is carried out in the case where the iterative formula of LMS algorithm is instructed, wave filter
Output reaches stable (whole estimation procedure must can be only achieved stable state through one section of learning time) after a period of time has passed;Filtering
While, using the envelope of two weight computing signals being continually changing.
One of other structures and parameter and specific embodiment one to four are identical.
Specific embodiment six:
Present embodiment described device on the basis of 8 groups of A/D converters are provided with are additionally provided with some extension A/D and turn
Parallel operation 12;The B2B connectors 6 are additionally provided with some extension A/D Sampling Interfaces on the basis of A/D Sampling Interfaces 602 are provided with
612;Described some extension A/D Sampling Interfaces 612 are connected to FPGA1 by some extension A/D converters 12;Meanwhile, supply
Electrical interface is powered for some extension A/D converters 12 by supply module 4.
One of other structures and parameter and specific embodiment one to five are identical.
Specific embodiment seven:
Configuration cable 8 described in present embodiment embeds RS232 electrical level transferring chips 11;When FPGA1 passes through DB9 plug connectors
9 when being connected with each other the communication that realizes with PC 7, power supply interface 604 is by supply module 4 to RS232 electrical level transferring chips 11
Power supply.
One of other structures and parameter and specific embodiment one to six are identical.
Specific embodiment eight:
AD7980 of the modulus conversion chip of the A/D converter 2 described in present embodiment for Analog Devices companies.
Its highest sample rate is 1MSPS, supports SPI interface agreement.In the present invention, the circuit of FPGA controls A/D samplings is exactly to utilize SPI
Interface is realized.
One of other structures and parameter and specific embodiment one to seven are identical.
Specific embodiment nine:
5 chip of FLASH memory described in present embodiment is the 39VF1601 of SST companies production.Its capacity is
16Mbit, and only need the 3.3V voltages just being capable of normal work.User only needs to control write enable signal, chip selection signal and output enable
Three holding wires of signal, just can complete the operation for writing or wiping FLASH data.To FLASH write 16bit data it
Before, it is necessary to three data of the write of order in specified address.Equally, before the data in erasing FLASH, it is also necessary to
Six data of the write of order in the address that specifies, to prevent deletion action by mistake.
One of other structures and parameter and specific embodiment one to eight are identical.
Specific embodiment ten:
B2B connectors 6 described in present embodiment also include that ppu interface 601, the FPGA1 connect external treatment
Device interface 601.So FPGA1 possesses the ability for carrying out data exchange with outside embedded system, will such as by way of bus
Data pass to arm processor, or data are passed to DSP by McBSP interfaces.Reserve the purpose of this ppu interface
It is easy for Function Extension in the future and is communicated with ppu, so other processors can be to the output signal of this device
It is further processed.
Result has two kinds of flow directions.If necessary to data are uploaded to PC, then DB9 connectors are accessed, FPGA passes through
Data are passed to PC by configuration cable;If data will pass to other processors, by B2B connectors " with external treatment
Device interface " is carried out, but is also carried out data transmission with the agreement of serial communication, i.e. data output routine inside FPGA is same
Set program, is all 232 serial port logics.
One of other structures and parameter and specific embodiment one to nine are identical.
Claims (10)
1. in a kind of underwater acoustic channel based on FPGA, pure-tone pulse detects the device with parameter estimation, it is characterised in that include:
FPGA (1), 8 groups of A/D converters (2), B2B connectors (6), E2Prom memory (3), supply module (4), FLASH memory
(5), DB9 plug connectors (9);
B2B connectors (6) include I/O input/output interfaces (610), A/D Sampling Interfaces (602), power supply interface (604),
A/D Sampling Interfaces (602) are connected to FPGA (1) by 8 groups of A/D converters (2) respectively;
FLASH memory (5) is connected to FPGA (1), stores for parameter;
E2Prom memory (3) is connected to FPGA (1), for program storage;
PC (7) connects DB9 plug connectors (9) by configuring cable (8), and FPGA (1) is also connected with DB9 plug connectors (9);FPGA
(1) being connected with each other by DB9 plug connectors, realizes the communication with PC (7);
I/O input/output interfaces (610) are connected to FPGA (1) by I/O protection circuit for input and output (10);
Power supply interface (604) is connected respectively to FPGA (1), 8 groups of A/D converters (2), E by supply module (4)2Prom memory
(3), FLASH memory (5) and DB9 plug connectors (9), respectively FPGA (1), 8 groups of A/D converters (2), E2PROM(3)、
FLASH memory (5) is powered;
Described FPGA (1) is used for the parameter estimation that pure-tone pulse in underwater acoustic channel detects sum;Including
Initialization unit, for the Initialize installation of system, it is ensured that state of the system in energy normal work;
Communication control unit, for carrying out data exchange with PC or ppu, specifically includes:Parsing PC is by string
The instruction that mouth is assigned, control FLASH read-write cells, A/D acquisition control units and signal processing unit, enters to I/O control units
Line parameter setting, analog digital conversion, data are calculated and are stored, and parameter estimation result is encoded and is returned and carry out frame signal
Detection and forwarding;
A/D acquisition control units, for sending A/D work clocks and frame signal, receive the output data of each road A/D converter,
And each circuit-switched data is respectively written in this unit in case signal processing unit is used;A/D acquisition control units receive Control on Communication list
The management of unit, can change acquisition channel quantity and sample rate, can be separately provided the running parameter of each A/D passages;
FLASH read-write cells, for storing the parameter configuration that PC is assigned, mainly include:Sample rate, A/D passages and right
The sense channel quantity that answers, preset signal feature and detection threshold value;
Signal processing unit, the detection and parameter estimation for underwater sound signal;
Whether I/O control units, have frame signal for real-time detection, and forward frame signal.
2. in a kind of underwater acoustic channel based on FPGA according to claim 1, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that signal processing unit carries out the detection of underwater sound signal and parameter estimation procedure is comprised the following steps:
Signal processing unit receives the pulse signal of A/D converter output, and pulse signals pointwise carries out Notch Filtering Processing,
And pulse signals carry out Noise Estimation, direct current biasing estimation simultaneously;
Pulse signal after Notch Filtering Processing is carried out taking envelope processing, and calculates instantaneous frequency variance, while calculating pulse
The amplitude threshold of signal;
The effective impulse quantity, pulsewidth, time delay, instantaneous phase, weights and the envelope row that take the pulse signal after envelope processing are estimated
Meter, while carrying out envelope detector and the wide device cascading judgement of mirror, when pulse signal envelope forward position begins to exceed amplitude threshold, and connects
Continuous sampled point exceedes amplitude threshold simultaneously, and pulse signal envelope tailing edge is less than amplitude threshold, and the instantaneous frequency of pulse signal
Less than the instantaneous frequency variance threshold value for setting, variance then judges that this signal is effective underwater sound simple signal;Wherein before envelope
It is forward position energy threshold along respective amplitude, tailing edge respective amplitude referred to as tailing edge energy measuring thresholding, continuous sampling point number are mirror
Wide device width threshold.
3. in a kind of underwater acoustic channel based on FPGA according to claim 2, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that described signal processing unit is the instantaneous frequency variance for calculating pulse signal by the way of sliding window
's.
4. in a kind of underwater acoustic channel based on FPGA according to claim 3, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that the estimation of described Noise Estimation and direct current biasing adopts first order recursive algorithm.
5. in a kind of underwater acoustic channel based on FPGA according to claim 4, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that described Notch filtering is carried out using LMS algorithm iteration.
6. in a kind of underwater acoustic channel based on FPGA according to one of claim 1 to 5, pure-tone pulse detection and parameter are estimated
The device of meter, it is characterised in that described device is additionally provided with some extension A/D on the basis of 8 groups of A/D converters are provided with
Transducer (12);B2B connectors (6) are additionally provided with some extension A/D on the basis of A/D Sampling Interfaces (602) are provided with
Sampling Interface (612);Described some extension A/D Sampling Interfaces (612) are connected to by some extension A/D converter (12)
FPGA(1);Meanwhile, power supply interface is powered for described some extension A/D converter (12) by supply module (4).
7. in a kind of underwater acoustic channel based on FPGA according to claim 6, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that embedded RS232 electrical level transferring chips (11) of described configuration cable (8);When FPGA (1) passes through DB9 grafting
When being connected with each other the communication that realizes with PC (7) of part (9), power supply interface (604) is by supply module (4) to RS232 level
Conversion chip (11) is powered.
8. in a kind of underwater acoustic channel based on FPGA according to claim 1, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that AD7980 of the modulus conversion chip of described A/D converter (2) for Analog Devices companies.
9. in a kind of underwater acoustic channel based on FPGA according to claim 1, pure-tone pulse detects the dress with parameter estimation
Put, it is characterised in that described FLASH memory (5) chip is the 39VF1601 of SST companies production.
10. in a kind of underwater acoustic channel based on FPGA according to right wants 1, pure-tone pulse detects the device with parameter estimation,
Characterized in that, B2B connectors (6) also include that ppu interface (601), described FPGA (1) connect external treatment
Device interface (601).
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