CN210836065U - Underwater acoustic signal processing device based on multi-core parallel high-speed platform - Google Patents
Underwater acoustic signal processing device based on multi-core parallel high-speed platform Download PDFInfo
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- CN210836065U CN210836065U CN201920788443.XU CN201920788443U CN210836065U CN 210836065 U CN210836065 U CN 210836065U CN 201920788443 U CN201920788443 U CN 201920788443U CN 210836065 U CN210836065 U CN 210836065U
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Abstract
The utility model relates to an underwater acoustic signal processing device based on parallel high-speed platform of multicore, the device includes: the system comprises a multi-channel synchronous SAR high-speed AD acquisition circuit, a multi-channel DA waveform generator, a processing unit, a data storage unit and a power circuit for providing power for the underwater acoustic signal processing device; the processing unit comprises an FPGA bottom layer logic control module, an SOPC ARM controller and a DSP computing unit, wherein the SOPC ARM controller and the DSP computing unit are respectively connected with the processing unit; the multichannel synchronous SAR high-speed AD acquisition circuit, the multichannel DA waveform generator and the data storage unit are respectively connected with the FPGA bottom layer logic control module. The utility model discloses the device adopts the SOPC FPGA of high integration and multicore DSP's framework, breaks traditional computer framework and specially for the customization of underwater acoustic signal processing platform, makes all functional unit of entire system integrated to single circuit board, has the characteristics that the integrated level is high.
Description
Technical Field
The utility model belongs to the technical field of electron, especially an underwater acoustic signal processing apparatus based on parallel high-speed platform of multicore.
Background
The underwater acoustic signal processing system is widely applied to military or civil fields such as underwater weapons, underwater exploration, ocean engineering and the like. The core technology is that underwater weak characteristic underwater acoustic signals received by an underwater transducer are amplified, filtered and digitized, and then are processed by an algorithm to identify position or motion information of a target, such as the azimuth, distance, depth, navigation speed and the like. The transducer array is required to generate a driving waveform, and characteristics such as frequency spectrum, amplitude, phase and the like of a multi-channel underwater sound signal induced by a reflected wave are scientifically calculated and analyzed. With the increasingly stringent and detailed requirements of weapon systems and underwater detection systems on the identification of objects or environments nowadays, increasingly higher requirements are also put on the performance of underwater acoustic signal processing machines. The improved channel number, the higher sampling rate, the faster data calculation and processing capability, the faster data transmission bandwidth, the more sufficient storage and recording space, the smaller size and the lower power consumption are targets that engineers in the industry continuously pursue.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an underwater acoustic signal processing apparatus based on parallel high-speed platform of multicore.
The utility model provides a technical scheme of above-mentioned problem does: an underwater acoustic signal processing device based on a multi-core parallel high-speed platform comprises:
the system comprises a multi-channel synchronous SAR high-speed AD acquisition circuit, a multi-channel DA waveform generator, a processing unit, a data storage unit and a power circuit for providing power for the underwater acoustic signal processing device;
the processing unit comprises an FPGA bottom layer logic control module, an SOPC ARM controller and a DSP computing unit, wherein the SOPC ARM controller and the DSP computing unit are respectively connected with the FPGA bottom layer logic control module;
the multichannel synchronous SAR high-speed AD acquisition circuit, the multichannel DA waveform generator and the data storage unit are respectively connected with an FPGA bottom layer logic control module in the processing unit.
According to the scheme, the processing unit adopts a lossless data chain among the multi-core processors to provide a data communication channel.
According to the scheme, the DSP computing unit comprises a master DSP computing unit and a slave DSP computing unit, and the master DSP computing unit performs data interaction with the slave DSP computing unit through a HyperLink high-speed serial bus.
According to the scheme, the DSP computing unit is connected with the FPGA bottom layer logic control module through the high-speed PCIE bus.
According to the scheme, the master DSP computing unit and the slave DSP computing unit are 8-core DSP computing units.
According to the scheme, the underwater acoustic signal processing device further comprises an RS232 interface for exchanging information with the course control system.
According to the scheme, the multi-channel synchronous SAR high-speed AD acquisition circuit is used for acquiring analog waveforms from low-noise amplification filter circuits of channels at the front end of the transducer array.
According to the scheme, the multichannel DA waveform generator is a sinusoidal signal generating circuit used for generating transmitting waveforms for the transducer.
The working principle of the device is as follows: the utility model discloses in the device, the high-speed AD acquisition circuit of synchronous SAR of FPGA bottom logic PL control multichannel gathers the analog waveform that comes from each passageway low noise amplification filter circuit of front end and delays it in the RAM in PL. These data will be mapped in real time by the DMA controller within the PL into the SOPC ARM controller peripheral DDR cache. And the SOPC ARM controller is responsible for transmitting data in the DDR to the main computing unit through the high-speed PCIE bus. And the master DSP computing unit performs data interaction with the slave DSP computing unit through a HyperLink high-speed serial bus. And the data and parameters processed by the master DSP and the slave DSP are mapped to the peripheral DDR of the SOPC ARM controller through the high-speed PCIE bus. The SOPC ARM controller stores the data into a large-capacity data storage unit or transmits the data to other terminals by using a gigabit network for simulation or read-back.
The utility model discloses the beneficial effect that the device brought is:
1. the traditional technology is composed of a multipurpose computer board card and various functional board card structures. Such computer systems are costly, bulky, and consume significant power. The design adopts a high-integration SOPC FPGA and multi-core DSP architecture, breaks through the traditional computer architecture and is specially customized for an underwater sound signal processing platform, so that all functional units of the whole system are integrated into a single circuit board.
2. The utility model discloses a8 nuclear DSPs of principal and subordinate's formula have greatly promoted signal processor's digital processing ability, can adopt more huge calculated amount, can let 16 DSP nuclear parallel computation signal characteristics.
Drawings
Fig. 1 is a schematic structural diagram of an apparatus according to an embodiment of the present invention;
fig. 2 is a sample photograph of a device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
As shown in fig. 1, an underwater acoustic signal processing apparatus for a multi-core parallel high-speed platform includes: the system comprises a multi-channel synchronous SAR high-speed AD acquisition circuit, a multi-channel DA waveform generator, an FPGA bottom layer logic control module, an SOPC ARM controller, a multi-core DSP computing unit, a large-capacity data storage unit and a power circuit;
the multi-channel synchronous SAR high-speed AD acquisition circuit is an AD acquisition circuit with 16 channels, 200KPS sampling rate and 16-bit precision; the multi-channel DA waveform generator is a sinusoidal signal generating circuit with a 6-way 1M update rate.
The FPGA bottom layer logic control module, the SOPC ARM controller and the multi-core DSP computing unit form a processing unit together;
the FPGA bottom layer logic control module is provided with bottom layer logic for high-speed parallel control of AD, DA, FLASH array and high-speed data link.
The SOPC ARM controller has the control functions of gigabit network ports, high-speed data chains and application software stored in data disks.
The multi-core DSP computing unit is provided with two 8-core DSP platforms and a high-speed data cache, and can complete functions of underwater sound signal digital signal processing, target position or motion information identification, navigation instruction indication, high-speed data link control and the like according to a built-in algorithm or control instruction.
In the embodiment, a lossless data chain is adopted to process underwater acoustic audio signals, and the lossless data chain among multi-core processors is used for providing a function of a high-speed data communication channel for two 8-core DSPs, a dual-core SOPC A8 ARM processor, an FPGA PL (programmable logic) and a DDR cache in the device.
The high-capacity data storage unit in this embodiment adopts a bottom-layer FLASH medium, which is a non-SATA hard disk or an eMMC type storage medium, and has a 1Tb high-capacity storage capacity and a 50MB/S storage bandwidth, and performs parallel control on the memory basic unit NAND FLASH arrays one by one.
The power supply circuit has the function of providing diversified direct current power supplies for the multi-core processor, and has the characteristics of high efficiency and low ripple.
The utility model discloses the working method of device: the FPGA bottom layer logic PL controls the multi-channel synchronous SAR high-speed AD acquisition circuit to acquire analog waveforms from low-noise amplification filter circuits of all channels at the front end and digitally buffer the analog waveforms in the RAM in the PL. These data will be mapped in real time by the DMA controller within the PL into the SOPC ARM controller peripheral DDR. And the SOPC ARM controller is responsible for transmitting data in the DDR to the main computing unit through the high-speed PCIE bus. And the master DSP computing unit performs data interaction with the slave DSP computing unit through a HyperLink high-speed serial bus. And the data and parameters processed by the master DSP and the slave DSP are mapped to the peripheral DDR of the SOPC ARM controller through the high-speed PCIE bus. The SOPC ARM controller stores the data into a large-capacity data storage unit or transmits the data to other terminals by using a gigabit network for simulation or read-back. And in each calculation, the main DSP calculation unit adjusts the required course instruction in real time through calculating the sampling data of each period and sends the required course instruction to the control system through an RS232 interface. And parameters of a transmitting waveform are given to the FPGA PL through the PCIE bus so that the PL can control the multichannel DA to generate the transmitting waveform with required frequency, amplitude and phase to the transducer.
Fig. 2 is a prototype produced according to the inventive solution, in which: the system comprises a 1-FPGA SOPC platform (PL + ARM), a 2-large-capacity data storage unit, a 3-multichannel synchronous SAR high-speed AD acquisition circuit, a 4-master multi-core DSP calculation unit, a 5-slave multi-core DSP calculation unit, a 6-multichannel DA waveform generator and a 7-power circuit.
Claims (8)
1. An underwater acoustic signal processing device based on a multi-core parallel high-speed platform is characterized by comprising:
the system comprises a multi-channel synchronous SAR high-speed AD acquisition circuit, a multi-channel DA waveform generator, a processing unit, a data storage unit and a power circuit for providing power for the underwater acoustic signal processing device;
the processing unit comprises an FPGA bottom layer logic control module, an SOPC ARM controller and a DSP computing unit, wherein the SOPC ARM controller and the DSP computing unit are respectively connected with the FPGA bottom layer logic control module;
the multichannel synchronous SAR high-speed AD acquisition circuit, the multichannel DA waveform generator and the data storage unit are respectively connected with the processing unit.
2. The underwater acoustic signal processing device based on the multi-core parallel high-speed platform according to claim 1, wherein a data communication channel is provided in the processing unit by adopting a lossless data chain among multi-core processors.
3. The underwater acoustic signal processing device based on the multi-core parallel high-speed platform according to claim 1, wherein the DSP computing unit comprises a master DSP computing unit and a slave DSP computing unit, and the master DSP computing unit performs data interaction with the slave DSP computing unit through a HyperLink high-speed serial bus.
4. The underwater acoustic signal processing device based on the multi-core parallel high-speed platform according to claim 3, wherein the master DSP computing unit and the slave DSP computing unit are 8-core DSP computing units.
5. The underwater acoustic signal processing device based on the multi-core parallel high-speed platform according to claim 1, wherein the DSP computing unit is connected to the FPGA bottom layer logic control module through a high-speed PCIE bus.
6. The underwater acoustic signal processing device based on the multi-core parallel high-speed platform as claimed in claim 1, further comprising an RS232 interface for exchanging information with a heading control system.
7. The underwater acoustic signal processing device based on the multi-core parallel high-speed platform according to claim 1, wherein the multi-channel synchronous SAR high-speed AD acquisition circuit is a multi-channel synchronous SAR high-speed AD acquisition circuit for acquiring analog waveforms from each channel low-noise amplification filter circuit at the front end of the transducer array.
8. The multi-core parallel high-speed platform-based underwater acoustic signal processing device according to claim 1, wherein the multi-channel DA waveform generator is a sinusoidal signal generating circuit for generating transmit waveforms for the transducers.
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| CN201920788443.XU CN210836065U (en) | 2019-05-28 | 2019-05-28 | Underwater acoustic signal processing device based on multi-core parallel high-speed platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114895459A (en) * | 2022-05-17 | 2022-08-12 | 中国科学院光电技术研究所 | Real-time controller for adaptive optical wavefront on surface layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114895459A (en) * | 2022-05-17 | 2022-08-12 | 中国科学院光电技术研究所 | Real-time controller for adaptive optical wavefront on surface layer |
| CN114895459B (en) * | 2022-05-17 | 2023-10-03 | 中国科学院光电技术研究所 | Surface layer self-adaptive optical wavefront real-time controller |
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Denomination of utility model: A Underwater Acoustic Signal Processing Device Based on Multi Core Parallel High Speed Platform Granted publication date: 20200623 Pledgee: Wuhan Financing Guarantee Co.,Ltd. Pledgor: WUHAN HUANDA ELECTRONIC&ELECTRIC CO.,LTD. Registration number: Y2024980010227 |