CN106449412A - Technological method for switch N type LDMOS device - Google Patents

Technological method for switch N type LDMOS device Download PDF

Info

Publication number
CN106449412A
CN106449412A CN201610876652.0A CN201610876652A CN106449412A CN 106449412 A CN106449412 A CN 106449412A CN 201610876652 A CN201610876652 A CN 201610876652A CN 106449412 A CN106449412 A CN 106449412A
Authority
CN
China
Prior art keywords
type
district
ion implanting
sti
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610876652.0A
Other languages
Chinese (zh)
Inventor
杨新杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201610876652.0A priority Critical patent/CN106449412A/en
Publication of CN106449412A publication Critical patent/CN106449412A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a technological method for a switching N type LDMOS device. The technological method comprises the steps of performing ion injection to form an N type embedded layer and a P type embedded layer; forming a P type epitaxial layer, and then performing N type deep well injection and thermal propulsion; performing photoetching and etching to form a second STI; performing P type ion injection for one time; performing photoetching and etching to form a first STI, and carrying out STI appearance optimization; forming an N well and a P well; forming an N type drift region; forming a gate oxide layer and a polysilicon layer; forming a P type body region through injection; forming a polysilicon gate electrode; forming a side wall; performing photoetching defining and ion injection to form a heavily-doped N type region and a heavily-doped P type region; carrying out quick thermal annealing; and forming a cobalt silicide and depositing interlayer dielectric. According to the technological method provided by the invention, a step of low-energy P type injection is added after the second STI etching and forming, and the doping of the drift region is changed into non-uniform doping by matching with photoetching defining and ion injection of the N type drift region; and therefore, it is more convenient to adjust Rds and BV, and separate regulation on two times of injection can be carried out.

Description

The process of switch N-type LDMOS device
Technical field
The present invention relates to field of manufacturing semiconductor devices, particularly relate to a kind of process switching N-type LDMOS device.
Background technology
In 0.18 μm of BCD technique, switch the structure of N-type LDMOS device as it is shown in figure 1, STI 1 is conventional in figure Isolation channel is (such as the degree of depth), STI2 is (such as thickness) it is the isolation channel more shallow than SIT1, it is only used in switch N-type LDMOS, Because shallow, the isolation doing routine is unsatisfactory for demand.
The manufacturing process of switch N-type LDMOS device comprises these steps at present：
The injection of 1.N type buried regions 1 and propelling；
The injection of 2.P type buried regions 3 and pick into；
3.P type epitaxial layer 2 is formed；
4.N moldeed depth trap 4 injects and advances, STI2 (the 2nd STI) photoetching and etching, the photoetching of STI 1 (STI) and quarter Erosion；
The photoetching of 5.N trap (NW) 5 and p-well (PW) and injection；
The photoetching of 6.N type drift region 6 (NF) and injection；
7. gate oxide is formed and grid polycrystalline silicon is formed；
8.P Xing Ti district's photoetching and etching, ion implanting；
9. gate lithography and etching；Form side wall；
10. the formation in heavily doped N-type district and injection；The formation in heavily doped P-type district and injection；
11. rapid thermal annealings activate；
12. cobalt silicides are formed；Deposit inter-level dielectric.
Above-mentioned manufacturing process has a problem in that：As shown in fig. 1, DA district (be under grid STI2 edge to N-type drift region Length), PF (P drift district, PF in figure), the mixing of PA region (being gate edge to the region between drain region in N-type drift region) Miscellaneous distribution is to be determined by the injection of N-type drift region；The dopant profiles in 2.P type drift region/PA region is identical, if PF/PA district The doping in territory is too light, then source and drain conducting resistance Rds can be caused bigger, if the doping in PF/PA region is too dense, then can cause again hitting Wear voltage to reduce.
Content of the invention
The technical problem to be solved is to provide the process of described switch N-type LDMOS device.
For solving the problems referred to above, a kind of process switching N-type LDMOS device of the present invention, it is characterised in that： Comprise following processing step：
1st step, ion implanting forms n type buried layer, and carry out picking into；
2nd step, ion implanting forms p type buried layer, and carry out picking into；
3rd step, p-type epitaxial layer is formed, then carry out the injection of N-type deep trap and pick into；
4th step, photoetching and etching form the 2nd STI；
5th step, carries out a p-type ion implanting；
6th step, photoetching and etching form a STI, the formation of thermal oxide layer；
7th step, lithographic definition and ion implanting form N trap；
8th step, lithographic definition and ion implanting form p-well；
9th step, lithographic definition and ion implanting form N-type drift region；N-type drift region and the active area by source region are without handing over Connect；
10th step, gate oxide is formed and polysilicon layer is formed；
11st step, lithographic definition and ion implanting form PXing Ti district；
12nd step, photoetching and etching form polysilicon gate；
13rd step, forms side wall；
14th step, lithographic definition and ion implanting form heavily doped N-type district；
15th step, lithographic definition and ion implanting form heavily doped P-type district；
16th step, rapid thermal annealing；
17th step, cobalt silicide is formed, and deposits inter-level dielectric.
Further, the 2nd STI that described 4th step is formed, the STI that its degree of depth is formed less than follow-up 6th step.
Further, the Implantation Energy of described 5th step is based on the 6th follow-up step oxidate temperature and determines, ion is noted DA/PF/PA region can be diffused under the effect of follow-up thermal oxide layer after entering；The dosage injecting is the characteristic need according to device Ask and adjust.
Further, described 9th step, injecting of N-type drift region territory needs to ensure with the active area by source region without handing-over do not have Have DA region, simultaneously PF area reduction.
The process of switch N-type LDMOS device of the present invention, increases by a step after the 2nd STI etching is formed Low-energy p-type is injected, and drift region doping is become non-uniform doping, and the drift region concentration that N-type drift region is not injected into is little, The drift region concentration having N-type to inject is big, and highfield appears in the bottom (near drain terminal) of the 2nd STI；Adjust Rds and adjustment BV is convenient, can two inject separate regulation, be independent of each other.
Brief description
Fig. 1 is the structural representation of switch N-type LDMOS device.
Fig. 2 is the Electric Field Distribution schematic diagram of the different implantation dosage in N-type drift region territory.
Fig. 3 is present invention process flow chart.
Description of reference numerals
1 is n type buried layer, and 2 is p-type extension, and 3 is p type buried layer, and 4 is N-type deep trap, and 5 is N trap, and 6 is N-type drift region (NF), 7 ShiPXing Ti district.
Detailed description of the invention
The process of switch N-type LDMOS device of the present invention, comprises following processing step：
1st step, ion implanting forms n type buried layer, and carry out picking into.
2nd step, ion implanting forms p type buried layer, and carry out picking into.
3rd step, p-type epitaxial layer is formed, then carry out the injection of N-type deep trap and pick into.
4th step, photoetching and etching form the 2nd STI.The degree of depth of the 2nd STI is less than subsequent step to form first The degree of depth of STI.2nd STI is also only technique required for N-type LDMOS device for the switch.
5th step, carries out a p-type ion implanting.The energy injecting is low-yield injection, picks into temperature according to follow-up Determine, after ion implanting, DA/PF/PA region can be diffused under the effect of follow-up thermal oxide layer；The dosage of ion implanting Then adjust according to the property requirements of device.
6th step, photoetching and etching form a STI；First STI is based on buried regions technique.
Thermal oxide layer is formed
7th step, lithographic definition and ion implanting form N trap.
8th step, lithographic definition and ion implanting form p-well.
9th step, lithographic definition and ion implanting form N-type drift region.NF herein injects to be needed to change domain, makes N-type Drift region ion implanting and the active area by source region are without handing-over.No longer having DA district, simultaneously PF area reduction, the degree reducing depends on Determine according to thermal oxide layer.
10th step, gate oxide is formed and polysilicon layer is formed；
11st step, lithographic definition and ion implanting form PXing Ti district；
12nd step, photoetching and etching form polysilicon gate；
13rd step, forms side wall；
14th step, lithographic definition and ion implanting form heavily doped N-type district；
15th step, lithographic definition and ion implanting form heavily doped P-type district；
16th step, rapid thermal annealing；
17th step, cobalt silicide is formed, and deposits inter-level dielectric.
Through above-mentioned processing step, the present invention changes NF injection zone, eliminates traditional DA region, reduces PF district Territory, drift region becomes non-uniform doping, and the drift region concentration that N-type drift region territory is not injected into is little, and the drift region having NF to inject is dense Degree is big, and highfield appears in the bottom of the 2nd STI, near drain terminal.As in figure 2 it is shown, be N-type drift region territory different from Electric Field Distribution schematic diagram under sub-implantation dosage, represent respectively be N-type drift region territory ion implantation dosage be 3E12CM-2、 3.5E12CM-2、4E12CM-2、4.5E12CM-2Under Electric Field Distribution contrast, from figure 2 it can be seen that N-type drift region territory is lighter Ion implantation dosage, the generation of electric field breakdown is the closer to surface.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.Those skilled in the art is come Saying, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any modification of being made, equivalent Replacement, improvement etc., should be included within the scope of the present invention.

Claims (8)

1. the process switching N-type LDMOS device, it is characterised in that：Comprise following processing step：
1st step, ion implanting forms n type buried layer, and carry out picking into；
2nd step, ion implanting forms p type buried layer, and carry out picking into；
3rd step, p-type epitaxial layer is formed, then carry out the injection of N-type deep trap and pick into；
4th step, photoetching and etching form the 2nd STI；
5th step, carries out a p-type ion implanting；
6th step, photoetching and etching form a STI；Form thermal oxide layer；
7th step, lithographic definition and ion implanting form N trap；
8th step, lithographic definition and ion implanting form p-well；
9th step, lithographic definition and ion implanting form N-type drift region；N-type drift region and the active area by source region are without handing-over；
10th step, gate oxide is formed and polysilicon layer is formed；
11st step, lithographic definition and ion implanting form PXing Ti district；
12nd step, photoetching and etching form polysilicon gate；
13rd step, forms side wall；
14th step, lithographic definition and ion implanting form heavily doped N-type district；
15th step, lithographic definition and ion implanting form heavily doped P-type district；
16th step, rapid thermal annealing；
17th step, cobalt silicide is formed, and deposits inter-level dielectric.
2. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：Described 2nd step, described P Type buried regions is formed at the periphery of n type buried layer, by device around encirclement.
3. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：Described 4th step is formed 2nd STI, the STI that its degree of depth is formed less than follow-up 6th step.
4. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：The injection of described 5th step Energy is based on what thermal oxide layer in follow-up 6th step was formed temperature and determines, can be at follow-up thermal oxide layer after ion implanting Effect under be diffused into DA district/P drift district/PA district, described DA district is raceway groove to the N-type drift region territory between the 2nd STI, institute Stating PA district is grid to the region between drain region in N-type drift region；The dosage injecting is to adjust according to the property requirements of device.
5. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：Described 8th step, described P Trap is positioned on p type buried layer.
6. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：Described 9th step, N-type is floated Moving injecting of district needs to ensure with the active area by source region without handing-over, and not having DA region, P-drift region reduces simultaneously.
7. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：Described 14th step, forms Heavily doped N-type district is source region and the drain region of LDMOS device.
8. the process switching N-type LDMOS device as claimed in claim 1, it is characterised in that：Described 15th step, forms P-well or PXing Ti district are drawn by heavily doped P-type district.
CN201610876652.0A 2016-09-30 2016-09-30 Technological method for switch N type LDMOS device Pending CN106449412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610876652.0A CN106449412A (en) 2016-09-30 2016-09-30 Technological method for switch N type LDMOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610876652.0A CN106449412A (en) 2016-09-30 2016-09-30 Technological method for switch N type LDMOS device

Publications (1)

Publication Number Publication Date
CN106449412A true CN106449412A (en) 2017-02-22

Family

ID=58172905

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610876652.0A Pending CN106449412A (en) 2016-09-30 2016-09-30 Technological method for switch N type LDMOS device

Country Status (1)

Country Link
CN (1) CN106449412A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635613A (en) * 2020-07-22 2021-04-09 重庆中易智芯科技有限责任公司 CMOS APD photoelectric device with low dark current

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132753A (en) * 1990-03-23 1992-07-21 Siliconix Incorporated Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
CN103311277A (en) * 2012-03-07 2013-09-18 旺宏电子股份有限公司 Semiconductor structure and preparation method thereof
CN104659090A (en) * 2013-11-18 2015-05-27 上海华虹宏力半导体制造有限公司 LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method
CN104821334A (en) * 2015-03-11 2015-08-05 上海华虹宏力半导体制造有限公司 N-type LDMOS device and process method thereof
CN105140289A (en) * 2015-09-22 2015-12-09 上海华虹宏力半导体制造有限公司 N-type LDMOS device and technical method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132753A (en) * 1990-03-23 1992-07-21 Siliconix Incorporated Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
CN103311277A (en) * 2012-03-07 2013-09-18 旺宏电子股份有限公司 Semiconductor structure and preparation method thereof
CN104659090A (en) * 2013-11-18 2015-05-27 上海华虹宏力半导体制造有限公司 LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method
CN104821334A (en) * 2015-03-11 2015-08-05 上海华虹宏力半导体制造有限公司 N-type LDMOS device and process method thereof
CN105140289A (en) * 2015-09-22 2015-12-09 上海华虹宏力半导体制造有限公司 N-type LDMOS device and technical method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635613A (en) * 2020-07-22 2021-04-09 重庆中易智芯科技有限责任公司 CMOS APD photoelectric device with low dark current
CN112635613B (en) * 2020-07-22 2022-06-21 重庆中易智芯科技有限责任公司 CMOS APD photoelectric device with low dark current

Similar Documents

Publication Publication Date Title
CN105448979B (en) Horizontal dual pervasion field effect pipe and forming method thereof
CN105789311B (en) Horizontal proliferation field effect transistor and its manufacturing method
CN104716177B (en) A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage
CN105428415B (en) NLDMOS device and its manufacturing method
CN102044563A (en) LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof
CN106298935B (en) LDMOS device and its manufacturing method
CN102412162B (en) Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS)
CN106876453A (en) Trench gate IGBT and preparation method
CN106206320A (en) The manufacture method of LDMOS
CN101924131A (en) Transverse-diffusion MOS (Metal Oxide Semiconductor) device and manufacturing method thereof
CN103178087A (en) Ultra-high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure and production method thereof
CN104658913B (en) NLDMOS manufacture method
CN105810680A (en) Jfet and manufacturing method thereof
CN208028069U (en) Novel two-sided step buried oxide SOI LDMOS with buried structure
CN105679831B (en) Horizontal proliferation field-effect transistor and its manufacturing method
CN105514166A (en) NLDMOS device and manufacture method thereof
CN104966732B (en) GaAs base pHEMT devices and preparation method thereof
CN104576732A (en) FinFET parasitic lateral double-diffused semiconductor device
CN104638003B (en) Radio frequency LDMOS device and process
CN106449412A (en) Technological method for switch N type LDMOS device
CN104282763B (en) Radio frequency horizontal dual pervasion field effect transistor preparation method
CN103811402B (en) A kind of isolation structure process for making of ultrahigh voltage BCD technology
CN103022125A (en) NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method
CN109119458A (en) Isolation structure and process
CN102088031B (en) N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170222