CN112635613A - CMOS APD photoelectric device with low dark current - Google Patents
CMOS APD photoelectric device with low dark current Download PDFInfo
- Publication number
- CN112635613A CN112635613A CN202010709400.5A CN202010709400A CN112635613A CN 112635613 A CN112635613 A CN 112635613A CN 202010709400 A CN202010709400 A CN 202010709400A CN 112635613 A CN112635613 A CN 112635613A
- Authority
- CN
- China
- Prior art keywords
- layer
- dark current
- junction
- sti
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005684 electric field Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000969 carrier Substances 0.000 claims description 23
- 230000015556 catabolic process Effects 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 12
- 230000005693 optoelectronics Effects 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 230000002028 premature Effects 0.000 claims description 5
- 230000007704 transition Effects 0.000 claims description 5
- 230000009286 beneficial effect Effects 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 230000010354 integration Effects 0.000 claims description 4
- 238000010521 absorption reaction Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 29
- 238000005516 engineering process Methods 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 6
- 238000005286 illumination Methods 0.000 abstract description 5
- 230000031700 light absorption Effects 0.000 abstract description 5
- 230000009471 action Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 41
- 238000000034 method Methods 0.000 description 24
- 230000008569 process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 5
- 238000001514 detection method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02016—Circuit arrangements of general character for the devices
- H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02027—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier for devices working in avalanche mode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
Abstract
The invention provides a CMOS APD photoelectric device with low dark current, belonging to the field of semiconductor photoelectric devices. The device structure comprises a P substrate and a P trap, wherein the P trap is used for ion implantation, an N + layer and two P + layers are ion implanted on the P trap, the N + layer is a cathode, and the P + layer is an anode. Forming a PN junction between the heavily doped N + layer and the lightly doped P well layer, namely forming an avalanche region, and arranging an illumination window, wherein when a light source is emitted into the device and absorbed by the light absorption region, a photon-generated carrier is generated and moves to the avalanche region under the action of an electric field to participate in multiplication; STI guard rings are doped at two ends of the gap of the P well layer, and small-size STI guard rings are doped at two sides of the N + layer, so that not only can the reduction of dark current be ensured, but also the photocurrent can be effectively detected through reasonable STI arrangement; the photoelectric effect and the capacitance are optimized on the design of the device electrode. The design technology is designed from three aspects of PN junction, STI protection ring and electrode arrangement, reduces dark current of the device, ensures that photocurrent can be detected, and reduces capacitance.
Description
Technical Field
The invention belongs to the field of semiconductor devices, relates to the design technology of an APD photoelectric device, and particularly relates to the design of a low-dark-current CMOS APD photoelectric device.
Background
An Avalanche Photodiode (Avalanche Photodiode) is a photodetector that can achieve high sensitivity and high bandwidth. It has the function of generating multiplication carrier electrons and holes by absorbing an optical signal in a depletion layer by utilizing an avalanche breakdown effect. The basic design technology of the CMOS APD is similar to that of a common PN junction, but a new design technology is adopted in the structural design of the device, so that the working bandwidth of the device can be effectively improved, and the dark current of the device is reduced. CMOS APDs operating in the linear region are widely used in the Internet of things, compact disc read-only memory (CD-ROM), Digital Versatile Disc (DVD), and Blu-ray disc due to their low voltage and low cost.
Semiconductor device isolation techniques can be classified into two types according to their process types. One is a local field oxidation isolation process, which uses silicon nitride as a mask to realize selective oxidation of silicon, in this process, except for the area where the active transistor is formed, a thick oxide layer called isolation or field oxide layer is grown on all other heavily doped silicon regions, but the CMOS process reaches 0.25 μm, the disadvantage of LOCOS appears, the first is because the black mouth wastes space, the second is because the difference of the topgraph height on the surface is too large, the ILD must be very thick, so contact cannot be made small. The other is the STI guard ring technology, which has the advantages of low process temperature, no bird's beak effect, good surface planarization, etc., and becomes the main isolation technology of CMOS devices. This design technique is currently widely used in CMOS process technology, but its use in APD devices has an impact on photocurrent. Therefore, the device dark current is reduced under the condition of ensuring that the APD device has certain sensitivity.
In a high-sensitivity sensor composed of CMOS APD devices operating in a linear mode, a device for detecting optical signals and amplifying the signals by utilizing the photoelectric effect and the avalanche multiplication effect of the high-sensitivity sensor. In recent years, the research on CMOS APD devices has focused on designing APD devices to achieve low dark current using different APD structure design techniques, and on large-scale APD arrays and their signal processing circuits. Both of these efforts require further optimization of the CMOS APD device design techniques and performance to minimize the dark current of the device. In the traditional design technology of the APD device, STI protection rings are added at the two sides of a cathode and an anode for optimization, and the drift distance of a photon-generated electron carrier and the reasonable application of the STI protection rings are ignored, so that the aim of keeping relatively low dark current under the condition of ensuring that weak photocurrent is detected cannot be achieved.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A low dark current CMOS APD optoelectronic device is presented. The technical scheme of the invention is as follows:
a CMOS APD photoelectric device with low dark current comprises a P substrate, an anode, a cathode and a P well layer, wherein the P well layer is implanted on the P substrate through ions, the P well layer and an N + layer can form a PN junction, an N + layer and two P + layers are implanted and accumulated on the P well layer, the P + layer is connected with the anode, the N + layer serves as a light receiving window and is connected with the cathode, the light receiving window and the cathode can be connected into a subsequent circuit, namely a transimpedance amplifier, the heavily doped N + layer and the lightly doped P well layer form the PN junction (almost the same concentration order as that of the heavily doped P + layer and the lightly doped N well), namely an avalanche region is formed and an illumination window is arranged, when a light source is emitted into the device and absorbed by the light absorption region, photo-generated carriers are generated, and the photo-generated carriers drift to the avalanche region under the action of an electric field to participate; STI shallow trench isolation guard rings are added at two ends of the gap of the P well layer, the STI guard rings prevent the PN junction from being broken down too early and reduce dark current, transparent positive and negative electrodes are adopted, the cathode is arranged in an L-shaped structure, the anode is arranged in an inverted F-shaped structure, and the two structures are beneficial to the connection of an external circuit.
Furthermore, the PN junction is a heavily doped junction of an N +/P well, the heavily doped N + layer and the lightly doped P well layer respectively adopt doping concentrations of 19 and 17, and short STI guard rings are arranged at two ends of the PN junction, so that the dark current is reduced, and the transition of diffusion carriers is reduced.
Furthermore, the electric field distribution at the PN junction is uniform and consistent, and the maximum electric field intensity reaches 6.9 multiplied by 105V/cm。
Furthermore, when incident light is incident on the P well layer and absorbed and generates photon-generated carriers, the N + layer and the P well layer are adopted on two sides of the PN junction, the diffusion carriers in the P substrate cannot diffuse towards the P substrate due to the STI protection rings on the two sides of the PN junction, so that dark current is reduced, avalanche breakdown is generated at the N +/P well, and the dark current serving as the diffusion carriers is reduced due to the fact that the PN junction is a heavily doped region.
Furthermore, the cathode and the anode are transparent cathode and anode electrodes, so that the complete absorption of the device on illumination can be ensured, the capacitance of the device can be effectively reduced, and the integration of the device on other circuits is facilitated.
Furthermore, the N + layer adopts semiconductors doped with pentavalent impurity elements with different concentrations, and the P substrate, the P + layer and the P well layer all adopt semiconductors doped with trivalent impurity elements with different concentrations.
The invention has the following advantages and beneficial effects:
the invention provides a novel design technology for designing a low dark current CMOS APD photoelectric device and a design method thereof. In a conventional single-window APD, a PN junction is formed by a heavily doped P + layer and a lightly doped N well to form an avalanche region, and the length of an STI guard ring is set to exceed the width of a depletion layer. The design method comprises the steps that a heavily doped N + layer and a lightly doped P well form a PN junction, and STI with the depth reduced by half (the detectability of photocurrent is ensured and the premature breakdown of the PN junction is avoided) is injected at two sides of the PN junction to form a protection ring. Compared with the conventional CMOS APD device, the device designed and optimized by the invention obviously reduces dark current and ensures the detectability of photocurrent.
The CMOS APD design technology with low dark current and the optimization method provided by the invention are as follows:
1. the APD device designed by the invention is a planar design technology of N +/P well/P substrate. The key factor influencing the transition time of the current carrier is found out, the maximum transition time of the photon-generated current carrier in the device is reduced through the structural design of the device in a targeted manner, and the working frequency of the device is further effectively improved. The device design technology is characterized in that: considering the device with the N +/P well structure, a light irradiation window is arranged between the heavily doped N + layer and the lightly doped P well. The longitudinal width of a depletion region is reduced by adopting a heavily doped avalanche junction, meanwhile, the illumination area is reduced, the transverse width of a depletion layer is reduced, the quantity and the range of diffusion carriers entering the depletion layer are reduced, and the dark current of the device is substantially reduced.
The avalanche junction is an N +/P well, when avalanche breakdown occurs to the PN junction, the carriers multiply, but the PN junction is not a conventional single-side abrupt junction, so that the energy band in a depletion region of the design technology is steeper, and most carriers are not easy to tunnel between bands, so that the transition of diffused carriers is substantially reduced, and the aim of reducing dark current is fulfilled.
2. The structure of the low dark current CMOS APD photoelectric device is characterized in that: the design technology is based on the design of the protection ring and the reasonable arrangement of the detection window. The STI rings which are shorter than the device are injected at two sides of the PN junction, because the edge breakdown of the depletion layer without the protection ring is easy to occur at the edge of the depletion layer and the breakdown electric field is unevenly distributed, the arrangement of the STI can ensure that the electric field of the depletion layer is evenly distributed, prevent the diffusion current from entering the depletion layer and simultaneously ensure that the photocurrent can be detected between the cathode and the anode. The structure avoids the premature edge breakdown of the PN junction, further reduces the dark current, and ensures the detection of the photocurrent under the condition of unchanged detection area.
The concentration, thickness, N + thickness of the P-well are adjustable. The concentration, the thickness and the N + thickness of the P trap are adjusted through a process or computer simulation, the dark current of the P trap reaches the lowest value through simulation, the transparent positive and negative electrodes can ensure the complete absorption of the device on illumination, the capacitance of the device can be effectively reduced, and the integration of the device on other circuits is facilitated.
Drawings
FIG. 1 is a diagram of a conventional CMOS APD design technique
FIG. 2 is a diagram of a preferred embodiment CMOS APD design technology provided by the present invention;
FIG. 3 is a diagram of a preferred embodiment CMOS APD electrode design technique according to the present invention;
FIG. 4 is a diagram of a preferred embodiment CMOS APD electric field profile provided by the present invention;
FIG. 5 is a graph of the electrical field strength for a CMOS APD according to a preferred embodiment of the present invention;
FIG. 6 is a graph of the optical dark current characteristics of a CMOS APD according to a preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
fig. 1 shows a technical diagram of a conventional CMOS APD optoelectronic device. As can be seen, in the design technique, the PN junction is composed of a heavily doped P + layer and a lightly doped N well, an avalanche region (corresponding to the 1-1 region in the figure) is located at the PN junction, and the P-substrate below the avalanche region is the main light absorption region. P + on two sides of the PN junction is used as a protection ring, premature edge breakdown of the device is avoided, and diffusion carriers on two sides of the device are prevented from entering. The working principle of the APD photoelectric device is that when incident light is absorbed by a light absorption region (corresponding to a region 1-1 in the figure), photogenerated carriers are generated inside the device, the photogenerated carriers drift to move to an avalanche region (corresponding to the region 1-1 in the figure) under the action of a high electric field (PN junction reverse bias), and diffusion current diffuses towards the avalanche region.
The STI disposed at the two ends of the N + layer needs to have a reasonable size and to allow the photo-generated electron-hole pairs to drift toward N + and P + respectively. The size and doping position are reasonably set by combining the BSIM4 model and the empirical formula mentioned in the literature. The main area of influence of the STI guard ring is in the horizontal direction, and for the design purpose of the device in this chapter, this section discusses the mobility and normalizes the mobility.
Calculating the mobility of the carriers on both sides of the STI under the normalized condition, wherein LOD is the transverse transit length of the carriers, STIWL,RThe distances from the left and right sides of the STI guard ring to other STI guard rings. The values of alpha, beta and zeta are 0.1102, 0.0729 and 1 respectively, which is related to the device adopting an N +/P well structure. In modeling, when the worst case occurs at the edge of an STI guard ring, diffusion conditions of hole-electron pairs under the maximum size and the minimum size of the STI in a device are considered, and then alpha, beta and zeta values are obtained.
MOBL,RIs mobility multiplied and the parameters L and R refer to the left and right directions with respect to STI. To find the final mobility, the mobility parameters at the left and right sides of the STI should be multiplied. It has also been found that lowering STIW or increasing LOD increases the mobility of the depletion layer in the N +/P well structure. The structure is thus shortened by 50% in the longitudinal dimension compared with the other patents. And the longer STI guard rings are arranged at the two ends of the P + to isolate the carrier of the substrate from slowly diffusing to the depletion layer, thereby reducing the dark current of the device.
FIG. 2 is a technical diagram of the design of a novel CMOS APD optoelectronic device, which shows that the device has two changes relative to a conventional APD, namely that a PN junction formed by an N +/P well is a heavily doped avalanche junction. When the light source is emitted into the device and absorbed by the light absorption region (corresponding to the 2-1 region in the figure), photon-generated carriers are generated, and the photon-generated carriers move to the avalanche region (corresponding to the 2-1 region in the figure) under the action of an electric field to participate in multiplication. The designed PN junction is a heavily doped avalanche junction, so that the size of a depletion region is obviously narrowed compared with that of a conventional APD, meanwhile, the potential barrier is higher, diffusion of diffusion carriers to the APD is reduced, a P well layer is added to form the potential barrier to reduce diffusion of substrate carriers, and the size of an STI (shallow trench isolation) protective ring is reduced (corresponding to a 2-2 region in a figure), so that the photogenerated carriers in the depletion layer are guaranteed to drift to an anode.
Fig. 3 shows a design technical diagram of a novel CMOS APD electrode, in which transparent cathode and anode electrodes can prevent the loss caused by the light shielding of the metal electrode, and at the same time, the capacitance of the device can be effectively reduced, which is beneficial to the integration of the device in other circuits. 3-1 denotes an anode, and 3-2 denotes a cathode.
FIG. 4 shows a novel CMOS APD electric field profile. As can be seen, in the avalanche region (corresponding to the 2-1 region in the figure), the photogenerated electron carriers in the P-well drift toward N +. An STI guard ring is also arranged in the design technology, the main function is to inhibit the premature edge breakdown of the PN junction, and the dark current of the device can be further reduced. For APDs, the dark current is mainly affected by two factors: temperature, device structure. With constant temperature, the device structure is the main factor that determines the dark current. From the foregoing analysis, it can be seen that the conventional APD employs LOCOS, which is prone to cause bird's beak effect at high electric field strength to degrade the device performance, and thus, the dark current of the device is increased. For the novel CMOS APD designed by the invention, as shown in FIG. 2, the STI longitudinal size is reduced, which not only ensures the detectability of photocurrent, but also reduces dark current.
FIG. 5 is a graph showing the electric field intensity of a novel CMOS APD device, which shows that the electric field distribution at the PN junction (about 0.48 μm) is uniform and consistent, and the maximum electric field intensity reaches 6.9 × 105V/cm, and the PN junction edge electric field is significantly lower than the central electric field due to the presence of the STI guard ring at the PN junction edge.
FIG. 6 is a graph of the optical dark current characteristics of a novel CMOS APD device showing that the minimum value of dark current is about 1 × 10-13A, when avalanche breakdown is not reached, the average value of photocurrent is about 1X 10-9A, the value of the dark current gradually approaches saturation with an increase in the bias voltage, and the saturation current reaches the milliamp level. From the overall dark current characteristic, the breakdown voltage is about-12V.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.
Claims (6)
1. A CMOS APD photoelectric device with low dark current comprises a P substrate, an anode and a cathode, and is characterized by further comprising a P well layer implanted on the P substrate through ions, wherein the P well layer is used for forming a PN junction with an N + layer; and STI shallow trench isolation protection rings with the depth reduced by half are added at two ends of the gap of the P well layer, the STI protection rings prevent the premature breakdown of PN junctions and reduce dark current, transparent positive and negative electrodes are adopted, the cathode is arranged in an L-shaped structure, the anode is arranged in an inverted F-shaped structure, and the two structures are beneficial to the connection of an external circuit of the P well layer.
2. The low dark current CMOS APD optoelectronic device of claim 1, wherein the PN junction is a heavily doped N +/P well, the heavily doped N + layer and the lightly doped P well are doped with doping concentrations of 19 and 17, respectively, and the short STI guard rings are provided at both ends to reduce dark current and reduce transition of diffusion carriers.
3. The low dark current CMOS APD optoelectronic device of claim 1, wherein the electric field distribution at said PN junction is uniform and consistent, with a maximum electric field strength of up to 6.9 x 105V/cm。
4. The low dark current CMOS APD optoelectronic device of claim 1, wherein when incident light is absorbed and generates photogenerated carriers at the P-well layer, N + layer and P-well layer are used on both sides of the PN junction, dark current is reduced because the STI guard rings on both sides of the PN junction make the diffused carriers in the P-substrate not diffuse towards the P-well layer, and avalanche breakdown at the N +/P-well is reduced because the PN junction is a heavily doped region, which is a diffused carrier.
5. The low dark current CMOS APD optoelectronic device of claim 1, wherein the cathode and anode are transparent cathode and anode electrodes, which can ensure complete absorption of the device to light, and at the same time, can effectively reduce device capacitance, facilitating device integration in other circuits.
6. The low dark current CMOS APD optoelectronic device of claim 1, wherein said N + layer is doped with pentavalent impurity element semiconductors of different concentrations, and said P substrate, said P + layer, and said P well layer are doped with trivalent impurity element semiconductors of different concentrations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010709400.5A CN112635613B (en) | 2020-07-22 | 2020-07-22 | CMOS APD photoelectric device with low dark current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010709400.5A CN112635613B (en) | 2020-07-22 | 2020-07-22 | CMOS APD photoelectric device with low dark current |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112635613A true CN112635613A (en) | 2021-04-09 |
| CN112635613B CN112635613B (en) | 2022-06-21 |
Family
ID=75300093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010709400.5A Active CN112635613B (en) | 2020-07-22 | 2020-07-22 | CMOS APD photoelectric device with low dark current |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112635613B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020514A (en) * | 2022-06-29 | 2022-09-06 | 杭州海康威视数字技术股份有限公司 | Photodiode, preparation method thereof, photoelectric detector and detection equipment |
| CN115101606A (en) * | 2022-05-16 | 2022-09-23 | 西安电子科技大学芜湖研究院 | Ultraviolet light detector |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465862B1 (en) * | 1999-10-05 | 2002-10-15 | Brannon Harris | Method and apparatus for implementing efficient CMOS photo sensors |
| US20080121866A1 (en) * | 2006-11-27 | 2008-05-29 | Ping Yuan | Avalanche photodiode detector |
| CN103887362A (en) * | 2014-03-28 | 2014-06-25 | 重庆邮电大学 | NP-type CMOS avalanche photodiode with deep N-trap |
| US20150054111A1 (en) * | 2013-08-23 | 2015-02-26 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Single photon avalanche diode |
| CN104681609A (en) * | 2013-12-03 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | n-type LDMOS device and manufacturing method thereof |
| CN105448913A (en) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | CMOS device and forming method thereof |
| CN106449412A (en) * | 2016-09-30 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Technological method for switch N type LDMOS device |
| CN109545849A (en) * | 2018-12-12 | 2019-03-29 | 上海华力集成电路制造有限公司 | CMOS integrated technique BJT structure and its manufacturing method |
| CN110197859A (en) * | 2019-06-28 | 2019-09-03 | 重庆邮电大学 | It is a kind of to work in the high bandwidth CMOS APD photoelectric device of visible light wave range |
-
2020
- 2020-07-22 CN CN202010709400.5A patent/CN112635613B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465862B1 (en) * | 1999-10-05 | 2002-10-15 | Brannon Harris | Method and apparatus for implementing efficient CMOS photo sensors |
| US20080121866A1 (en) * | 2006-11-27 | 2008-05-29 | Ping Yuan | Avalanche photodiode detector |
| US20150054111A1 (en) * | 2013-08-23 | 2015-02-26 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Single photon avalanche diode |
| CN104681609A (en) * | 2013-12-03 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | n-type LDMOS device and manufacturing method thereof |
| CN103887362A (en) * | 2014-03-28 | 2014-06-25 | 重庆邮电大学 | NP-type CMOS avalanche photodiode with deep N-trap |
| CN105448913A (en) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | CMOS device and forming method thereof |
| CN106449412A (en) * | 2016-09-30 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Technological method for switch N type LDMOS device |
| CN109545849A (en) * | 2018-12-12 | 2019-03-29 | 上海华力集成电路制造有限公司 | CMOS integrated technique BJT structure and its manufacturing method |
| CN110197859A (en) * | 2019-06-28 | 2019-09-03 | 重庆邮电大学 | It is a kind of to work in the high bandwidth CMOS APD photoelectric device of visible light wave range |
Non-Patent Citations (1)
| Title |
|---|
| 陈婷: "高光电探测效率CMOS SPAD器件的研究", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115101606A (en) * | 2022-05-16 | 2022-09-23 | 西安电子科技大学芜湖研究院 | Ultraviolet light detector |
| CN115101606B (en) * | 2022-05-16 | 2023-10-03 | 西安电子科技大学芜湖研究院 | Ultraviolet light detector |
| CN115020514A (en) * | 2022-06-29 | 2022-09-06 | 杭州海康威视数字技术股份有限公司 | Photodiode, preparation method thereof, photoelectric detector and detection equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112635613B (en) | 2022-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107946389A (en) | A kind of CMOS single-photon avalanche diodes for long-wave band faint light | |
| US7211829B2 (en) | Semiconductor photodetector device | |
| CN108550592B (en) | Low dark count rate CMOS SPAD photoelectric device | |
| CN106449770A (en) | Annular-gate single-photon avalanche diode capable of preventing edge breakdown and preparation method of annular-gate single-photon avalanche diode capable of preventing edge breakdown | |
| CN112635613B (en) | CMOS APD photoelectric device with low dark current | |
| JP2015041746A (en) | Single-photon avalanche diode | |
| JP2017005276A (en) | Single-photon avalanche diode | |
| CN104810377A (en) | High-integration single-photon avalanche diode detector array unit | |
| JPWO2010041756A1 (en) | Photodetector | |
| CN110197859B (en) | High-bandwidth CMOS APD photoelectric device working in visible light wave band | |
| US10312391B2 (en) | Apparatus and method for single-photon avalanche-photodiode detectors with reduced dark count rate | |
| US8212327B2 (en) | High fill-factor laser-treated semiconductor device on bulk material with single side contact scheme | |
| TW201306291A (en) | Lateral avalanche photodiode structure | |
| Guo et al. | High-responsivity Si photodiodes at 1060 nm in standard CMOS technology | |
| JP2002314118A (en) | Photodetector | |
| CN114975657B (en) | SPAD device structure, SPAD detector and SPAD device structure manufacturing method | |
| CN106960852B (en) | Ultraviolet avalanche photodiode detector with drift channel and detection method thereof | |
| US20090261441A1 (en) | Optical semiconductor device | |
| CN213583789U (en) | Integrated photoelectric sensor | |
| US20030087466A1 (en) | Phototransistor device | |
| KR102617788B1 (en) | UTBB photoelectric detector pixel unit, array and method | |
| US8796743B2 (en) | Light-sensitive component | |
| CN109904271B (en) | Light sensing semiconductor unit and light sensing semiconductor array | |
| JP2020507927A (en) | Semiconductor structure and its manufacture | |
| US11749774B2 (en) | Avalanche photodetector (variants) and method for manufacturing the same (variants) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |