CN106449410A - Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate - Google Patents
Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate Download PDFInfo
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- CN106449410A CN106449410A CN201610874172.0A CN201610874172A CN106449410A CN 106449410 A CN106449410 A CN 106449410A CN 201610874172 A CN201610874172 A CN 201610874172A CN 106449410 A CN106449410 A CN 106449410A
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- Prior art keywords
- grid
- silicon
- substrate
- grid substrate
- photoresist
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229910052796 boron Inorganic materials 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005429 filling process Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
Abstract
The invention discloses a fabrication method of an enhanced N-type (Metal Oxide Semiconductor) transistor with a protruding grid substrate. The fabrication method comprises the following steps of 1, performing boron ion injection process on a wafer to form a P-type doping silicon substrate; 2, performing a shallow groove isolation process; 3, performing an etching process of a protruding part of the grid substrate; growing a layer of P-type doping silicon on the structure obtained in the step 2, wherein the height of the silicon is equal to the height of the protruding part of the grid substrate; 4, covering the grid substrate part by photoresist; 5, etching a part outside the photoresist by an etching technology, growing a poly-silicon grid, and forming a side wall; and 6, performing a source/drain injection process. In the growth structure, the substrate of a grid upwards protrudes, and the on/off of a circuit can be controlled at two sides of the circuit. By such a design, circuit control can be substantially improved, leakage is reduced, and the brake length of the transistor can be substantially shortened.
Description
Technical field
The present invention relates to IC manufacturing field, and in particular to the N-type metal-oxide-semiconductor that a kind of enhanced grid substrate protrudes
Manufacture method.
Background technology
In the prior art, the size of metal-oxide-semiconductor is done less and less, undersized, the then transistor of the N-type metal-oxide-semiconductor of enhancement mode
Grid control electric current also very little, be not easy to adjustment, then control accuracy is very poor.
Content of the invention
For the deficiencies in the prior art, the invention discloses a kind of manufacture of the N-type metal-oxide-semiconductor of enhanced grid substrate protrusion
Method.
Technical scheme is as follows：
A kind of manufacture method of the N-type metal-oxide-semiconductor that enhanced grid substrate protrudes, comprises the following steps：
Step 1, on the wafer on carry out boron ion injection process, form the silicon substrate of p-type doping；
Step 2, shallow grooved-isolation technique being carried out, isolation channel is etched, oxide filling process is carried out within isolation channel again afterwards,
The process of oxide planarization is finally carried out；
Step 3, carry out the etching process of grid substrate projection；In structure first obtained by step 2, one layer is grown
The silicon of p-type doping, which is highly highly equal with grid substrate projection；By photoresist, grid substrate portions are covered afterwards；
Finally by lithographic technique, will in addition to photoresist where etch；
Step 4, growing polycrystalline silicon grid；Grow gate oxide first, afterwards deposit polycrystalline silicon, and will be many by light section technology
Crystal silicon gate part cover, finally by lithographic technique, will in addition to photoresist where etch；
Step 5, formation side wall；Depositing layer of silicon dioxide first, removing is removed using dry ionic lithographic technique afterwards
Silicon dioxide outside sidewall section；
Step 6, carry out source, leakage injection technology；Female ion is injected, forms the n-type doping region of source electrode and drain electrode.
The method have the benefit that：
In the structure grown by the present invention, the substrate of grid is protruding upward, can connecing in the both sides control circuit of circuit
Through and off are opened.This design can greatly improve circuit control and reduce leakage current (leakage), it is also possible to significantly shorten crystal
The lock of pipe is long.
Description of the drawings
Fig. 1 is the structure chart grown by the present invention.
Specific embodiment
Fig. 1 is the structure chart grown by the present invention.As shown in figure 1, including silicon substrate 1 in this structure.The two of silicon substrate 1
Hold the isolation area 3 that makes for Si oxide.There is one layer of transition zone 2 between isolation area 3 and silicon substrate 1.The middle of silicon substrate 1 is
Polysilicon gate 5.The bottom of polysilicon gate 5 is the shape that raises up.There is one layer of dioxy between the bottom of polysilicon gate 5 and silicon substrate 1
SiClx 7.The top of polysilicon gate 5 is by one layer of titanium polycrystalline silicon 6.Between polysilicon gate 5 and isolation area 3, have within silicon substrate 1
The source region 8 of n-type doping and drain region 4.There is side wall 9 both sides of polysilicon gate 5.
The manufacturing process of the present invention is：
Step 1, on the wafer on carry out boron ion injection process, form the silicon substrate 1 of p-type doping；
Step 2, shallow grooved-isolation technique being carried out, isolation channel is etched, oxide filling process is carried out within isolation channel again afterwards,
The process of oxide planarization is finally carried out.
Step 3, carry out the etching process of grid substrate projection；In structure first obtained by step 2, one layer is grown
The silicon of p-type doping, which is highly highly equal with grid substrate projection；By photoresist, grid substrate portions are covered afterwards；
Finally by lithographic technique, will in addition to photoresist where etch.
Step 4, growing polycrystalline silicon grid 4；Gate oxide is grown first, afterwards deposit polycrystalline silicon, and will by light section technology
4 part of polysilicon gate cover, finally by lithographic technique, will in addition to photoresist where etch.
Step 5, formation side wall 9；Depositing layer of silicon dioxide first, removing is removed using dry ionic lithographic technique afterwards
Silicon dioxide outside sidewall section.
Step 6, carry out source, leakage injection technology；Female ion is injected, forms the n-type doping region of source electrode 4 and drain electrode 8.
Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above example.It is appreciated that this
Skilled person directly derive without departing from the spirit and concept in the present invention or associate other improve and become
Change, be all considered as being included within protection scope of the present invention.
Claims (1)
1. the manufacture method of the N-type metal-oxide-semiconductor that a kind of enhanced grid substrate protrudes, it is characterised in that comprise the following steps：
Step 1, on the wafer on carry out boron ion injection process, form the silicon substrate of p-type doping；
Step 2, shallow grooved-isolation technique is carried out, isolation channel is etched, carries out oxide filling process afterwards again within isolation channel, finally
Carry out the process of oxide planarization；
Step 3, carry out the etching process of grid substrate projection；In structure first obtained by step 2, one layer of p-type is grown
The silicon of doping, which is highly highly equal with grid substrate projection；By photoresist, grid substrate portions are covered afterwards；Finally
By lithographic technique, will in addition to photoresist where etch；
Step 4, growing polycrystalline silicon grid；Grow gate oxide first, afterwards deposit polycrystalline silicon, and pass through light section technology by polysilicon
Gate part cover, finally by lithographic technique, will in addition to photoresist where etch；
Step 5, formation side wall；Depositing layer of silicon dioxide first, removing side wall is removed using dry ionic lithographic technique afterwards
Silicon dioxide outside part；
Step 6, carry out source, leakage injection technology；Female ion is injected, forms the n-type doping region of source electrode and drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874172.0A CN106449410A (en) | 2016-09-30 | 2016-09-30 | Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874172.0A CN106449410A (en) | 2016-09-30 | 2016-09-30 | Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106449410A true CN106449410A (en) | 2017-02-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610874172.0A Withdrawn CN106449410A (en) | 2016-09-30 | 2016-09-30 | Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449410A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100818084B1 (en) * | 2005-12-28 | 2008-03-31 | 주식회사 하이닉스반도체 | Transister and method for forming the same |
| CN103035530A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method of N-channel metal oxide semiconductor (NMOS) switch device |
| US20130344668A1 (en) * | 2006-06-09 | 2013-12-26 | Suman Datta | Strain-inducing semiconductor regions |
-
2016
- 2016-09-30 CN CN201610874172.0A patent/CN106449410A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100818084B1 (en) * | 2005-12-28 | 2008-03-31 | 주식회사 하이닉스반도체 | Transister and method for forming the same |
| US20130344668A1 (en) * | 2006-06-09 | 2013-12-26 | Suman Datta | Strain-inducing semiconductor regions |
| CN103035530A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method of N-channel metal oxide semiconductor (NMOS) switch device |
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| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170222 |
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| WW01 | Invention patent application withdrawn after publication |