CN106298888A - The N-type metal-oxide-semiconductor that enhanced grid substrate protrudes - Google Patents
The N-type metal-oxide-semiconductor that enhanced grid substrate protrudes Download PDFInfo
- Publication number
- CN106298888A CN106298888A CN201610873860.5A CN201610873860A CN106298888A CN 106298888 A CN106298888 A CN 106298888A CN 201610873860 A CN201610873860 A CN 201610873860A CN 106298888 A CN106298888 A CN 106298888A
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- CN
- China
- Prior art keywords
- polysilicon gate
- silicon substrate
- oxide
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 4
- 239000010936 titanium Substances 0.000 claims abstract description 4
- 230000007704 transition Effects 0.000 claims abstract description 4
- 238000004904 shortening Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses the N-type metal-oxide-semiconductor that a kind of enhanced grid substrate protrudes, including silicon substrate；The two ends of described silicon substrate are the isolation area that Si oxide is made；One layer of transition zone is had between described isolation area and described silicon substrate；The middle of described silicon substrate is polysilicon gate；The bottom of described polysilicon gate is the shape that raises up；Layer of silicon dioxide is had between bottom and the described silicon substrate of described polysilicon gate；The top of described polysilicon gate is by one layer of titanium polycrystalline silicon；Between described polysilicon gate and described isolation area, within described silicon substrate, there are source region and the drain region of n-type doping；There is side wall the both sides of described polysilicon gate.In basis, the substrate of grid is protruding upward, can be in the connecting and disconnecting of the both sides control circuit of circuit.This design can greatly improve circuit control and reduce leakage current (leakage), it is also possible to the lock significantly shortening transistor is long.
Description
Technical field
The present invention relates to IC manufacturing field, be specifically related to the N-type metal-oxide-semiconductor that a kind of enhanced grid substrate protrudes.
Background technology
In the prior art, the size of metal-oxide-semiconductor is done less and less, the N-type metal-oxide-semiconductor of enhancement mode undersized, then transistor
Grid control electric current the least, be not easy to adjust, then control accuracy is very poor.
Summary of the invention
For the deficiencies in the prior art, the invention discloses the N-type metal-oxide-semiconductor that a kind of enhanced grid substrate protrudes.
Technical scheme is as follows:
The N-type metal-oxide-semiconductor that a kind of enhanced grid substrate protrudes, including silicon substrate；The two ends of described silicon substrate are silicon oxidation
The isolation area that thing is made；One layer of transition zone is had between described isolation area and described silicon substrate；The middle of described silicon substrate is many
Crystal silicon grid；The bottom of described polysilicon gate is the shape that raises up；One is had between bottom and the described silicon substrate of described polysilicon gate
Layer silicon dioxide；The top of described polysilicon gate is by one layer of titanium polycrystalline silicon；Between described polysilicon gate and described isolation area,
Source region and the drain region of n-type doping is had within described silicon substrate；There is side wall the both sides of described polysilicon gate.
The method have the benefit that:
In the present invention, the substrate of grid is protruding upward, can be in the connecting and disconnecting of the both sides control circuit of circuit.This
Design can greatly improve circuit control and reduce leakage current (leakage), it is also possible to the lock significantly shortening transistor is long.
Accompanying drawing explanation
Fig. 1 is the structure chart of the present invention.
Detailed description of the invention
Fig. 1 is the structure chart of the present invention.As it is shown in figure 1, the present invention includes silicon substrate 1.The two ends of silicon substrate 1 are silicon oxidation
The isolation area 3 that thing is made.One layer of transition zone 2 is had between isolation area 3 and silicon substrate 1.The middle of silicon substrate 1 is polysilicon gate 5.
The bottom of polysilicon gate 5 is the shape that raises up.Layer of silicon dioxide 7 is had between bottom and the silicon substrate 1 of polysilicon gate 5.Polycrystalline
The top of Si-gate 5 is by one layer of titanium polycrystalline silicon 6.Between polysilicon gate 5 and isolation area 3, within silicon substrate 1, there is n-type doping
Source region 8 and drain region 4.There is side wall 9 both sides of polysilicon gate 5.
The manufacturing process of the present invention is:
Step 1, on wafer on carry out boron ion implantation process, form the silicon substrate 1 of p-type doping；
Step 2, carry out shallow grooved-isolation technique, etch isolation channel, within isolation channel, carry out oxide filling process the most again,
Finally carry out the process of oxide planarization.
Step 3, the etching process of grid substrate projection of carrying out；First, in the structure obtained by step 2, one layer is grown
The silicon of p-type doping, its height is equal with the height of grid substrate projection；By photoresist, grid substrate portions is covered afterwards；
Finally by lithographic technique, by the local etching in addition to photoresist.
Step 4, growing polycrystalline silicon grid 4；First gate oxide, afterwards deposit polycrystalline silicon are grown, and will by light section technology
Polysilicon gate 4 part covers, finally by lithographic technique, by the local etching in addition to photoresist.
Step 5, formation side wall 9；First deposit layer of silicon dioxide, use dry ionic lithographic technique to remove removing afterwards
Silicon dioxide outside sidewall section.
Step 6, carry out source, leakage injection technology；Inject female ion, form source region 4 and the n-type doping region in drain region 8.
Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above example.It is appreciated that this
Skilled person the most directly derive or associate other improve and become
Change, within being all considered as being included in protection scope of the present invention.
Claims (1)
1. the N-type metal-oxide-semiconductor that an enhanced grid substrate protrudes, it is characterised in that include silicon substrate (1)；Described silicon substrate (1)
Two ends be the isolation area (3) that Si oxide is made；One layer of transition zone is had between described isolation area (3) and described silicon substrate (1)
(2)；The middle of described silicon substrate (1) is polysilicon gate (5)；The bottom of described polysilicon gate (5) is the shape that raises up；Described
Layer of silicon dioxide (7) is had between bottom and the described silicon substrate (1) of polysilicon gate (5)；The top of described polysilicon gate (5) by
One layer of titanium polycrystalline silicon (6)；Between described polysilicon gate (5) and described isolation area (3), described silicon substrate have N-type within (1)
The source region (8) of doping and drain region (4)；There is side wall (9) both sides of described polysilicon gate (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610873860.5A CN106298888A (en) | 2016-09-30 | 2016-09-30 | The N-type metal-oxide-semiconductor that enhanced grid substrate protrudes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610873860.5A CN106298888A (en) | 2016-09-30 | 2016-09-30 | The N-type metal-oxide-semiconductor that enhanced grid substrate protrudes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106298888A true CN106298888A (en) | 2017-01-04 |
Family
ID=57717260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610873860.5A Withdrawn CN106298888A (en) | 2016-09-30 | 2016-09-30 | The N-type metal-oxide-semiconductor that enhanced grid substrate protrudes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298888A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120049253A1 (en) * | 2004-12-28 | 2012-03-01 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
| US20130344668A1 (en) * | 2006-06-09 | 2013-12-26 | Suman Datta | Strain-inducing semiconductor regions |
| CN105118832A (en) * | 2015-07-20 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Sonos memory and manufacturing method thereof |
-
2016
- 2016-09-30 CN CN201610873860.5A patent/CN106298888A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120049253A1 (en) * | 2004-12-28 | 2012-03-01 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
| US20130344668A1 (en) * | 2006-06-09 | 2013-12-26 | Suman Datta | Strain-inducing semiconductor regions |
| CN105118832A (en) * | 2015-07-20 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Sonos memory and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170104 |
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| WW01 | Invention patent application withdrawn after publication |