CN106413273B - The technique for improving plate face copper particle - Google Patents
The technique for improving plate face copper particle Download PDFInfo
- Publication number
- CN106413273B CN106413273B CN201610936173.3A CN201610936173A CN106413273B CN 106413273 B CN106413273 B CN 106413273B CN 201610936173 A CN201610936173 A CN 201610936173A CN 106413273 B CN106413273 B CN 106413273B
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- Prior art keywords
- wiring board
- processing
- electric plating
- nog plate
- board
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
Abstract
The present invention provides a kind of techniques for improving plate face copper particle, and electric plating of whole board-nog plate process flow is adjusted to first time electric plating of whole board-- second nog plate of-second electric plating of whole board of first time nog plate process flow.The beneficial effects of the present invention are: in the case where total time is constant, electric plating of whole board processing is divided into electric plating of whole board processing twice, and increase a nog plate processing between the processing of electric plating of whole board twice, effectively improve the case where PCB surface generates big copper particle during electric plating of whole board.
Description
Technical field
The present invention relates to wiring board manufacturing fields, refer in particular to a kind of technique for improving plate face copper particle.
Background technique
Production outer-layer circuit is broadly divided into positive process or negative film process two ways in route board industry at present, with negative film
The process that mode makes outer-layer circuit is main are as follows: preceding process-sinks copper-electric plating of whole board-outer graphics-outer layer etching-rear process, In
In electric plating of whole board processing, the general practice is that copper thickness is disposably plated to specified thickness (disposable copper thickness 25-35 microns of plating), In
In this treatment process, the time of plating is longer, however electroplating liquid medicine is in use for some time, and the impurity in medicine cylinder can be gradually
Increase, impurity once adhere in the circuit board, can assist side Surface Creation copper particle, the wiring board made of negative film mode because
To be electroplated for a long time, PCB surface is easy to generate big copper particle, in the nog plate processing after electric plating of whole board processing, using needle
The processing mode of brush or nonwoven fabric polish-brush is difficult to remove clean this big copper particle, and uses the processing mode of abrasive belt grinding that can make
Increased production cost, it is also possible to deeper polishing scratch can be generated in the circuit board, if but do not handle big copper particle, wiring board can be made
When pressing dry film in the processing of subsequent outer graphics, big copper particle pierces through dry film, causes to etch rear board appearance open circuit, notch
The defects of, seriously affect qualification rate.
Summary of the invention
The technical problems to be solved by the present invention are: the wiring board of improvement negative film technique production Surface Creation in copper facing is big
The case where copper particle, avoids big copper particle in subsequent processing from influencing the quality of wiring board.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows: a kind of technique for improving plate face copper particle, according to
It is secondary the following steps are included:
S1, copper electroplating layer as needed thickness determine the electroplating current density and electroplating time of wiring board；
S2, first time electric plating of whole board is carried out to wiring board by the 45%-55% of determining electroplating time；
S3, the processing of first time nog plate is carried out to wiring board；
S4, second of electric plating of whole board is carried out to wiring board by remaining electroplating time；
S5, second of nog plate processing is carried out to wiring board.
Further, electric plating of whole board processing is done to wiring board with the parameter of 2.0-2.4ASD in step S2.
Further, in step S3 with the current of electric parameter of 2.5-3.1A, with 600# nonwoven fabric polish-brush to wiring board into
Row nog plate.
It further, is 5.5-6.5m/min to the wiring board conveying speed of wiring board nog plate processing in step S3.
Further, electric plating of whole board processing is done to wiring board with the parameter of 2.0-2.4ASD in step S4.
Further, in step S5 with the current of electric parameter of 2.5-3.1A, with 600# nonwoven fabric polish-brush to wiring board into
Row nog plate.
It further, is 5.5-6.5m/min to the wiring board conveying speed of wiring board nog plate processing in step S5.
The beneficial effects of the present invention are: in the case where total time is constant, an electric plating of whole board processing is divided into two
Secondary electric plating of whole board processing, and increase a nog plate processing between the processing of electric plating of whole board twice, it effectively improves in electric plating of whole board
PCB surface generates the case where big copper particle in the process.
Specific embodiment
In order to describe the technical content, the structural feature, the achieved object and the effect of this invention in detail, below in conjunction with embodiment
It is explained in detail.
It is a kind of improve plate face copper particle technique, successively the following steps are included:
S1, copper electroplating layer as needed thickness determine the electroplating current density and electroplating time of wiring board；
S2, first time electric plating of whole board is carried out to wiring board by the 45%-55% of determining electroplating time；
S3, the processing of first time nog plate is carried out to wiring board；
S4, second of electric plating of whole board is carried out to wiring board by remaining electroplating time；
S5, second of nog plate processing is carried out to wiring board.
Implement example:
Need copper-plated thickness at 33.16 microns in this implementation example, taking parameter is the current density of 2.2ASD, it is contemplated that
Electroplating time is T=80min.
First time electroplating time is set as T1=(45%-55%) T=36-44min, copper facing is with a thickness of 16.58 microns.
Using needle brush or nonwoven fabric polish-brush, it is preferred that 600# nonwoven fabric polish-brush is used, with the current of electric of 2.5-3.1A
Parameter polishes for the first time to wiring board.
Second of electroplating time is set as remaining electroplating time T2=T-T1, for example first time electroplating time is 44min, then the
The second time electroplating time is T2=80-44=36min, for another example the first time copper facing time is 36min, then second of electroplating time is T2=
80-36=44min, copper facing is with a thickness of 16.58 microns.
Using 600# nonwoven fabric polish-brush, second is carried out to wiring board with the current of electric parameter of 2.5-3.1A and is polished.
As can be seen from the above description, the beneficial effects of the present invention are: it, will primary full plate electricity in the case where total time is constant
Plating is divided into electric plating of whole board processing twice, and increases a nog plate processing between the processing of electric plating of whole board twice, effectively changes
It has been apt to the case where PCB surface generates big copper particle during electric plating of whole board.
Embodiment 1
Electric plating of whole board processing is done to wiring board with the parameter of 2.0-2.4ASD in step S2.
The current density of 2.0-2.4ASD is conducive to the speed for accelerating electric plating of whole board, improves production efficiency.
Embodiment 2
Step S3 carries out nog plate to wiring board with the current of electric parameter of 2.5-3.1A, with 600# nonwoven fabric polish-brush.
Can effectively remove PCB surface generation tiny copper particle, reduce wiring board in subsequent electroplating process because
Snowball effect generates a possibility that big copper particle.
Embodiment 3
It is 5.5-6.5m/min to the wiring board conveying speed of wiring board nog plate processing in step S3.
It can guarantee nog plate effect and nog plate efficiency.
Embodiment 4
Electric plating of whole board processing is done to wiring board with the parameter of 2.0-2.4ASD in step S4.
The current density of 2.0-2.4ASD is conducive to the speed for accelerating electric plating of whole board, improves production efficiency.
Embodiment 5
With the current of electric parameter of 2.5-3.1A in step S5, nog plate is carried out to wiring board with 600# nonwoven fabric polish-brush.
The tiny copper particle that removal PCB surface generates again, dry film when guaranteeing to press dry film in subsequent outer graphics process
It will not be pierced through by copper particle.
Embodiment 6
It is 5.5-6.5m/min to the wiring board conveying speed of wiring board nog plate processing in step S5.
It can guarantee nog plate effect and nog plate efficiency.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright description is applied directly or indirectly in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (1)
1. it is a kind of improve plate face copper particle technique, successively the following steps are included:
S1, copper electroplating layer as needed thickness determine the electroplating current density and electroplating time of wiring board；
S2, first time electric plating of whole board is carried out to wiring board by the 45%-55% of determining electroplating time, with the ginseng of 2.0-2.4ASD
Several pairs of wiring boards do electric plating of whole board processing；
S3, the processing of first time nog plate is carried out to wiring board, with the current of electric parameter of 2.5-3.1A, with 600# nonwoven fabric polish-brush pair
Wiring board carries out nog plate, and the wiring board conveying speed to the processing of wiring board nog plate is 5.5-6.5m/min；
S4, second of electric plating of whole board is carried out to wiring board by remaining electroplating time, with the parameter of 2.0-2.4ASD to wiring board
Do electric plating of whole board processing；
S5, second of nog plate processing is carried out to wiring board, with the current of electric parameter of 2.5-3.1A, with 600# nonwoven fabric polish-brush pair
Wiring board carries out nog plate, and the wiring board conveying speed to the processing of wiring board nog plate is 5.5-6.5m/min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610936173.3A CN106413273B (en) | 2016-11-01 | 2016-11-01 | The technique for improving plate face copper particle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610936173.3A CN106413273B (en) | 2016-11-01 | 2016-11-01 | The technique for improving plate face copper particle |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106413273A CN106413273A (en) | 2017-02-15 |
| CN106413273B true CN106413273B (en) | 2019-11-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610936173.3A Active CN106413273B (en) | 2016-11-01 | 2016-11-01 | The technique for improving plate face copper particle |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108133886A (en) * | 2017-12-11 | 2018-06-08 | 上海申和热磁电子有限公司 | A kind of method of DBC substrate backs grinding |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841972A (en) * | 2010-04-23 | 2010-09-22 | 汕头超声印制板公司 | Method for manufacturing high-AR and fine-line PCB |
| CN101977486A (en) * | 2010-10-29 | 2011-02-16 | 东莞红板多层线路板有限公司 | Method for manufacturing via stubs of circuit board |
| CN104717845A (en) * | 2013-12-13 | 2015-06-17 | 深圳崇达多层线路板有限公司 | Technological method for outer layer circuit board resin hole plugging of multi-layer circuit board |
| CN105323973A (en) * | 2015-11-03 | 2016-02-10 | 大连崇达电路有限公司 | Reworking method for solving bad backlight caused by rough circuit board hole wall |
-
2016
- 2016-11-01 CN CN201610936173.3A patent/CN106413273B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841972A (en) * | 2010-04-23 | 2010-09-22 | 汕头超声印制板公司 | Method for manufacturing high-AR and fine-line PCB |
| CN101977486A (en) * | 2010-10-29 | 2011-02-16 | 东莞红板多层线路板有限公司 | Method for manufacturing via stubs of circuit board |
| CN104717845A (en) * | 2013-12-13 | 2015-06-17 | 深圳崇达多层线路板有限公司 | Technological method for outer layer circuit board resin hole plugging of multi-layer circuit board |
| CN105323973A (en) * | 2015-11-03 | 2016-02-10 | 大连崇达电路有限公司 | Reworking method for solving bad backlight caused by rough circuit board hole wall |
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| CN106413273A (en) | 2017-02-15 |
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