CN106340577A - Substrate for chip mounting and chip package mounted with chip - Google Patents
Substrate for chip mounting and chip package mounted with chip Download PDFInfo
- Publication number
- CN106340577A CN106340577A CN201510394273.3A CN201510394273A CN106340577A CN 106340577 A CN106340577 A CN 106340577A CN 201510394273 A CN201510394273 A CN 201510394273A CN 106340577 A CN106340577 A CN 106340577A
- Authority
- CN
- China
- Prior art keywords
- chip
- conductive part
- insulation division
- concavo
- convex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
Abstract
The invention relates to a substrate for chip mounting. According to the invention, the substrate for chip mounting comprises multiple a plurality of conductive portions, a plurality of insulating portions and a cavity, wherein the plurality of conductive portions apply electrodes to at least two mounted chip; the plurality of insulating portions are formed between adjacent conductive portions and electrically isolate the conductive portions; and the cavity dents towards the inner side in an area containing at least three conductive portions and at least two insulating portions to form a space for mounting the chips.
Description
Technical field
The present invention relates to a kind of substrate for pasting chip, it is used for mounting more particularly, to one kind
Multiple chips are in the board structure of intracavity.
Background technology
Led (light emitting diode) generally, as semiconductor light-emitting-diode is not
The Environmental light source of parent of induction public hazards, is attracted attention in multiple fields.Recently, use model with led
Enclose the back light unit (back-light expanding indoor and outdoor lighting, car headlamp, display device to
) etc. unit:blu multiple fields are it is desirable to the high-luminous-efficiency of led and outstanding heat dissipation characteristics.In order to
Obtain efficient led it is necessary first to improve material or the structure of led, but additionally, led encapsulation
Structure and be also required to improve for its material etc..
Hereinafter, various types of luminescence chips (including led) are referred to as " optical element core
Piece ", and optical element chip is mounted on the state of substrate and is referred to as " chip package ".Conventional
Optical element encapsulation with by substrate, such as centered on multiple insulating barriers of aluminum or copper base up/down perforation electrically
Insulation both sides substrate, a side terminal of the optical element of arrangement, such as anode terminal pass through wire etc. with
The electrical property of substrate of quite row connects, and another side terminal, such as cathode terminal also by wire etc. with cross
The electrical property of substrate of the adjacent column of vertically insulated layer connects.And, in order to improve from optical element reflection
The reflection efficiency of light, forms by shape wide at the top and narrow at the bottom on two row neighbouring across vertically insulated layer
The chamber that groove is constituted, and optical element and the wire being electrically connected with this are contained in intracavity portion.
But in these compositions, only optical element chip is mounted on the central part in chamber, and will mount
When the encapsulation of one optical element chip connects multiple, generally form and be connected in parallel, therefore, in order to
Realize the back light unit of predetermined power, need to increase the magnitude of current of supply according to the encapsulation number connecting,
And there is a problem of increasing power consumption.
Content of the invention
Problems to be solved by the invention
In order to realize the back light unit of predetermined power, the purpose of the present invention is used for providing a kind of chip attachment
Board structure, it can reduce the supply magnitude of current.
More specifically, the purpose of the present invention for provide by realize can mount in a substrate multiple
The structure of optical element chip, can reduce the board structure of power consumption.
For solution to problem
Multiple conductive parts are included according to a kind of chip attachment substrate of the present embodiment, to attachment at least
Two chips apply electrode；Multiple insulation divisions, are formed between described conductive part, described in electrical isolation
Conductive part；And chamber, it is comprising the area of insulation division described in conductive part described at least three and at least two
On domain, to inward side to the recessed space being formed with and mounting described chip.
Preferably, mutually different electrode is applied to the described conductive part neighbouring across described insulation division.
Preferably, the chip being mounted on the identical conduction portion of described intracavity electrically connects in parallel and mounts,
And be mounted on the different conductive parts of described intracavity chip direct connection electrically connect and mount.
Preferably, in described at least three conductive parts of described intracavity, positioned at any one end
The non-pasting chip of conductive part, does not mount the conductive part of described chip and the core being mounted on neighbouring conductive part
The electrode portion of piece is electrically connected with.
Preferably, described insulation division is by being formed at the anodic oxide coating bonding of at least one side of conductive part
To described conductive part, and conductive part described in electrical isolation.
Described chip attachment substrate may also include concavo-convex, its described insulation division by described intracavity every
From each described conductive part surface on formed with predetermined height, with the electrode being formed at described chip
Portion's bonding.
Preferably, described electrode portion is formed at the institute being relatively formed with the described conductive part surface in described chamber
State in the one side of chip, described described electrode portion that is concavo-convex and being formed at described opposite side is bonding.
Described chip attachment substrate may also include solder, and it is formed on described concavo-convex surface, uses
In welding described electrode portion and described concavo-convex.
Preferably, described chip attachment substrate also includes recess, and this recess is pre- in described intracavity depression
Depthkeeping degree, wherein, described concavo-convex on each the described conductive part surface be formed with described recess with pre-
Fixed height is formed, bonding with the electrode portion being formed at described chip.
Described chip attachment substrate may also include coating, its insulation division isolation described in described intracavity
Formed with predetermined height on each described conductive part surface, concavo-convex and described conductive part described in bonding.
Described chip attachment substrate may also include through hole, its by described chip attachment use substrate according to
During the cutting of predetermined unit region, on the region of facet and described insulation division intersection, described in insertion absolutely
Edge and described chip attachment substrate.
Aim to solve the problem that described technical problem a kind of chip attachment raw sheet according to the present embodiment include many
Individual conductive part, it is at least two of the unit chip substrate being mounted on zoning on chip attachment raw sheet
Chip applies electrode；Multiple insulation divisions, it is formed between described conductive part, leads described in electrical isolation
Electric portion；And chamber, it is comprising the region of insulation division described in conductive part described at least three and at least two
On, to inward side to the recessed space being formed with and mounting described chip.
Aim to solve the problem that a kind of chip package according to the present embodiment of described technical problem includes multiple conductions
Portion, it applies electrode to being pasted with least chip；Multiple insulation divisions, its be formed at described conductive part it
Between, conductive part described in electrical isolation；Chamber, is comprising conductive part described at least three and at least two institutes
State on the region of insulation division, to inward side to the recessed space being formed with and mounting described chip；And at least two
Individual chip, it is mounted on the plurality of conductive part, is applied in difference respectively from the plurality of conductive part
Electrode.
The effect of invention
The invention has the advantages that by realizing to mount multiple optical elements in a substrate
Multiple chips of attachment can be connected by the structure of chip with straight parallel-connection structure.Therefore, connect with parallel
Connect to compare and can reduce the supply magnitude of current, result can reduce power consumption.
Brief description
Fig. 1 is the perspective view representing according to the chip attachment substrate according to one embodiment of the invention.
Fig. 2 is the profile representing the chip attachment substrate according to one embodiment of the invention.
Fig. 3 is to represent pasting chip on the chip attachment substrate according to one embodiment of the invention
The profile of example.
Fig. 4 is the top view representing the chip attachment substrate according to one embodiment of the invention.
Fig. 5 is the perspective view representing the chip attachment raw sheet according to one embodiment of the invention.
Description of reference numerals
10: chip attachment raw sheet 100: chip attachment substrate
110: conductive part 120: insulation division
130: concavo-convex 140: chamber
150: through hole 200: chip
Specific embodiment
Description below only illustrates the principle of the present invention.Even if clearly not retouching in this manual
State or illustrate, those skilled in the art can implement the former of the present invention in the spirit and scope of the present invention
Manage and create multiple devices.The conditional language occurring in this manual and embodiment are merely intended to make
The design of the present invention is understood, and they are not limited to embodiment and the bar mentioned in description
Part.
In order that the people with general knowledge in the technical field of the invention can be easily implemented with this
Bright, and it is understandable so that the above objects, features and advantages of the present invention is become apparent from, with reference to attached
Figure and specific embodiment are described in further detail to the present invention.
When the present invention is described, judge illustrating as being not necessarily to of known technology related to the present invention
Ground or obscure idea of the invention, description is omitted.With reference to the accompanying drawings to having this heat release material
Material is described in detail in the preferred embodiment of interior chip attachment substrate.
Fig. 1 is the accompanying drawing representing the chip attachment substrate according to one embodiment of the invention.
With reference to Fig. 1, conductive part 110, insulation division are included according to the chip attachment substrate of the present embodiment
120 and chamber 140.
Apply electrode in the present embodiment conductive part 110 to the chip 200 of attachment.That is, it is to chip 200
Apply electrode, conductive part 110 formed by conductive material, the bottom of conductive part 110 be formed with electrode
Substrate 50 bonding, be applied in electrode from outside.Can be with aluminium plate in the present embodiment conductive part 110
Formed.
Be to apply electrode respectively to the electrode portion of chip 200, insulation division 120 by conductive part 110 electrically every
From.That is, it is the electrode that chip 200 is applied respectively with anode and negative electrode, electrical isolation conductive part 110,
And each conductive part 110 isolated is applied in anode and negative electrode respectively from outside.
Additionally, in the present embodiment, being to apply electrode at least two chips, conductive part 110 can be formed
For multiple.I.e. with reference to Fig. 1, three conductive parts 110 can be bonded with a unit substrate.
And, it is to apply different electrodes at least two chips and isolate multiple conductions in the present embodiment
Portion 110, insulation division 120 forms multiple.I.e. with reference to Fig. 1, in three conductions in a unit substrate
Two insulation divisions 120 can be formed between portion 110.
Therefore, in three conductive parts 110 isolated by two insulation divisions 120 positioned at the two of two ends
In individual conductive part 110, pasting chip on two conductive parts 110 in addition to a conductive part 110.
Now, apply mutually different electrode to the described conductive part 110 neighbouring across insulation division 120, at this
Embodiment, applies identical electrode to two conductive parts 110 positioned at two ends.The leading of non-pasting chip
Electric portion 110 can be electrically connected with the electrode portion of the chip being mounted on neighbouring conductive part 110.
That is, the chip being mounted on identical conductive part 110 electrically connects in parallel and mounts, and is mounted on another
The chip direct connection ground of one conductive part 110 electrically connects and mounts, and is therefore formed multiple on chip substrate
The straight parallel-connection structure of chip.
Subsequently, in the present embodiment, for forming the space of pasting chip 200, chip 200 attachment substrate
Including chamber 140, this chamber 140 becomes to the inner side direction spill of conductive part 110.I.e. with reference to Fig. 2, mount core
The surface of the substrate of piece 200 is recessed formation compared with exterior face.I.e. substrate is in the portion of pasting chip 200
The periphery divided forms the shape of outer wall.Now, the light released from chip 200 for reflection, chamber 140 can shape
Become shape wide at the top and narrow at the bottom.The outer wall in chamber 140 can tilt to the core direction of mounted substrate
Form is formed.
I.e. in the present embodiment, on the conductive part in space that chip attachment is formed in chamber 140, in attachment
After chip, chamber 140 is sealed with lens etc., and chip package can be manufactured.
And, in the present embodiment, insulation division 120 can be formed with the dielectric film of synthetic resin material.
Now, using the bonding conductive part such as liquid phase adhesive 110 and insulation division 120, for improving bonding force,
Can carry out in the state of the bonding film of synthetic resin material is clipped between conductive part 110 and insulation division 120
Bonding.Now, for more improving bonding force, the temperature higher than room temperature and normal pressure can kept
Can perform technique for sticking with the High Temperature High Pressure room of pressure.Additionally, bonding plane is passed through with mechanically or chemically side
After method gives roughness, technique for sticking can be carried out.
I.e. in conductive part 110 and the insulation division 120 of the present embodiment, at least one side to conductive part 110,
Preferably, the face in opposing insulation portion 120 is carried out with anodic oxidation (anodizing) process, by this conductive part
110 can bond to insulation division 12.When i.e. conductive part 110 is made of aluminum, for improving bonding force, viscous
Anodized can be carried out to each bonding plane it is also possible to so carrying out anode before connecing technique
The surface of oxidation processes gives roughness.
Additionally, in the present embodiment, such as conductive part 110 is aluminium base, insulation division 120 can be by phase
Anodized is carried out to the face of conductive part 110 and carries out bonding and formed.
Further, may also include concavo-convex 130 in the present embodiment chip attachment substrate.
On the surface of each conductive part that the present embodiment concavo-convex 130 is isolated by insulation division in chamber 140 with
Predetermined height is formed, bonding with the electrode portion being formed at chip.
The present embodiment concavo-convex 130 on the surface of each conductive part 110 isolated by insulation division 120 with
Predetermined height is formed, bonding with the electrode portion being formed at chip 200.I.e. concavo-convex 130 in conductive part
On 110 surface, with reference to Fig. 2, shape on the surface of the conductive part 110 of the central part being equivalent to chamber 140
Become.
The surface being equivalent to the conductive part 110 of the central part in chamber 140 is isolated by insulation division 120, and concavo-convex
Formed with predetermined height on the surface of 130 two conductive parts 110 isolated by insulation division 120.Concavo-convex
130 is that the electrode being applied to conductive part 110 applies to by the electrode portion of the chip 200 of attachment, preferably
Ground is formed by conductive material, or can be the gold concavo-convex 130 being made of gold.
I.e. the electrode portion of chip 200 be formed at relative with the surface of the conductive part 110 being formed with chamber 140
The one side of chip 200, concavo-convex 130 bond to the electrode portion being formed at opposite side.
With reference to Fig. 3, Fig. 3 is to represent according to attachment core on the chip 200 attachment substrate of above-described embodiment
The accompanying drawing of chip 200 encapsulation of piece 200, is formed at the bottom of chip 200 in the electrode portion of Fig. 3 chip 200
Face, when chip 200 is mounted on substrate, the electrode portion of chip 200 bonds to and is formed at the concavo-convex of substrate
130.
Therefore, in the present embodiment, concavo-convex 130 are formed at the place (electricity that there is chip 200 on aluminium base
Pole part), concavo-convex 130 can be formed using wire bonding apparatus.Or it is in another embodiment, recessed
The convex electrode portion that can be previously formed in chip, or the electrode portion body of chip is formed such that with energy
Enough play the thickness of concavo-convex effect, and bond on aluminium base.
Additionally, with reference to Fig. 3, chip 200 attachment substrate is welding electrode portion and concavo-convex 130 also can wrap
Include the solder (not shown) being formed on concavo-convex 130 surfaces.The coating being formed in uvchip electrode portion
(not shown) and concavo-convex 130 can pass through hot ultrasonic (thermo-sonic) welding bonding, or concavo-convex
Forming solder (not shown) on 130 surface and pass through welding being capable of bonding.
And, in the present embodiment chip 200 attachment substrate, recess is in the pre- depthkeeping of chamber 140 sunken inside
Degree, concavo-convex 130 on each conductive part 110 surface be formed with recess so that predetermined height is formed energy
Enough bond to the electrode portion being formed at chip 200.I.e. as described in Figure 2, chamber 140 can be formed with
Also form the recess with desired depth as shown in Figure 6 on conductive part 110 surface, and the table in recess
Form concavo-convex 130 on face.
Outside in flip-chip 200 structure, the space of output uv light is in addition to chip 200 bottom
Part, during pasting chip by concavo-convex 130 and electrode portion bonding part with irradiate uv light partly bright
Really divide, thus, it is possible to improve uv power.
And it is possible to alternatively form following sealings 400, therefore, the energy when constituting sealing 400
Enough amounts more correctly controlling material.This will illustrate in the following detailed description.
Coating (not shown) be may also include according to the chip 200 attachment substrate of the present embodiment.Coating is (not
Diagram) it is formed on the surface of conductive part 110 between concavo-convex 130 and conductive part 110.I.e. due to conductive part
The bonding reliability of concavo-convex 130 on 110 surfaces can reduce thus can be by conductive part 110 surface
The selective coating of upper formation (not shown) is by concavo-convex 130 firmer bondings.
Referring to Fig. 5, the chip attachment according to one embodiment of the invention is said with raw sheet 10
Bright.
With reference to Fig. 5, conductive part 110 is included according to the chip attachment raw sheet 10,10 of the present embodiment, absolutely
Edge 120 and chamber 140.
I.e. above-described embodiment chip attachment with substrate 100 pass through by according to the chip raw sheet 10 of Fig. 4 with pre-
The size of order position chip substrate is cut and is formed, the therefore chip attachment raw sheet according to the present embodiment
The effect according to above-described embodiment is played in 10 conductive part 110, insulation division 120 and chamber 140.
Therefore, conductive part 110 stacks in a direction and constitutes chip raw sheet 10, insulation division 120 and institute
State conductive part 110 to be alternately stacked and conductive part 110 described in electrical isolation.
Chamber 140 above chip raw sheet 10 each multiple unit chip substrate 100 of zoning comprise absolutely
Be recessed on the region of edge 120 desired depth.
Above this detailed description is repeated, therefore omit the description here.
Additionally, through hole 150 be may also include according to the chip attachment raw sheet 10 of the present embodiment.
I.e. with reference to Fig. 5, chip attachment raw sheet 10 also includes through hole 150, and this through hole 150 is with unit core
In the line of cut of unit chip substrate and the part of insulation division 120 intersection on the basis of the region of plate base 100
Insertion chip raw sheet 10.
Therefore, when being pre-formed through hole 150 before diced chip raw sheet 10 and cutting, it is formed with logical
The region in hole 150 is not required to separately cutting technique.Therefore, in sawing (sawing) or scribing (dicing) work
When skill is cut to aluminum and insulation division, in the part of bonding insulation division and aluminum, burr (burr) occurs,
This burr is crossed another neighbouring conductive part 110 and is led to electrical insulation breakdown phenomenon, but root
Chip attachment raw sheet 10 according to the present invention can solve the problem that problem so.
When cutting the chip attachment according to Fig. 5 with raw sheet 10 it becomes possible to manufacture inclusion as shown in Figure 4
The chip substrate of through hole 150.
In a word, according to the present invention, by realizing mounting multiple optical element cores in a substrate
The structure of piece, can make multiple chips of attachment connect with straight parallel-connection structure.Therefore, be connected in parallel
Structure is compared and can be reduced the supply magnitude of current, and result can reduce power consumption.
Additionally, although it is not shown, using according to the chip attachment of above-described embodiment substrate package light
When learning element chip, optical element chip is mounted on multiple conductive parts from each multiple conductive part quilt
Apply different electrodes.
Now, being applied through wire bonding or bonding with conductive part be capable of, and according to patch of electrode
The chip structure of dress can carry out various modifications to these electrode applying modes.
Foregoing description only relates to the description of a specific embodiment of the technical spirit of the present invention, and this
Bright those skilled in the art must not depart from the basic feature of the present invention to carry out different modifications or to change
Become.
Therefore, presently disclosed embodiment and accompanying drawing are not limited to the technology essence of the present invention
God, but in order to describe this technical spirit, and the scope of the present invention should not necessarily be limited by described embodiment and
Accompanying drawing.Protection scope of the present invention should be determined by claim, and institute in equivalent scope
The explanation having technical spirit all should fall within the scope of the present invention.
Claims (13)
1. a kind of chip attachment substrate is it is characterised in that include:
Multiple conductive parts, it applies electrode at least two chips of attachment；
Multiple insulation divisions, it is formed between described conductive part, conductive part described in electrical isolation；And
Chamber, it is comprising the region of insulation division described in conductive part described at least three and at least two
On, to inward side to the recessed space being formed with and mounting described chip.
2. chip attachment substrate according to claim 1 is it is characterised in that to across described
The neighbouring described conductive part of insulation division applies mutually different electrode.
3. chip attachment substrate according to claim 2 is it is characterised in that be mounted on described
The chip in the identical conduction portion of intracavity electrically connects in parallel and mounts, and is mounted on described chamber
The chip direct connection ground of interior different conductive parts electrically connects and mounts.
4. chip attachment substrate according to claim 2 is it is characterised in that in described intracavity
Described at least three conductive parts in, the conductive part positioned at any one end does not mount core
Piece, does not mount the conductive part of described chip and the electricity of the chip being mounted on neighbouring conductive part
Pole portion is electrically connected with.
5. chip attachment substrate according to claim 1 is it is characterised in that described insulation division
Bond to described conductive part by being formed at the anodic oxide coating of at least one side of conductive part,
And conductive part described in electrical isolation.
6. chip attachment substrate according to claim 1 is it is characterised in that also include:
Concavo-convex, it is on each described conductive part surface of the described insulation division isolation by described intracavity
On formed with predetermined height, bonding with the electrode portion being formed at described chip.
7. chip attachment substrate according to claim 6 is it is characterised in that described electrode portion
It is formed at the one side being relatively formed with the described chip on described conductive part surface in described chamber
On, described described electrode portion that is concavo-convex and being formed at described opposite side is bonding.
8. chip attachment substrate according to claim 6 is it is characterised in that also include:
Solder, it is formed on described concavo-convex surface, for welding described electrode portion and described
Concavo-convex.
9. chip attachment substrate according to claim 6 is it is characterised in that also include:
Recess, its described intracavity be recessed desired depth,
Wherein, described concavo-convex on each the described conductive part surface be formed with described recess with pre-
Fixed height is formed, bonding with the electrode portion being formed at described chip.
10. chip attachment substrate according to claim 6 is it is characterised in that also include:
Coating, on its each described conductive part surface by the described insulation division isolation of described intracavity
Formed with predetermined height, concavo-convex and described conductive part described in bonding.
11. chip attachment substrates according to claim 1 are it is characterised in that also include:
Through hole, its when described chip attachment substrate is cut according to predetermined unit region,
On the region of facet and described insulation division intersection, insulation division described in insertion and described chip
Attachment substrate.
A kind of 12. chip attachment raw sheets are it is characterised in that include:
Multiple conductive parts, it is to the unit chip substrate being mounted on zoning on chip attachment raw sheet
At least two chips apply electrodes；
Multiple insulation divisions, it is formed between described conductive part, conductive part described in electrical isolation；And
Chamber, it is comprising the region of insulation division described in conductive part described at least three and at least two
On, to inward side to the recessed space being formed with and mounting described chip.
A kind of 13. chip packages are it is characterised in that include:
Multiple conductive parts, it applies electrode to being pasted with least chip；
Multiple insulation divisions, it is formed between described conductive part, conductive part described in electrical isolation；
Chamber, it is comprising the region of insulation division described in conductive part described at least three and at least two
On, to inward side to the recessed space being formed with and mounting described chip；And
At least two chips, it is mounted on the plurality of conductive part, from the plurality of conductive part
It is applied in different electrodes respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510394273.3A CN106340577A (en) | 2015-07-07 | 2015-07-07 | Substrate for chip mounting and chip package mounted with chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510394273.3A CN106340577A (en) | 2015-07-07 | 2015-07-07 | Substrate for chip mounting and chip package mounted with chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106340577A true CN106340577A (en) | 2017-01-18 |
Family
ID=57827035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510394273.3A Pending CN106340577A (en) | 2015-07-07 | 2015-07-07 | Substrate for chip mounting and chip package mounted with chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106340577A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120126429A1 (en) * | 2010-09-09 | 2012-05-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die |
| CN103999554A (en) * | 2011-12-15 | 2014-08-20 | 普因特工程有限公司 | Optical device integrated with driving circuit and power supply circuit, method for manufacturing optical device substrate used therein, and substrate thereof |
| CN104576905A (en) * | 2013-10-10 | 2015-04-29 | 普因特工程有限公司 | Method for Mounting Chip and Chip Package |
| CN104576883A (en) * | 2013-10-29 | 2015-04-29 | 普因特工程有限公司 | Array substrate for mounting chip and method for manufacturing the same |
| CN104584244A (en) * | 2012-08-03 | 2015-04-29 | 普因特工程有限公司 | Method for manufacturing optical device and optical device manufactured by same |
-
2015
- 2015-07-07 CN CN201510394273.3A patent/CN106340577A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120126429A1 (en) * | 2010-09-09 | 2012-05-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die |
| CN103999554A (en) * | 2011-12-15 | 2014-08-20 | 普因特工程有限公司 | Optical device integrated with driving circuit and power supply circuit, method for manufacturing optical device substrate used therein, and substrate thereof |
| CN104584244A (en) * | 2012-08-03 | 2015-04-29 | 普因特工程有限公司 | Method for manufacturing optical device and optical device manufactured by same |
| CN104576905A (en) * | 2013-10-10 | 2015-04-29 | 普因特工程有限公司 | Method for Mounting Chip and Chip Package |
| CN104576883A (en) * | 2013-10-29 | 2015-04-29 | 普因特工程有限公司 | Array substrate for mounting chip and method for manufacturing the same |
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