CN113053864B - Semiconductor double-layer array flip packaging structure and packaging method thereof - Google Patents
Semiconductor double-layer array flip packaging structure and packaging method thereof Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 52
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
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Abstract
The invention provides a semiconductor double-layer array flip-chip packaging structure, which comprises a base, wherein the base comprises a substrate, a limiting fixing ring, a motor socket, an electrode strip, a heat dissipation groove and a heat dissipation module, the limiting fixing ring is fixedly connected to the upper end surface of the substrate, the motor socket is fixedly connected to the inner part of the upper end surface of the substrate, the electrode strip is fixedly connected to the side end surface of the substrate, the heat dissipation groove is formed in the lower end surface of the substrate, the heat dissipation module is fixedly connected to the inner part of the heat dissipation groove, the heat dissipation module comprises a heat dissipation water tank, a piston and a heat dissipation copper pipe, the heat dissipation copper pipe is fixedly connected to the lower end surface of the heat dissipation module, the piston is slidably connected to the inner part of the heat dissipation copper pipe, a chip fixing cover is fixedly connected to the upper end surface of the base, the chip fixing cover comprises a protection base, a transparent cover plate, a volume groove and a limiting groove, the invention effectively improves the packaging strength of a semiconductor, meanwhile, the heat dissipation capability of the package is improved, and the service life of the semiconductor is longer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor double-layer array flip packaging structure and a packaging method thereof.
Background
Semiconductor refers to a material with controllable conductivity ranging from an insulator to a conductor. From the aspects of scientific technology and economic development, the semiconductor influences the daily work and life of people, the material is not approved by the academic world until the 20 th century and the 30 th century, the LED is a semiconductor light-emitting diode established on a semiconductor transistor, the semiconductor light source adopting the LED technology has small volume, the planar packaging can be realized, the heating value is low during the work, the energy is saved, the efficiency is high, the service life of the product is long, the reaction speed is high, the product is green, environment-friendly and pollution-free, the product can be developed into a light, thin and short product, the product can be rapidly popularized once being published, the product becomes a new generation of high-quality illumination light source, the product is widely applied to our lives at present, such as traffic indicator lamps, backlight sources of electronic products, urban night scene beautifying light sources, indoor illumination and other fields, and the light-emitting semiconductor can be applied only by being packaged.
The electrode is led out by the existing luminous semiconductor package only through a gold thread, the gold thread is fine and easy to break, the gold thread breakage can lead to the failure of normal work of the luminous semiconductor, meanwhile, the existing luminous semiconductor package structure encapsulates the luminous semiconductor through resin, the problem that the circuit and maintenance cannot be checked when the luminous semiconductor device is damaged is caused, and great resource waste is caused.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a semiconductor double-layer array flip-chip packaging structure, which solves the problems that the prior light-emitting semiconductor packaging only leads out electrodes through gold wires, the gold wires are tiny and easy to break, the breakage of the gold wires can cause the light-emitting semiconductor to be incapable of working normally, meanwhile, the prior light-emitting semiconductor packaging structure encapsulates the light-emitting semiconductor by resin, which causes the problem that the circuit can not be checked and the maintenance can not be completed when the light-emitting semiconductor device is damaged, thereby causing great resource waste, and the prior light-emitting semiconductor packaging has poor self material reflection capability, has partial absorption effect on the light emitted by the light-emitting semiconductor, so that the light-emitting efficiency of the light-emitting semiconductor is not high, and the existing light-emitting semiconductor package completely seals the semiconductor, so that heat generated during the operation of the light-emitting semiconductor cannot be dissipated, and the service life of the light-emitting semiconductor is rapidly reduced at high temperature.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: a semiconductor double-layer array flip packaging structure comprises a base, wherein the base comprises a base plate, a limiting fixing ring, an electrode socket, an electrode strip, a heat dissipation groove and a heat dissipation module, the limiting fixing ring is fixedly connected to the upper end face of the base plate, the electrode socket is fixedly connected to the inner portion of the upper end face of the base plate, the electrode strip is fixedly connected to the side end face of the base plate, the heat dissipation groove is formed in the lower end face of the base plate, the heat dissipation module is fixedly connected to the inner portion of the heat dissipation groove, the heat dissipation module comprises a heat dissipation water tank, a piston and a heat dissipation copper pipe, the heat dissipation copper pipe is fixedly connected to the lower end face of the heat dissipation module, the piston is slidably connected to the inner portion of the heat dissipation copper pipe, a chip fixing cover is fixedly connected to the upper end face of the base and comprises a protection base, a transparent cover plate, a volume groove and a limiting groove, the transparent cover plate is fixedly connected to the upper end face of the protection base, the volume groove is formed in the upper end face of the protection base, the limiting groove is formed in the periphery of the lower end face of the protection base, a chip packaging block is fixedly connected to the upper end face of the base and comprises a first electrode plate, a first electrode support piece, a light-emitting semiconductor, a second electrode plate, a second electrode support piece, a first contact pin, a second electrode piece and a limiting groove, the first electrode support piece is fixedly connected to the rear end face of the first electrode plate, one side of the lower end face of the light-emitting semiconductor is fixedly connected to the upper end face of the first electrode support piece, the other side of the lower end face of the light-emitting semiconductor is fixedly connected to the upper end face of the second electrode support piece, one end of the second electrode support piece is fixedly connected to the front end face of the second electrode plate, the first contact pin is fixedly connected to the lower end face of the second electrode support piece, and the second contact pin is fixedly connected to the lower end face of the first electrode plate.
Preferably, the electrode sockets are two groups, the two groups of electrode sockets are arranged in the limiting fixing ring, the electrode strips are two groups, one end of each electrode strip is fixedly connected inside the substrate, and the electrode sockets and the electrode strips are fixedly connected inside the substrate.
Preferably, the heat dissipation water tank is located right below the chip packaging block, water is filled in the heat dissipation water tank, the heat dissipation copper pipe is separated from the interior of the heat dissipation water tank through a piston, the piston slides on the upper portion of the heat dissipation copper pipe, and at least one group of heat dissipation copper pipes is arranged.
Preferably, the chip package piece is located the volume inslot portion at base plate up end, the volume inslot wall has plated the one deck DBR, the volume inslot wall is 1 with the horizontal plane contained angle.
Preferably, the size and the position of the limiting groove are matched with those of the limiting fixing ring, and the limiting groove is fixedly connected with the limiting fixing ring through insulating glue.
Preferably, the first pin and the second pin are respectively matched with the size and the position of the group of electrode sockets.
Preferably, at least one group of the first electrode supporting sheets is fixedly connected to the rear end face of the first electrode sheet, at least one group of the second electrode supporting sheets is fixedly connected to the front end face of the second electrode sheet, and the first electrode supporting sheets and the second electrode supporting sheets are staggered on one sides of the first electrode sheet adjacent to the first contact pins.
Preferably, the upper end surfaces of the first electrode support piece and the second electrode support piece are respectively covered with a layer of copper sheet, and the first electrode support piece and the second electrode support piece are fixed on the upper end surface of the substrate through insulating glue.
Preferably, a gold wire is welded on each of the P and N electrodes of the light-emitting semiconductor, the other end of the gold wire of the P electrode is welded on the upper end face of the second electrode branch piece, and the other end of the gold wire of the N electrode is welded on the upper end face of the first electrode branch piece.
Preferably, two sides of the lower end face of the light-emitting semiconductor are respectively and fixedly connected to the copper sheets on the upper end faces of the first electrode support sheet and the second electrode support sheet through silver adhesive.
Preferably, when the light-emitting semiconductor is packaged, the first electrode plate, the first electrode support piece, the second electrode plate and the second electrode support piece are fixedly connected to the upper end face of the substrate through the electrode socket and the insulating glue, the first electrode support piece and the second electrode support piece are mutually staggered on the upper end face of the substrate, then a gold wire is respectively welded on the P electrode and the N electrode of the light-emitting semiconductor, the other ends of the gold wires on the P electrode and the N electrode of the light-emitting semiconductor are respectively welded on the copper sheets on the upper end faces of the second electrode support piece and the first electrode support piece, the two sides of the lower end face of the light-emitting semiconductor are respectively fixed on the upper end faces of the first electrode support piece and the second electrode support piece through the silver glue, then the chip fixing cover is fixed on the upper end face of the substrate through the matching of the limiting groove and the limiting fixing ring, a layer of insulating glue is uniformly coated on the upper end face of the limiting fixing ring when the chip fixing cover is fixed, and finally the heat dissipation module is fixedly connected inside the heat dissipation groove, and completing the packaging of the light emitting semiconductor.
(III) advantageous effects
The invention provides a semiconductor double-layer array flip packaging structure and a packaging method thereof, which have the following beneficial effects:
1. the device is characterized in that at least one group of first electrode branch sheets are fixedly connected with the rear end face of a first electrode sheet, at least one group of second electrode branch sheets are fixedly connected with the front end face of a second electrode sheet, the first electrode branch sheets and the second electrode branch sheets are mutually staggered on one side of the first electrode sheet adjacent to a first contact pin, two sides of the lower end face of a luminescent semiconductor are respectively and fixedly connected with the upper end faces of the first electrode branch sheets and the second electrode branch sheets, a gold thread is respectively welded on a P electrode and an N electrode of the luminescent semiconductor, the other end of the gold thread of the P electrode is welded on the upper end face of the second electrode branch sheet, the other end of the gold thread of the N electrode is welded on the upper end face of the first electrode branch sheet, two sides of the lower end face of the luminescent semiconductor are respectively and fixedly connected on the copper sheets on the upper end faces of the first electrode branch sheets and the second electrode branch sheets through silver glue, so that the electrical connection between the semiconductor and the electrode is reliable, and two groups of electrode sockets are fixedly connected in the upper end faces of a substrate, the electrode strip is fixedly connected with the electrode socket in the substrate, so that the problem that the conventional light-emitting semiconductor package only leads the electrode out through a gold thread, the gold thread is small and easy to break, and the light-emitting semiconductor cannot normally work is solved.
2. The upper end faces of the first electrode support piece and the second electrode support piece are fixed on the upper end face of the substrate through insulating cement on two sides of the lower end face of the light-emitting semiconductor, the first electrode support piece and the second electrode support piece are fixed on the upper end face of the substrate through the insulating cement, the semiconductor is fixed and tight in packaging, meanwhile, a limiting fixing ring is fixedly connected on the upper end face of the substrate, a limiting groove is formed in the lower end face of a chip fixing cover, the chip fixing cover is fixed on the upper end face of the substrate through the limiting fixing ring and the limiting groove in a matched mode, a chip packaging block is arranged inside the chip fixing cover and has good air tightness when being protected, and therefore the problem that the light-emitting semiconductor is encapsulated through resin in the existing light-emitting semiconductor packaging structure is solved, the problem that circuits cannot be checked and maintained when light-emitting semiconductor devices are damaged is caused, and great resource waste is caused.
3. Through seting up the volume groove at protection base up end, and the chip package piece is inside the volume inslot, one deck DBR has been plated at volume inslot wall simultaneously, volume inslot wall is 1 with horizontal plane contained angle for the light that the semiconductor sent can all launch away basically through the volume groove, and then effectively improved the luminous efficacy of semiconductor, thereby it is relatively poor to have solved current luminous semiconductor package self material reflectance, there is partial absorption to the light that luminous semiconductor sent, lead to the not high problem of luminous efficiency of luminous semiconductor.
4. The lower end surface of the substrate is provided with the heat dissipation groove, the heat dissipation module is fixedly connected in the heat dissipation groove, the heat dissipation module is arranged right below the chip packaging block, so that the heat dissipation module can absorb heat generated during the operation of the semiconductor, and water is filled in the heat dissipation module, a heat radiation copper pipe is fixedly connected with the lower end surface of the heat radiation module, a piston is connected in the heat radiation copper pipe in a sliding way and is arranged at the upper part of the heat radiation copper pipe, and the heat dissipation copper pipe is separated from the interior of the heat dissipation module through the piston, so that the position of the piston in the heat dissipation copper pipe can be pressed downwards when the temperature of water in the heat dissipation module rises, and then part of water can get into the inside of heat dissipation copper pipe, obtains better radiating effect to solved current light-emitting semiconductor encapsulation and sealed the semiconductor completely, the heat that the light-emitting semiconductor during operation produced can't distribute away, leads to the problem that light-emitting semiconductor life sharply descends under high temperature.
Drawings
FIG. 1 is a schematic view of the overall structure of the device body of the present invention;
FIG. 2 is a schematic view of a base structure of the device body of the present invention;
FIG. 3 is a schematic bottom view of the base of the device body of the present invention;
FIG. 4 is a schematic view of the internal structure of the heat dissipation module of the device body according to the present invention;
FIG. 5 is a schematic view of a chip fixing block of the device body according to the present invention;
FIG. 6 is a schematic diagram of a chip package block structure of the device body according to the present invention.
In the figure: the chip packaging structure comprises a base 1, a chip fixing cover 2, a chip packaging block 3, a base plate 4, a limiting fixing ring 5, an electrode socket 6, an electrode strip 7, a heat dissipation groove 8, a heat dissipation module 9, a heat dissipation water tank 10, a piston 11, a heat dissipation copper pipe 12, a protective base 13, a transparent cover plate 14, a volume groove 15, a limiting groove 16, a first electrode plate 17, a first electrode support 18, a light-emitting semiconductor 19, a second electrode plate 20, a second electrode support 21, a first contact pin 22 and a second contact pin 23.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The embodiment of the invention provides a semiconductor double-layer array flip-chip packaging structure and a packaging method thereof, wherein the semiconductor double-layer array flip-chip packaging structure comprises a base 1, the base 1 comprises a substrate 4, a limiting fixing ring 5, an electrode socket 6, an electrode strip 7, a heat dissipation groove 8 and a heat dissipation module 9, the limiting fixing ring 5 is fixedly connected with the upper end surface of the substrate 4, the electrode socket 6 is fixedly connected with the inner part of the upper end surface of the substrate 4, the electrode strip 7 is fixedly connected with the side end surface of the substrate 4, the heat dissipation groove 8 is arranged on the lower end surface of the substrate 4, the heat dissipation module 9 is fixedly connected with the inner part of the heat dissipation groove 8, the heat dissipation module 9 comprises a heat dissipation water tank 10, a piston 11 and a heat dissipation copper pipe 12, the heat dissipation copper pipe 12 is fixedly connected with the lower end surface of the heat dissipation module 9, the piston 11 is slidably connected with the inner part of the heat dissipation copper pipe 12, the upper end surface of the base 1 is fixedly connected with a chip fixing cover 2, the chip fixing cover 2 comprises a protective base 13, a transparent cover plate 14, a volume groove 15 and a limiting groove 16, the transparent cover plate 14 is fixedly connected with the upper end surface of the protection base 13, the volume groove 15 is arranged on the upper end surface of the protection base 13, the limiting groove 16 is arranged around the lower end surface of the protection base 13, the upper end surface of the base 1 is fixedly connected with the chip packaging block 3, the chip packaging block 3 comprises a first electrode plate 17, a first electrode support plate 18 and a light-emitting semiconductor 19, second electrode slice 20, second electrode support 21, first contact pin 22 and second contact pin 23, first electrode support 18 fixed connection is at first electrode slice 17 rear end face, emitting semiconductor 19 lower extreme face one side fixed connection is at first electrode support 18 up end, emitting semiconductor 19 lower extreme face opposite side fixed connection is at second electrode support 21 up end, second electrode support 21 one end fixed connection is at the preceding terminal surface of second electrode slice 20, first contact pin 22 fixed connection is at second electrode support 21 lower extreme face, second contact pin 23 fixed connection is at first electrode slice 17 lower extreme face.
Two groups of electrode sockets 6, two groups of electrode sockets 6 are arranged in a limiting fixing ring 5, two groups of electrode strips 7 are arranged, one end of each electrode strip is fixedly connected in a substrate 4, the electrode sockets 6 and the electrode strips 7 are fixedly connected in the substrate 4, a heat dissipation water tank 10 is positioned right below a chip packaging block 3, water is filled in the heat dissipation water tank 10, a heat dissipation copper pipe 12 is separated from the interior of the heat dissipation water tank 10 through a piston 11, the piston 11 slides on the upper part of the heat dissipation copper pipe 12, at least one group of heat dissipation copper pipe 12 is arranged, the chip packaging block 3 is positioned in a volume groove 15 on the upper end surface of the substrate 4, the inner wall of the volume groove 15 is plated with a DBR layer, the included angle between the inner wall of the volume groove 15 and the horizontal plane is 1 degree, the size position of a limiting groove 16 is matched with the limiting fixing ring 5, the limiting groove 16 is fixedly connected with the limiting fixing ring 5 through insulating glue, and a first contact pin 22 and a second contact pin 23 are respectively matched with the size position of one group of electrode sockets 6, at least one group of first electrode branch sheets 18 are fixedly connected with the rear end face of a first electrode sheet 17, at least one group of second electrode branch sheets 21 are fixedly connected with the front end face of a second electrode sheet 20, the first electrode branch sheets 18 and the second electrode branch sheets 21 are mutually staggered on one sides of the first electrode sheet 17 adjacent to a first contact pin 22, the upper end faces of the first electrode branch sheets 18 and the second electrode branch sheets 21 are respectively covered with a copper sheet, the first electrode branch sheets 18 and the second electrode branch sheets 21 are fixed on the upper end face of a substrate 4 through insulating glue, a gold thread is respectively welded on a P electrode and an N electrode of a luminescent semiconductor 19, the other end of the P electrode is welded on the upper end face of the second electrode branch sheets 21, the other end of the N electrode gold thread is welded on the upper end face of the first electrode branch sheets 18, two sides of the lower end face of the luminescent semiconductor 19 are respectively fixedly connected on copper sheets on the upper end faces of the first electrode branch sheets 18 and the second electrode branch sheets 21 through silver glue, when the luminescent semiconductor 19 is packaged, first, a first electrode plate 17, a first electrode support 18, a second electrode plate 20 and a second electrode support 21 are fixedly connected to the upper end face of a substrate 4 through an electrode socket 6 and insulating glue, the first electrode support 18 and the second electrode support 21 are mutually staggered on the upper end face of the substrate 4, then gold wires are respectively welded on the P pole and the N pole of a luminescent semiconductor 19, the other ends of the gold wires on the luminescent semiconductor 19P and the N pole are respectively welded on copper sheets on the upper end faces of the second electrode support 21 and the first electrode support 18, silver glue is used for respectively fixing two sides of the lower end face of the luminescent semiconductor 19 on the upper end faces of the first electrode support 18 and the second electrode support 21, then a chip fixing cover 2 is fixed on the upper end face of the substrate 4 through a limiting groove 16 and a limiting fixing ring 5 in a matching mode, and a layer of insulating glue is uniformly coated on the upper end face of the limiting fixing ring 5 when the chip fixing cover 2 is fixed, finally, the heat dissipation module 9 is fixedly connected inside the heat dissipation groove 8, and the packaging of the light emitting semiconductor 19 is completed.
In summary, in the solderless LED chip mount, first, at least one set of first electrode tabs 18 is fixedly connected to the rear end surface of the first electrode sheet 17, at least one set of second electrode tabs 21 is fixedly connected to the front end surface of the second electrode sheet 20, the first electrode tabs 18 and the second electrode tabs 21 are staggered on one side of the first electrode sheet 17 adjacent to the first contact pin 22, two sides of the lower end surface of the light emitting semiconductor 19 are respectively and fixedly connected to the upper end surfaces of the first electrode tabs 18 and the second electrode tabs 21, a gold wire is respectively welded to the P electrode and the N electrode of the light emitting semiconductor 19, the other end of the gold wire of the P electrode is welded to the upper end surface of the second electrode tab 21, the other end of the gold wire of the N electrode is welded to the upper end surface of the first electrode tab 18, and two sides of the lower end surface of the light emitting semiconductor 19 are respectively and fixedly connected to the copper sheets on the upper end surfaces of the first electrode tabs 18 and the second electrode tabs 21 through silver paste, make semiconductor and electrode electric connection reliable, simultaneously two sets of electrode socket 6 of the inside fixedly connected with of terminal surface on base plate 4, at the lower terminal surface of first electrode piece 17 and second electrode piece 20 fixed connection second contact pin 23 and first contact pin 22 respectively, first contact pin 22 and the big or small position of second contact pin 23 and electrode socket 6 looks adaptation, two sets of electrode socket 6 of the inside fixedly connected with of terminal surface on base plate 4, two sets of electrode strip 7 respectively have one end fixed connection inside base plate 4, electrode socket 6 and electrode strip 7 are at the inside fixed connection of base plate 4, make electrode strip 7 draw forth the electrode of semiconductor through electrode socket 6, thereby solved current luminous semiconductor encapsulation and only drawn forth the electrode through the gold thread, the tiny easy fracture of gold thread leads to the unable normal work problem of luminous semiconductor.
Secondly, a heat dissipation groove 8 is arranged on the lower end surface of the substrate 4, a heat dissipation module 9 is fixedly connected in the heat dissipation groove 8, the heat dissipation module 9 is arranged under the chip packaging block 3, so that the heat dissipation module 9 can absorb heat generated during the operation of a semiconductor, meanwhile, water is filled in the heat dissipation module 9, a heat dissipation copper pipe 12 is fixedly connected on the lower end surface of the heat dissipation module 9, a piston 11 is connected in the heat dissipation copper pipe 12 in a sliding manner, the piston 11 is arranged on the upper part of the heat dissipation copper pipe 12, the heat dissipation copper pipe 12 is separated from the interior of the heat dissipation module 9 through the piston 11, so that when the temperature of the interior of the heat dissipation module 9 rises, the position of the piston 11 in the heat dissipation copper pipe 12 is pressed downwards, and part of the water enters the heat dissipation copper pipe 12 to obtain better heat dissipation effect, thereby solving the problem that the prior light-emitting semiconductor packaging completely seals the light-emitting semiconductor and the heat generated during the operation cannot be dissipated out, resulting in a problem that the service life of the light emitting semiconductor is drastically reduced at high temperature.
And, through seting up volume groove 15 at protection base 13 up end, and chip package piece 3 is inside volume groove 15, one deck DBR has been plated at volume groove 15 inner wall simultaneously, volume groove 15 inner wall is 1 with the horizontal plane contained angle, make the light that the semiconductor sent can all launch out basically through volume groove 15, and then effectively improved the luminous efficacy of semiconductor, thereby it is relatively poor to have solved current luminous semiconductor package self material reflectance, there is partial absorption to the light that luminous semiconductor sent, lead to the not high problem of luminous efficiency of luminous semiconductor.
Moreover, a heat dissipation groove 8 is arranged on the lower end surface of the substrate 4, a heat dissipation module 9 is fixedly connected inside the heat dissipation groove 8, and the heat dissipation module 9 is arranged right below the chip packaging block 3, so that the heat dissipation module 9 can absorb heat generated during the operation of a semiconductor, meanwhile, water is filled inside the heat dissipation module 9, a heat dissipation copper pipe 12 is fixedly connected on the lower end surface of the heat dissipation module 9, a piston 11 is connected inside the heat dissipation copper pipe 12 in a sliding manner, the piston 11 is arranged on the upper part of the heat dissipation copper pipe 12, and the heat dissipation copper pipe 12 is separated from the inside of the heat dissipation module 9 through the piston 11, so that when the temperature of the inside of the heat dissipation module 9 rises, the position of the piston 11 inside the heat dissipation copper pipe 12 is pressed downwards, and part of water enters the inside of the heat dissipation copper pipe 12, a better heat dissipation effect is obtained, thereby solving the problem that the prior light-emitting semiconductor packaging completely seals the light-emitting semiconductor and the heat generated during the operation cannot be dissipated out, leading to a problem that the service life of the light emitting semiconductor is drastically reduced at high temperature.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A semiconductor double-layer array flip-chip packaging structure comprises a base (1), and is characterized in that: the base (1) comprises a base plate (4), a limiting fixing ring (5), an electrode socket (6), an electrode strip (7), a radiating groove (8) and a radiating module (9), wherein the limiting fixing ring (5) is fixedly connected with the upper end face of the base plate (4), the electrode socket (6) is fixedly connected inside the upper end face of the base plate (4), the electrode strip (7) is fixedly connected with the side end face of the base plate (4), the radiating groove (8) is formed in the lower end face of the base plate (4), the radiating module (9) is fixedly connected inside the radiating groove (8), the radiating module (9) comprises a radiating water tank (10), a piston (11) and a radiating copper pipe (12), the radiating copper pipe (12) is fixedly connected with the lower end face of the radiating module (9), the piston (11) is slidably connected inside the radiating copper pipe (12), and a chip fixing cover (2) is fixedly connected with the upper end face of the base (1), the chip fixing cover (2) comprises a protection base (13), a transparent cover plate (14), a volume groove (15) and a limiting groove (16), the transparent cover plate (14) is fixedly connected to the upper end face of the protection base (13), the volume groove (15) is formed in the upper end face of the protection base (13), the limiting groove (16) is formed in the periphery of the lower end face of the protection base (13), the upper end face of the base (1) is fixedly connected with a chip packaging block (3), the chip packaging block (3) comprises a first electrode plate (17), a first electrode support piece (18), a light-emitting semiconductor (19), a second electrode plate (20), a second electrode support piece (21), a first contact pin (22) and a second contact pin (23), the first electrode support piece (18) is fixedly connected to the rear end face of the first electrode plate (17), one side of the lower end face of the light-emitting semiconductor (19) is fixedly connected to the upper end face of the first electrode support piece (18), the other side of the lower end face of the light-emitting semiconductor (19) is fixedly connected to the upper end face of a second electrode support piece (21), one end of the second electrode support piece (21) is fixedly connected to the front end face of a second electrode piece (20), a first contact pin (22) is fixedly connected to the lower end face of the second electrode support piece (21), and a second contact pin (23) is fixedly connected to the lower end face of a first electrode piece (17).
2. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: electrode socket (6) are totally two sets ofly, and two sets of electrode socket (6) are inside spacing retainer plate (5), electrode strip (7) are totally two sets ofly, and one end fixed connection is inside base plate (4), electrode socket (6) and electrode strip (7) are at the inside fixed connection of base plate (4).
3. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: the chip packaging structure is characterized in that the heat dissipation water tank (10) is located right below the chip packaging block (3), water is filled in the heat dissipation water tank (10), the heat dissipation copper pipe (12) is separated from the interior of the heat dissipation water tank (10) through a piston (11), the piston (11) slides on the upper portion of the heat dissipation copper pipe (12), and at least one group of heat dissipation copper pipes (12) is arranged.
4. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: chip package piece (3) are located inside volume groove (15) at base plate (4) up end, volume groove (15) inner wall has plated the one deck DBR, volume groove (15) inner wall is 1 with the horizontal plane contained angle.
5. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: the size and the position of the limiting groove (16) are matched with those of the limiting fixing ring (5), and the limiting groove (16) is fixedly connected with the limiting fixing ring (5) through insulating glue.
6. The semiconductor double-layer array flip-chip packaging structure of claim 2, wherein: the first pin (22) and the second pin (23) are respectively matched with the size and the position of a group of electrode sockets (6).
7. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: at least one group of first electrode supporting sheets (18) is fixedly connected to the rear end face of the first electrode sheet (17), at least one group of second electrode supporting sheets (21) is fixedly connected to the front end face of the second electrode sheet (20), and the first electrode supporting sheets (18) and the second electrode supporting sheets (21) are mutually staggered on one side, adjacent to the first electrode sheet (17) and the first contact pin (22), of the first electrode sheet (17).
8. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: the upper end faces of the first electrode supporting piece (18) and the second electrode supporting piece (21) are respectively covered with a layer of copper sheet, and the first electrode supporting piece (18) and the second electrode supporting piece (21) are fixed on the upper end face of the substrate (4) through insulating glue.
9. The semiconductor double-layer array flip-chip packaging structure of claim 1, wherein: a gold wire is welded on the P electrode and the N electrode of the light-emitting semiconductor (19), the other end of the gold wire of the P electrode is welded on the upper end face of the second electrode support piece (21), and the other end of the gold wire of the N electrode is welded on the upper end face of the first electrode support piece (18).
10. The semiconductor double-layer array flip-chip packaging structure of claim 8, wherein: two sides of the lower end face of the light-emitting semiconductor (19) are respectively and fixedly connected to the copper sheets on the upper end faces of the first electrode support sheet (18) and the second electrode support sheet (21) through silver adhesive.
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