CN106326158A

CN106326158A - Method for generating clock output by means of asynchronous bus

Info

Publication number: CN106326158A
Application number: CN201610679683.7A
Authority: CN
Inventors: 朱伟; 冯威; 陈志军; 伍翔; 王晶龙; 吴艳
Original assignee: Changsha Rich Communication Technology Co Ltd
Current assignee: Changsha Rich Communication Technology Co Ltd
Priority date: 2016-08-18
Filing date: 2016-08-18
Publication date: 2017-01-11
Anticipated expiration: 2036-08-18
Also published as: CN106326158B

Abstract

The invention discloses a method for generating a clock output by means of an asynchronous bus, comprising the following steps: (1) connecting a data line DATA of a primary device to an input end of a D trigger, and connecting a write signal WE of the primary device to a latch signal LE of the D trigger, wherein an output of the D trigger serves as a clock signal CLK; (2) the primary device applies a DMA (Direct Memory Access) manner to continuously perform write operations on the asynchronous bus; and (3) the data line DATA performs electrical level overturning in each write operation, so that outputs of the D trigger are periodical clock signals CLK. According to the method disclosed by the invention, the clock signals are generated by means of a universal high-speed asynchronous bus and a simple peripheral circuit, the peripheral circuit is simple, a clock module is not required for external equipment or a slave device, cost can be lowered, and an additionally occupied area of a circuit board is not needed.

Description

The method producing clock output with asynchronous bus

Technical field

The present invention relates to a kind of method that asynchronous bus produces clock output.

Background technology

In electronic circuit, clock is a digital display circuit signal of interest, and substantial amounts of data process, transmission is required for clock Synchronization or triggering.Circuits System has many peripheral hardwares to be to need to provide clock effectively to work together.Peripheral hardware or from equipment Generally carry clock module, or provided clock to peripheral hardware by main equipment.But the not design of a lot of processors is containing numeral The output of clock signal, peripheral hardware clock module can cause each peripheral hardware will join the peripheral components such as clock crystal or crystal oscillator, This will cause cost to increase, and also take the area of circuit board simultaneously.

Summary of the invention

The technical problem to be solved is, overcomes the deficiency of above-mentioned background technology, it is provided that one asynchronous bus The method producing clock output, utilize general high-speed asynchronous bus and simple peripheral circuit to produce clock signal, outside Circuit is simple, peripheral hardware and from equipment without clock module, it is possible to reduce the cost, it is not necessary to additionally take the area of circuit board.

The present invention solves its technical problem and employed technical scheme comprise that, a kind of asynchronous bus produces the side of clock output Method, comprises the following steps:

(1) the data wire DATA by main equipment is connected to the input of d type flip flop, the write signal WE of main equipment is connected to D and touches Send out on the latch signal LE of device；The output of d type flip flop is as clock signal clk；

(2) main equipment applies dma mode to be carried out continuously write operation on asynchronous bus；

(3) data wire DATA carries out level upset when each write operation so that d type flip flop is output as periodic clock letter Number CLK.

Further, in step (2), adjust clock signal clk by adjusting the time of write operation every time on asynchronous bus Frequency.

Further, in step (3), by when on write operation adjustment data wire, the flip-flop transition of low and high level adjusts output The frequency of clock signal CLK.

Compared with prior art, advantages of the present invention is as follows: by general high-speed asynchronous bus and simple peripheral electricity Road produces stable clock signal clk, also can adjust the frequency of clock signal clk, and the frequency of clock signal clk can be by two The mode of kind is adjusted: 1, adjust the frequency of clock signal clk by adjusting the time of write operation every time on asynchronous bus； 2, by the frequency adjusting output clock signal clk flip-flop transition of low and high level on write operation adjustment data wire；If it is sharp It is controlled with multiple data wires, it is also possible to the clock signal of output multi-channel is for different peripheral hardwares.And external circuit is simple Single, coordinate software can meet various clock demand neatly, peripheral hardware and from equipment without clock module, it is possible to lower into This, it is not necessary to additionally take the area of circuit board.

Accompanying drawing explanation

Fig. 1 is the connection block diagram of the bus mode of existing intel i80.

Fig. 2 be existing intel i80 bus mode output write eDRAM.

Fig. 3 is the circuit diagram of the embodiment of the present invention.

Fig. 4 is the waveform diagram of the embodiment of the present invention.

Fig. 5 is the write operation time diagram of the embodiment of the present invention.

Detailed description of the invention

Below in conjunction with the accompanying drawings and the present invention is described in further detail by specific embodiment.

Overwhelming majority processor all has EBI, with reference to Fig. 1, Fig. 2, the most the most frequently used intel i80's Bus mode, wherein chip selection signal CS is for particular device a certain in bus, only (this enforcement when chip selection signal CS is effective Example is Low level effective), corresponding reception equipment just starts there is write signal WE response, and accepts data corresponding to write signal WE (the present embodiment is that write signal WE rising edge gathers data/address bus).If chip selection signal CS is invalid, even if write signal WE has Making, be considered as the equipment for other, accepting device corresponding for this chip selection signal CS will not do to be comprehended.Generally data/address bus is all Being to connect high-speed peripheral, bus speed is than higher speed.If it is suitable that general high-speed asynchronous bus can be utilized to produce Clock signal, the design of a lot of circuit application schemes can be offered convenience by this.

With reference to Fig. 3, the present embodiment by general high-speed asynchronous bus and simple peripheral circuit produce needs time Clock signal, its method comprises the following steps:

(1) the data wire DATA0 by main equipment is connected to the input of d type flip flop, the write signal WE of main equipment is connected to D and touches Send out on the latch signal LE of device；The output of d type flip flop is as clock signal clk；If many data lines DATA is respectively coupled to many Individual d type flip flop, then can produce the clock signal of multichannel；

Common asynchronous bus write operation has unstability, the distribution of system multiplex, the task of different priority levels or The processor write operation interval interrupting all causing main equipment is uncertain, so that the output signal time cycle produced is unstable Fixed.All can support the working method of DMA at present in the processor of main flow, the transmission of data is not relying on a large amount of Jie of processor Enter, the dma controller in processor directly administer bus.The transmission means of DMA is utilized: processor need to for this present embodiment The DSR wanted, then DMA can be responsible for ceaselessly exporting data with write operation, sequential is stablized and high speed, finally The signal stablizing frequency is produced under outside d type flip flop effect；

Owing to clock frequency is according to different peripheral equipment requirements, frequency also has a difference, the most same outer is located at the different time also Need different clock frequencies, therefore the frequency adjusting clock signal clk is necessary.

In step (2), the frequency of clock signal clk can be adjusted by adjusting the time of write operation every time on asynchronous bus Rate.The time of write operation is adjusted by the time sequence parameter of software arrangements write operation every time；Generally write operation is to have several sequential Parameter can adjust, with reference to Fig. 5, a T_clkClock cycle is by two T_WEWrite cycle time determines, and a T_WE's Time is main by T again_WS、T_WLAnd T_CHDetermine, T_WSRepresent that chip selection signal CS effectively arrives the write signal WE effective time；T_WLRepresent Write signal WE low level time；T_CHRepresent chip selection signal CS high level time.Clock signal in Fig. 5 can be calculated by formula Frequency F=1/2* (the T of CLK_WS+T_WL+T_CH)。T_WS、T_WLAnd T_CHThree variablees are to arrange adjustment in the processor of main equipment , therefore value is set by change and adjusts the final frequency of output.

(3) data wire DATA carries out level upset when each write operation so that when d type flip flop is output as periodic Clock signal CLK；If data wire DATA adjusts time and the period of change of low and high level by write operation, then can produce different frequency The periodic timing signal CLK of rate and dutycycle.

When each write operation, write signal WE makes d type flip flop in the signal level of outfan meeting latch input terminal DATA0. Illustrate as a example by Fig. 4: for the first time during write operation, the DATA0 signal of data/address bus is 0, then the outfan of d type flip flop becomes low electricity Flat, and latch maintenance low level always；For the second time during write operation, DATA0 signal becomes 1, and the outfan of trigger the most then becomes Becoming high level, and latch maintenance high level always, when each write operation, DATA0 can change repeatedly, then d type flip flop is defeated Going out end and produce the waveform of low and high level mechanical periodicity, namely the clock signal clk needed, the clock frequency of clock signal clk is The half of write signal WE period frequency.

In step (3), adjusted by write operation and adjust output clock signal the flip-flop transition of low and high level on data wire The frequency of CLK.If the output signal of DATA0 is if the clock frequency that 0-0-1-1-0-0-1-1 then exports becomes write cycle time 1/4.Need several write cycle times by calculating the height change of clock output, just can obtain the frequency of clock signal clk for somewhat One of write cycle time.

Stable clock signal clk can be obtained by the inventive method, also can adjust the frequency of clock signal clk, clock The frequency of signal CLK can be adjusted by two ways: 1, by adjusting the time of write operation every time on asynchronous bus Adjust the frequency of clock signal clk；2, by when on write operation adjustment data wire, the flip-flop transition of low and high level adjusts output The frequency of clock signal CLK；It is controlled if, with multiple data wires, it is also possible to the clock signal of output multi-channel is for outside different If using.And external circuit is simple, coordinate software can meet various clock demand neatly, peripheral hardware and from equipment without from Band clock module, it is possible to reduce the cost, it is not necessary to additionally take the area of circuit board.

Those skilled in the art can carry out various modifications and variations to the present invention, if these amendments and modification are at this Within the scope of invention claim and equivalent technologies thereof, then these amendments and modification are also within protection scope of the present invention.

The prior art that the content not described in detail in description is known to the skilled person.

Claims

1. the method producing clock output with asynchronous bus, it is characterised in that comprise the following steps:

2. the method producing clock output with asynchronous bus as claimed in claim 1, it is characterised in that: in step (2), pass through The time adjusting write operation every time on asynchronous bus adjusts the frequency of output clock signal clk.

3. the method producing clock output with asynchronous bus as claimed in claim 1 or 2, it is characterised in that: in step (3), Adjusted by write operation and adjust the frequency of output clock signal clk the flip-flop transition of low and high level on data wire.