CN105320635A - Method for realizing MAX 2769 interface control by adopting universal digital I/O - Google Patents
Method for realizing MAX 2769 interface control by adopting universal digital I/O Download PDFInfo
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- CN105320635A CN105320635A CN201510582399.3A CN201510582399A CN105320635A CN 105320635 A CN105320635 A CN 105320635A CN 201510582399 A CN201510582399 A CN 201510582399A CN 105320635 A CN105320635 A CN 105320635A
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- max2769
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The present invention belongs to the technical field of realizing interface control by using a universal digital I/O, and relates to a method for realizing MAX 2769 interface control by adopting a universal digital I/O. The method comprises following steps that functions of output pins of the universal digital I/O are planned and the output pins are connected with MAX 2769 serial interface terminals; and according to an MAX 2769 serial interface timing sequence and a serial-parallel data conversion requirement, interface control is carried out by serial data transmission. According to the method provided by the present invention, the range of optional devices of the universal I/O is wide; the hardware connection is directly visible, simple and reliable; the problems of complex design and long production implementation cycle of FPGA and CPLD circuits are avoided; SPI control word sending is achieved by an inexact but synchronous timing relationship to meet a control requirement; control functions which usually can only be implemented by using FPGA and CPLD are provided; and the method is simple in design and economical in implementation, and can be used for a variety of chip controls which need an SPI interface for status setting.
Description
Technical field
The invention belongs to electronic measuring technology field, relate to a kind of method adopting general digital I/O to realize the method for MAX2769 Interface Controller.
Background technology
MAX2769 is the nautical star signal receiving chip that MAXIM company produces, and is widely used in the reception of GPS, GLONASS and Galileo navigation star signal, measurement and location.Its function comprises the sampling output etc. of radio frequency amplification, intermediate frequency conversion, the highest three bit digital.Need to be configured it by three special line serial port circuits to the control of its internal state, content comprises running parameters such as arranging its gain, bandwidth, signal branch; Usually need to adopt the technical design special interface circuits such as FPGA, CPLD, also need to adopt crystal oscillator to realize clock signal, hardware makes construction cycle length, software programming realization is complicated.
Summary of the invention
For convenience of in engineering practice to SPI Interface Controller, the invention provides a kind of method adopting general digital I/O to realize MAX2769 Interface Controller, technical scheme is as follows:
Adopt a method for general digital I/O Interface realization MAX2769 Interface Controller, comprise the steps:
(1) general digital I/O exports pin functionality planning and is connected with MAX2769 serial line interface terminal; The ground wire of described MAX2769 interface, chip select line, clock line, data line export stitch with the general digital I/O of planning and are directly connected, middle without driving buffer circuit, and the free time of MAX2769 chip, pass broken string are directly connected with the general digital I/O digital pin of planning, middle without driving buffer circuit;
(2) according to MAX2769 serial line interface sequential and serial parallel data conversion requirements, sent by serial data and realize Interface Controller; The realization of clock exports low and high level change by general digital I/O and realizes, the low and high level duration be not less than the condition of 25 μ s under do not require that absolute time is accurate; Signal set up retention time non-precision but relative time clock along meeting MAX2769 3-line serial interface timing requirements.
Preferably, in described step (2) forward in sequential, the control word low level of a high position for each control word of MAX2769 chip in sequential rearward, each control word is one group by 32 and sends.
Preferably, be that foundation and the retention time minimum interval unification of the choosing of clock concrete in described step (2), sheet or signal are set to 100 μ s.
Preferably, control directly to be adjusted by corresponding I/O stitch level to the free time of MAX2769 chip, turn-off function in described step (2), select with the sheet of 3-line serial interface, clock and data line state be irrelevant.
Beneficial effect:
A kind of method adopting general digital I/O to realize MAX2769 Interface Controller that the present invention relates to, wherein the Alternative devices of general purpose I/O is extensive, signal wiring is directly perceived and simple and reliable, avoid a difficult problem for FPGA, CPLD circuit design complexity, making length performance period, by non-precision but synchronous sequential relationship realize SPI control word send, meet control overflow, usually the controlling functions needing FPGA, CPLD to realize is provided, simplicity of design, realize economical, can be used for the multiple chip controls needing to be undertaken by SPI interface state setting.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is MAX2769 interface connection diagram;
Fig. 2 is MAX2769 interface sequence figure;
Fig. 3 is that data of the present invention send realization flow.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, be clearly and completely described below to the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Adopt a method for general digital I/O Interface realization MAX2769 Interface Controller, comprise the steps:
(1) general digital I/O exports pin functionality planning and is connected with MAX2769 serial line interface terminal; The ground wire of described MAX2769 interface, chip select line, clock line, data line export stitch with the general digital I/O of planning and are directly connected, middle without driving buffer circuit, and the free time of MAX2769 chip, pass broken string are directly connected with the general digital I/O digital pin of planning, middle without driving buffer circuit;
(2) according to MAX2769 serial line interface sequential and serial parallel data conversion requirements, sent by serial data and realize Interface Controller; The realization of clock exports low and high level change by general digital I/O and realizes, the low and high level duration be not less than the condition of 25 μ s under do not require that absolute time is accurate; Signal set up retention time non-precision but relative time clock along meeting MAX2769 3-line serial interface timing requirements.
In described step (2) forward in sequential, the control word low level of a high position for each control word of MAX2769 chip in sequential rearward, each control word is one group by 32 and sends, be that foundation and the retention time minimum interval unification of the choosing of clock concrete in described step (2), sheet or signal are set to 100 μ s, control directly to be adjusted by corresponding I/O stitch level to the free time of MAX2769 chip, turn-off function in described step (2), select with the sheet of 3-line serial interface, clock and data line state be irrelevant.
Embodiment 1:
Computing machine is controlled MAX2769A by USB9812C, its hardware interface as shown in Figure 1, in figure, AC represents zero live wire connecing alternating current, FG represents the ground wire connecing alternating current, general purpose I/O and outward appearance are that the port corresponding relation of parallel port MAX2769A sees the following form, this design mainly considers control signal and grounded circuit, realizes the function of basic controlling.
Port corresponding relation
According to the connection of Fig. 1, the I/O output level of USB9812C just can by form on MAX2769 board as the interface of parallel port, and directly the sheet of control MAX2769A chip selects (CS), data (DATA), clock (SCLK), idle (IDLE) and turns off (SHDN) stitch.According to certain sequential, the I/O of control USB9812C exports Transistor-Transistor Logic level, transmits control signal and required data to MAX2769, just can reach the object changing MAX2769 duty.
1, MAX2769A chip SPI timing requirements
MAX2769A can configure its mode of operation by a serial programmable interface, and this interface is made up of three lines: SCLK (serial clock), CS (chip selection signal) and SDATA (serial data).PLL, AGC, output module selection etc. are all performed by this interface, when setting low Deng chip selection signal, the control data of one 32 (upper byte D27 is front) passes through the synchronous of serial clock, and order is input to the serial shift register of MAX2769A inside.Interface sequence specification, representative value and retention time to ask for an interview to following Fig. 2 and following table.
MAX2769A interface sequence
| Symbol | Explanation | Representative value | Unit |
| t CSS | CS signal negative edge is gone up along the time interval to first SCLK signal | 10 | ns |
| t DS | The time interval that data are set up to serial clock | 10 | ns |
| t DH | Data are to the clock retention time | 10 | ns |
| t CH | Serial clock high-level pulse width | 25 | ns |
| t CL | Time clock low level width | 25 | ns |
| t CSH | Last SCLK signal is gone up along going up along the time interval to CS signal | 10 | ns |
| t CSW | CS high-level pulse width | 1 | clock |
2, the realization of data transmission
The register of MAX2769 is set to 32, high 28 represent settings, low 4 is register address, need the Data Input Interface (SDATA) this 32 bit data being input in a serial fashion MAX2769, that is the data on the stitch needing the input of the data of USB9812C and MAX2769 to be connected become high level for a moment according to the requirement of 32 bit data, become low level for a moment, certain this change will coordinate the level of other stitch to change, to meet above-mentioned timing requirements.USB9812C has 7 tunnel available digital Transistor-Transistor Logic levels to export, the requirement of MAX2769 incoming level can be met, therefore hardware no longer needs the level-conversion circuits such as driving or buffering, directly the USB9812C stitch of needs can be received the corresponding stitch of MAX2769 control interface, then in a program by certain time interval, the level changing USB9812C digital output pin pin can realize serial sequential, and if Fig. 3 is serial sequential process flow diagram, various retention time unification is set to 100 μ s.
In program, the stand-by period realizes utility debug function tic, toc, monitor toc in a cycle and enter the front tic mistiming arranged of circulating, although this mode timing accuracy is not high, such as on this project computing machine used, precision is about 6 μ s, but it is enough for realizing serial sequential and meeting the time requirement showing " MAX2769 interface sequence ", shown in Fig. 3 flow process, 3 groups of register data whole end of transmission used times are about 10ms, because state adjustment frequency is lower, substantially only arrange once when program initialization runs, therefore this time loss is complete acceptable in engineering practice.
A kind of method adopting general digital I/O to realize MAX2769 Interface Controller that the present invention relates to, wherein the Alternative devices of general purpose I/O is extensive, signal wiring is directly perceived and simple and reliable, avoid a difficult problem for FPGA, CPLD circuit design complexity, making length performance period, by non-precision but synchronous sequential relationship realize SPI control word send, meet control overflow, usually the controlling functions needing FPGA, CPLD to realize is provided, simplicity of design, realize economical, can be used for the multiple chip controls needing to be undertaken by SPI interface state setting
Above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (4)
1. adopt a method for general digital I/O Interface realization MAX2769 Interface Controller, it is characterized in that, comprise the steps:
(1) general digital I/O exports pin functionality planning and is connected with MAX2769 serial line interface terminal; The ground wire of described MAX2769 interface, chip select line, clock line, data line export stitch with the general digital I/O of planning and are directly connected, middle without driving buffer circuit, and the free time of MAX2769 chip, pass broken string are directly connected with the general digital I/O digital pin of planning, middle without driving buffer circuit;
(2) according to MAX2769 serial line interface sequential and serial parallel data conversion requirements, sent by serial data and realize Interface Controller; The realization of clock exports low and high level change by general digital I/O and realizes, the low and high level duration be not less than the condition of 25 μ s under do not require that absolute time is accurate; Signal set up retention time non-precision but relative time clock along meeting MAX2769 3-line serial interface timing requirements.
2. the method adopting general digital I/O to realize MAX2769 Interface Controller as claimed in claim 1, be characterised in that, in sequential rearward, each control word is one group by 32 and sends forward in sequential, the control word low level of a high position for each control word of MAX2769 chip in described step (2).
3. the method adopting general digital I/O to realize MAX2769 Interface Controller as claimed in claim 1, is characterised in that, is that the foundation of the choosing of clock concrete in described step (2), sheet or signal and retention time minimum interval unification are set to 100 μ s.
4. the method adopting general digital I/O to realize MAX2769 Interface Controller as claimed in claim 1, be characterised in that, control directly to be adjusted by corresponding I/O stitch level to the free time of MAX2769 chip, turn-off function in described step (2), select with the sheet of 3-line serial interface, clock and data line state be irrelevant.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109324987A (en) * | 2018-09-27 | 2019-02-12 | 青岛海信电器股份有限公司 | Sequential control method, device and the electronic equipment of analogue communication interface |
| CN112506838A (en) * | 2021-02-03 | 2021-03-16 | 青岛鼎信通讯股份有限公司 | SPI clock synchronization method applied to IR46 electric meter calibrating device |
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| EP2438851A2 (en) * | 2010-10-08 | 2012-04-11 | Cardiac Science Corporation | Microcontrolled electrocardiographic monitoring circuit with differential voltage encoding |
| CN102890278A (en) * | 2011-07-19 | 2013-01-23 | 哈尔滨伟方智能科技开发有限责任公司 | MIMU (Micro Inertial Measurement Unit) fully-integrated navigation system based on FPGA (Field Programmable Gate Array) Beidou |
| CN204536559U (en) * | 2015-04-10 | 2015-08-05 | 上海工程技术大学 | A kind of satnav radio-frequency unit based on ARM |
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2015
- 2015-09-14 CN CN201510582399.3A patent/CN105320635A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2438851A2 (en) * | 2010-10-08 | 2012-04-11 | Cardiac Science Corporation | Microcontrolled electrocardiographic monitoring circuit with differential voltage encoding |
| CN102890278A (en) * | 2011-07-19 | 2013-01-23 | 哈尔滨伟方智能科技开发有限责任公司 | MIMU (Micro Inertial Measurement Unit) fully-integrated navigation system based on FPGA (Field Programmable Gate Array) Beidou |
| CN204536559U (en) * | 2015-04-10 | 2015-08-05 | 上海工程技术大学 | A kind of satnav radio-frequency unit based on ARM |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109324987A (en) * | 2018-09-27 | 2019-02-12 | 青岛海信电器股份有限公司 | Sequential control method, device and the electronic equipment of analogue communication interface |
| CN112506838A (en) * | 2021-02-03 | 2021-03-16 | 青岛鼎信通讯股份有限公司 | SPI clock synchronization method applied to IR46 electric meter calibrating device |
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Application publication date: 20160210 |