CN204203685U

CN204203685U - A kind of circuit structure of electromechanical integration equipment

Info

Publication number: CN204203685U
Application number: CN201420614979.7U
Authority: CN
Inventors: 胡金高; 孙敏; 陈熙亮; 周胡平; 高由先; 李为国
Original assignee: FUZHOU RAINBOW COMPUTERIZED TECHNOLOGY Co Ltd
Current assignee: Fuzhou Ruineng Control Technology Co ltd
Priority date: 2014-10-23
Filing date: 2014-10-23
Publication date: 2015-03-11
Anticipated expiration: 2024-10-23

Abstract

The utility model discloses a kind of circuit structure of electromechanical integration equipment, comprise a CPLD, the 2nd CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data line; A described CPLD is electrically connected the first Low Voltage Differential Signal LVDS interface; Described 2nd CPLD is electrically connected the second Low Voltage Differential Signal LVDS interface; Described first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface are electrically connected by clock line and data line.The utility model utilizes LVDS technology, realize 8 a small amount of lines, pack by the data of CPLD integrated technology and unpack, to transmit two local a large amount of signals separated by a distance, routing complexity with reduce engine in electrical integrated and miscellaneous equipment, simultaneously to the reliability of system, reduce troubleshooting time there is obvious effect.

Description

A kind of circuit structure of electromechanical integration equipment

Technical field

The utility model relates to circuit structure, is specifically related to a kind of circuit structure of electromechanical integration equipment.

Background technology

Along with the raising of labor cost, the automatically processing device of requirement becomes increasingly complex, and simultaneously along with a large amount of of Embedded computer system popularize, distributed AC servo system becomes inexorable trend.Therefore in the dcs of complexity, complicacy and the reliability of wiring just become very outstanding, traditional method, each signal demand of usual outside wire, another one place (as scene) is moved to from a place (as Main Control Tank), if system has hundreds of root signal, even thousands of, this brings great difficulty certainly to remote wiring.As in embroidery machine, pattern sewing machine and vamp machine system, be arranged in on-the-spot signal to have: head signal, framework four-way are offside, trimming, button line, hook line, main shaft signal, main spindle's, frame position, clamp, etc., if all connected from main control CPU, its wiring mixes well imagines, tradition often needs master control to be positioned over scene, and this makes troubles to again the operability (figure display, the operation of various data card, network linking operation etc.) of master control.

Utility model content

The purpose of this utility model utilizes LVDS technology, realizes a small amount of several threads, is conciliate wrap in a large amount of signal of two localized transmissions separated by a distance by the packing of data, the routing complexity with reduce engine in electrical integrated and miscellaneous equipment.

The utility model, for the problems referred to above, provides a kind of circuit structure of electromechanical integration equipment.

According to an aspect of the present utility model, provide a kind of circuit structure of electromechanical integration equipment, comprise a CPLD, the 2nd CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data line; A described CPLD is electrically connected the first Low Voltage Differential Signal LVDS interface; Described 2nd CPLD is electrically connected the second Low Voltage Differential Signal LVDS interface; Described first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface are electrically connected by clock line and data line.

Advantage of the present utility model:

The utility model utilizes LVDS technology, pack by the data of CPLD integrated technology and unpack, to transmit two local a large amount of signals (as 200) separated by a distance, routing complexity with reduce engine in electrical integrated and miscellaneous equipment, simultaneously to the reliability of system, reduce troubleshooting time there is obvious effect.

Except object described above, feature and advantage, the utility model also has other object, feature and advantage.Below with reference to figure, the utility model is described in further detail.

Accompanying drawing explanation

The accompanying drawing forming a application's part is used to provide further understanding of the present utility model, and schematic description and description of the present utility model, for explaining the utility model, is not formed improper restriction of the present utility model.

Fig. 1 is the electrical block diagram of a kind of electromechanical integration equipment of the present utility model;

Fig. 2 is the method for work knot of the circuit of a kind of electromechanical integration equipment of the present utility model

Structure process flow diagram.

Embodiment

In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.

With reference to figure 1, the circuit structure of a kind of electromechanical integration equipment as shown in Figure 1, comprises a CPLD, the 2nd CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data line; A described CPLD is electrically connected the first Low Voltage Differential Signal LVDS interface; Described 2nd CPLD is electrically connected the second Low Voltage Differential Signal LVDS interface; Described first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface are electrically connected by clock line and data line.

With reference to figure 2, the method for work of foregoing circuit structure as shown in Figure 2, comprises the following steps:

S1, when all multi signal will be sent to the second ground from the first ground, has all multi signal will be sent to the first ground from the second ground simultaneously, packs, form the serial data of a string length at a CPLD at the first place to signal group; Adding check code at each serial data rear portion simultaneously, by using the high-frequency clock of CPLD inside, serial data being sent in the mode of a time clock data bit;

S2, in order to the reliability of long-distance transmissions, by the first Low Voltage Differential Signal LVDS interface by signal synchronism output;

S3, be located in second and first carry out level translation to the LVDS Low Voltage Differential Signal of the first ground transmission, the clock that utilization is brought and data are located in second the 2nd CPLD moving into the second ground serially;

S4, the second the 2nd CPLD be located in are after all receiving all signals, and code of testing is checked;

S5, in the incorrect situation of check code, the reception value that local data group retains last time is constant; When check code is correct, the new data set of reception is located in second and presents;

S6 is when being sent to the first ground from the second ground to signal group, identical with above-mentioned pattern.

Ultimate principle of the present utility model describes as follows: preferably have the second point (on-the-spot board) that 100 (referring between 10-1000) signals send away from the first point (master control), there is 100 Information Monitoring points second point from afar to deliver to the first point simultaneously, if adopt classic method at least to want 200 lines, obviously too complicated; If employing this method, can by the CPLD of monolithic (Complex programmable logical device) chip 100 data formed a tape verifying and packet, by LVDS (Low Voltage Differential Signal), pass with serial ports at a high speed, also the CPLD of a monolithic is had in other one end, the tape verifying received and packet carry out CPLD and unpack, and points 100 independently signal present, just achieve 100 signal transmission between two places; The transmission that rightabout 100 signals are also of this sort, so just achieves the mutual biography of 200 signals.

In LVDS serial ports transmittance process, in order to ensure the promptness of Signal transmissions, sufficiently high speed should be adopted, such as each signal wire time delay is no more than for ten thousand/second, then the standard baud rate of LVDS serial ports should be not less than 2MHz, usually can adopt the general Internet Engineering Task speed of tens to hundreds of MHz, be convenient to wire rod buying and implement.

LVDS represents differential signal, and need two lines, consider two-way clock and data-signal, therefore the program needs 8 lines altogether.Can share with internet line.

The utility model utilizes LVDS technology, realize 8 a small amount of lines, pack by the data of CPLD integrated technology and unpack, to transmit two local a large amount of signals (as 200) separated by a distance, routing complexity with reduce engine in electrical integrated and miscellaneous equipment, simultaneously to the reliability of system, reduce troubleshooting time there is obvious effect.

The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.

Claims

1. a circuit structure for electromechanical integration equipment, is characterized in that, comprises a CPLD, the 2nd CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data line; A described CPLD is electrically connected the first Low Voltage Differential Signal LVDS interface; Described 2nd CPLD is electrically connected the second Low Voltage Differential Signal LVDS interface; Described first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface are electrically connected by clock line and data line.