CN208480056U - A kind of pcb board of deciphering machine control panel - Google Patents
A kind of pcb board of deciphering machine control panel Download PDFInfo
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- CN208480056U CN208480056U CN201820847808.7U CN201820847808U CN208480056U CN 208480056 U CN208480056 U CN 208480056U CN 201820847808 U CN201820847808 U CN 201820847808U CN 208480056 U CN208480056 U CN 208480056U
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Abstract
The utility model discloses a kind of pcb board of deciphering machine control panel, the pcb board is N layers, N is the even number not less than 4, double-core ARM cpu chip, DDR3 memory chip, gigabit ethernet interface, QSPI interface etc. are all set in the top layer of pcb board, reflection compensation resistance is set to the bottom of pcb board, the power supply area of kernel needed for bus plane marks various chips and periphery, Vtt are placed on bottom, and Vref is placed on the region specially marked in stratum；It is connected to the middle layer that the data line between double-core ARM cpu chip and DDR3 memory chip, address wire and control line are arranged between top layer and bottom, connecting line, double-core ARM cpu chip between the connecting line of address wire, control line between two panels DDR3 memory chip, double-core ARM cpu chip and gigabit Ethernet mouth and the connecting line between QSPI interface are also disposed at the middle line layer between top layer and bottom.The utility model enables the control panel even running for carrying double-core ARM cpu chip.
Description
Technical field
The utility model relates to a kind of pcb boards, specifically, are a kind of pcb boards of deciphering machine control panel, belong to pcb board
Technical field.
Background technique
Network cipher refers to cryptographic system used in information system security under protection network environment, its main feature is that application is wide
It is general, enormous amount；The decoding difficulty of subnetwork password is big；Dedicated network password type is more, variation is fast, scouts and studies very
It is difficult.Currently, can be used for the commercially produced product that common Information System Password restores in the world is broadly divided into two classes: pure software system
With the hardware system developed based on FPGA technology.
Hardware system based on FPGA technology mainly has TACC1441 hardware accelerator and the ICS company of Tableau company
Cobra hardware accelerator.Relative to pure software system, the performance of these products improves a lot, but considers network cipher
Huge operand necessary to decoding, the above product is still difficult to reach to be required under battle conditions, and expensive, large-scale integrated at
This is excessively high, and commercialization promotional value is limited.
For the defect for the hardware system developed based on FPGA technology, the network that applicant has developed a kind of novel concept is close
Code recovery system carries out big complexity operation based on asic chip, using networking general frame, applied cryptography technology it is multinomial
Newest research results greatly improve code breaking speed in conjunction with means such as special purpose system library, rainbow tables, can be directed to more than ten
The different cryptographic system of kind carries out high speed decoding, effectively prevents the defect of existing product, breaches large-scale commercial application
Bottleneck.
The days such as above-mentioned network cipher recovery system includes control panel, and the address for being responsible for cryptanalysis machine is distributed, authorization is arranged
The transmitting-receiving and chip operation control of normal management work and task data.Double-core ARM cpu chip, two panels are carried on control panel
DDR3 memory, standard gigabit ethernet interface and 8 QSPI interfaces etc..Control panel is using Xilinx company ZYNQ-7000 series
In XC7Z020-2CLG484I double-core ARM cpu chip be core, the gigabit network interface for using the ARM at the end PS included, USB
OTG, TF card, jtag interface etc., network interface needs reconfigure in design before solving, and reliability, stability are relatively low, open
The problems such as hair period is long.When the pcb board to control panel is designed, in the case where scalability is reinforced, the design of PCB does not have
Ready-made is available, after carrying out satisfactory cutting to peripheral interface, needs to carry out completely new PCB design, to guarantee that PCB is flat
Steady operation.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of pcb board of deciphering machine control panel, make to carry double-core ARM
The control panel of cpu chip being capable of even running.
In order to solve the technical problem, the technical solution adopted in the utility model is: a kind of PCB of deciphering machine control panel
Plate carries double-core ARM cpu chip, DDR3 memory chip, gigabit ethernet interface, QSPI interface etc. on deciphering machine control panel,
And the control pin and address pin of DDR3 memory chip are connected to power supply Vtt by reflection compensation resistance, while in DDR3
It deposits chip and connects same reference power source Vref, double-core ARM cpu chip with the memory reference voltage pin of double-core ARM cpu chip
Communicated to connect by QSPI bus interface and deciphering chip, double-core ARM cpu chip by gigabit ethernet interface and gigabit with
Too net transceiver communications connect, and the pcb board is N layers, and N is the even number not less than 4, double-core ARM cpu chip, DDR3 memory core
Piece, gigabit ethernet interface, QSPI interface etc. are all set in the top layer of pcb board, and reflection compensation resistance is set to the bottom of pcb board
Layer, the power supply area of core power needed for bus plane marks various chips and peripheral power supply, Vtt are placed on bottom, and Vref is put
Set the region specially marked in the earth formation；It is connected to data line between double-core ARM cpu chip and DDR3 memory chip, address
Line and control line are arranged in the intermediate wiring layer between top layer and bottom, address wire, control between two panels DDR3 memory chip
Connecting line, double-core ARM cpu chip and QSPI between the connecting line of line, double-core ARM cpu chip and gigabit Ethernet mouth connect
Connecting line between mouthful is also disposed at the intermediate wiring layer between top layer and bottom.
The pcb board of deciphering machine control panel described in the utility model, pcb board are 8 layers, respectively top layer, the second layer, third
Layer, bus plane, the 4th layer, stratum, layer 5 and bottom, low 8 of the data line between double-core ARM cpu chip and DDR3 chip
The line group of position, 2 address wires, the address wire between 1 control line and two panels memory, control line 13 connecting lines be arranged in
Third layer；The line group of the most-significant byte of data line between double-core ARM cpu chip and DDR3 chip and 2 address wires, 3 controls
13 articles of connecting lines of address wire, control line between line, 2 articles of control clock differential lines and two panels memory are arranged in the 4th layer；
11 address wires, 5 control lines and 1 RESET line between all double-core ARM cpu chips of layer 5 and DDR3 chip.
Such 15 address wires, 9 control lines are distributed over 3 intermediate cloth plus 2 control clock differential lines and 1 RESET line
Line layer suffers, top layer and the floor file of bottom free area, takes full advantage of inner space between CPU and DDR3 chip, ensure that letter
Number integrality.
The pcb board of deciphering machine control panel described in the utility model, the data between double-core ARM cpu chip and DDR3 chip
Address wire, control line between line, address wire, control line and two panels memory is according to grouping equal length treatment, wherein each memory
One group of the least-significant byte of the data line of chip, the line in another group of the most-significant byte of data line, one group, every group of address wire, control line are isometric.
The pcb board of deciphering machine control panel described in the utility model, bus plane mark core power needed for chip and periphery electricity
The power supply area in source, Vtt are placed on bottom, and Vref is placed on the region specially marked in stratum, connects on each pin of Vref
Connect the decoupling capacitor of 0.1uf；Double-core ARM cpu chip, DDR3 chip each power pins be all connected with a filter capacitor,
Storage capacitor is arranged in double-core ARM cpu chip and filter capacitor periphery, and decoupling capacitor, filter capacitor, storage capacitor are set to PCB
The bottom of plate.
The pcb board of deciphering machine control panel described in the utility model, gigabit ethernet interface and gigabit ethernet transceiver it
Between be equipped with 4 pairs of connecting lines, 4 pairs of connecting lines require transmission data, 4 pairs of connecting lines require according to difference cabling requirement into
Row wiring, each pair of line are that the two lines in one group, every group are isometric.
The pcb board of deciphering machine control panel described in the utility model, layer not floor file and power supply below gigabit ethernet interface.
The pcb board of deciphering machine control panel described in the utility model, double-core ARM cpu chip are provided with extension mouth, extend mouth
Connecting line between double-core ARM cpu chip is distributed in the second layer, third layer, the 4th layer and the layer 5 of pcb board, the second layer
It there also is provided JATG mouthfuls of line, the rest part floor file of the second layer.
The utility model has the beneficial effects that PCB described in the utility model is set as 8 layers, specific placement bus plane and bottom
Layer can be adequately isolated wiring layer, reduce the influence to signal integrity.In order to keep the stabilization of power supply, bus plane is marked respectively
The power supply area of core power and peripheral power supply needed for kind chip, Vtt is placed on bottom and Vref is placed in stratum specially
The region marked connects the decoupling capacitor of 0.1uf on each pin of Vref；Double-core ARM cpu chip, DDR3 chip it is every
A power pins are all connected with a filter capacitor, and storage capacitor is arranged in double-core ARM cpu chip and filter capacitor periphery, power supply
Stabilization is to guarantee the key point of PCB even running.The utility model is related to keeping signal integrity by wiring, passes through power supply
Design guarantees power supply even running, to make the control panel even running for carrying double-core ARM cpu chip.
Detailed description of the invention
Fig. 1 is the circuit diagram that double-core ARM cpu chip is connect with DDR3 chip；
Fig. 2 is the circuit connection diagram of gigabit ethernet interface and gigabit ethernet transceiver；
Fig. 3 is the schematic diagram of the Vref power supply area of bus plane setting；
Fig. 4 is the cabling schematic diagram of pcb board third layer；
The cabling schematic diagram that Fig. 5 is the 4th layer of pcb board；
Fig. 6 is the cabling schematic diagram of pcb board layer 5.
Specific embodiment
The utility model is further described in the following with reference to the drawings and specific embodiments.
A kind of pcb board of deciphering machine control panel carries double-core ARM cpu chip, DDR3 memory core on deciphering machine control panel
Piece, gigabit ethernet interface, QSPI interface and power module, as shown in Figure 1, DDR3 memory chip is 2 in the present embodiment,
Double-core ARM cpu chip and two panels DDR3 memory chip two-way communication link, U1 indicates to carry double-core ARM cpu chip in figure, M1,
M2 respectively indicates two DDR3 memory chips, and two panels DDR3 chip is connected to power supply Vtt, two panels by reflection compensation resistance Rt
DDR3 chip also needs the reference voltage Vref of 0.75V.Double-core ARM cpu chip passes through QSPI interface and deciphering chip communication link
It connects, for sending task of decryption, receiving and deciphering as a result, in the present embodiment to deciphering chip, is equipped with 8 QSPI interfaces, i.e., one
Double-core ARM cpu chip can control 8 deciphering chips.As shown in Fig. 2, double-core ARM cpu chip passes through gigabit ethernet interface
It is communicated to connect with gigabit ethernet transceiver KSZ9031RNX- PHY, in figure, P2, P3, P4, P5, P6, P7, P8, P9
Indicate gigabit ethernet interface, on the left of line represent the connection between gigabit ethernet interface and gigabit ethernet transceiver
Line, is equipped with 4 pairs of connecting lines between gigabit ethernet interface and gigabit ethernet transceiver, which requires transmission number
According to.The end of address wire, control line between double-core ARM cpu chip and DDR3 chip increases reflection compensation resistance and pull-up electricity
Source, the pull-up power supply are exactly Vtt.
In the present embodiment, the pcb board is N layers, and N is the even number not less than 4, double-core ARM cpu chip, DDR3 memory core
Piece, gigabit ethernet interface, QSPI interface are all set in the top layer of pcb board, and reflection compensation resistance is set to the bottom of pcb board,
Power module is arranged in bus plane, data line, address wire and the control being connected between double-core ARM cpu chip and DDR3 chip
Line is arranged in the middle layer between top layer and bottom, connecting line, the double-core of address wire, control line between two panels DDR3 chip
Connecting line, double-core ARM cpu chip between ARM cpu chip and gigabit Ethernet mouth and the connecting line between QSPI interface
Middle line layer between top layer and bottom is set.
In the present embodiment, pcb board is 8 layers, respectively top layer, the second layer, third layer, bus plane, the 4th layer, stratum, the
Five layers and bottom, top layer and bottom are mainly used for arranging that component, specific arrangement upper section have been described, bus plane segmentation
For muti-piece power supply, for providing power supply, stratum for providing ground connection, the second layer, third layer, the 4th layer, layer 5 be used for cabling.
Specifically, the line group of the least-significant byte of the data line between double-core ARM cpu chip and DDR3 chip, 2 addresses
13 connecting lines of address wire, control line between line, 1 control line and two panels memory are arranged in third layer；Double-core ARM
The line group of the most-significant byte of data line between cpu chip and DDR3 chip and 2 address wires, 3 control lines, control clock difference
13 articles of connecting lines of address wire, control line between line (2 articles) and two panels memory are arranged in the 4th layer；Layer 5 is all double
11 address wires, 5 control lines and 1 RESET line between core ARM cpu chip and DDR3 chip.Such 15 address wires,
9 control lines are distributed over 3 internal layers and suffer plus control clock differential lines (2) and 1 RESET line, CPU and DDR3 core
Inner space is taken full advantage of between piece, ensure that signal integrity top layer and the floor file of bottom free area.
In order to guarantee stabilization of level, bus plane as shown in Figure 3 marks various chips (specifically double-core core ARM CPU core
Piece, DDR3 chip and gigabit ethernet transceiver) needed for core power and peripheral power supply power supply area, Vtt is placed on bottom
Layer, Vref are placed on the region specially marked in stratum, and Vref is the same reference power source, is connected on each pin of Vref
The decoupling capacitor of 0.1uf；And each power pins of double-core ARM cpu chip, DDR3 chip are all connected with a filtered electrical
Hold, which is arranged close to power pins, while in double-core ARM cpu chip and filter capacitor periphery setting energy storage electricity
Hold, decoupling capacitor, filter capacitor, storage capacitor are set to the bottom of pcb board.
In the present embodiment, 4 pairs of connecting lines, 4 pairs of companies are equipped between gigabit ethernet interface and gigabit ethernet transceiver
Wiring requires transmission data, so 4 pairs of connecting lines require to be routed according to the requirement of differential lines, the line width of two lines is 5mil
, spacing 10mil, each pair of line is that the two lines in one group, every group want isometric, and specific line map is as shown in Figure 2.
It in the present embodiment, needs to hollow out below gigabit ethernet interface, i.e., each layer below gigabit ethernet interface is not
It can floor file and power supply.The connecting line of gigabit ethernet interface and double-core ARM cpu chip needs are isometric, one group of signal wire of reception,
The line sent in one group of signal wire, every group is isometric.
In the present embodiment, double-core ARM cpu chip is provided with extension mouth, extends between mouth and double-core ARM cpu chip
Connecting line is distributed in the second layer of pcb board, third layer, the 4th layer and layer 5, the second layer there also is provided JATG mouthfuls of line, be
Isolation is realized in isolation top layer and memory wiring, the rest part floor file of the second layer.
In order to guarantee PCB even running, on pcb board when all snakelike coilings, single line is former by 5W by 3W principle, differential lines
Then coiling, W are line width, and 3W principle is that the distance between line and line keep 3 times of line widths, and 3W principle is that the distance between line and line are protected
5 times of line widths are held, and guarantee that spacing presses at least 3H in each signal line group, spacing 5H between different groups of groups, H are signal wire to main reference
The spacing of plane, address wire, order wire, control line are using VDD as reference planes.
PCB described in the utility model is set as 8 layers, and specific placement bus plane and bottom can be adequately isolated wiring layer,
Reduce the influence to signal integrity.For core power needed for keeping the stabilization of power supply, bus plane to mark various chips and
The power supply area of peripheral power supply, Vtt is placed on bottom and Vref is placed on the region specially marked in stratum, and each of Vref draws
The decoupling capacitor of 0.1uf is connected on foot；Double-core ARM cpu chip, DDR3 chip each power pins be all connected with a filtering
Storage capacitor is arranged in capacitor, double-core ARM cpu chip and filter capacitor periphery, and the stabilization of power supply is to guarantee PCB even running
Key point.The utility model is related to keeping signal integrity by wiring, is designed by power supply and guarantees power supply even running, from
And make the control panel even running for carrying double-core ARM cpu chip.
Described above is only the basic principle and preferred embodiment of the utility model, and those skilled in the art are according to this reality
With the novel improvement and replacement made, belong to the protection scope of the utility model.
Claims (7)
- Carried 1. a kind of pcb board of deciphering machine control panel, on deciphering machine control panel double-core ARM cpu chip, DDR3 memory chip, Gigabit ethernet interface, QSPI interface, double-core ARM cpu chip and DDR3 memory chip two-way communication link, and in DDR3 The control pin and address pin for depositing chip by reflection compensation resistance are connected to power supply Vtt, while DDR3 memory chip and double The memory reference voltage pin of core ARM cpu chip connects same reference power source Vref, and double-core ARM cpu chip is total by QSPI Line interface and deciphering chip communicate to connect, and double-core ARM cpu chip passes through gigabit ethernet interface and gigabit ethernet transceiver Communication connection, it is characterised in that: the pcb board is N layers, and N is the even number not less than 4, double-core ARM cpu chip, DDR3 memory Chip, gigabit ethernet interface, QSPI interface are all set in the top layer of pcb board, and reflection compensation resistance is set to the bottom of pcb board Layer, be connected to the data line between double-core ARM cpu chip and DDR3 memory chip, address wire and control line be arranged in top layer and Intermediate wiring layer between bottom, connecting line, the double-core ARM CPU of address wire, control line between two panels DDR3 memory chip Connecting line, double-core ARM cpu chip between chip and gigabit Ethernet mouth and the connecting line between QSPI interface are also disposed at Intermediate wiring layer between top layer and bottom.
- 2. the pcb board of deciphering machine control panel according to claim 1, it is characterised in that: pcb board is 8 layers, is respectively pushed up Layer, the second layer, third layer, bus plane, the 4th layer, stratum, layer 5 and bottom, double-core ARM cpu chip and DDR3 chip it Between the line group of least-significant byte of data line, 2 address wires, the address wire between 1 control line and two panels memory chip, control 13 connecting lines of line are arranged in third layer；The line group of the most-significant byte of data line between double-core ARM cpu chip and DDR3 chip 13 of address wire, control line between 2 address wires, 3 control lines, 2 control clock differential lines and two panels memory Connecting line is arranged in the 4th layer；11 address wires between all double-core ARM cpu chips of layer 5 and DDR3 chip, 5 Control line and 1 RESET line.
- 3. the pcb board of deciphering machine control panel according to claim 2, it is characterised in that: double-core ARM cpu chip and DDR3 Data line, address wire, control line between chip and address wire, the control line between two panels memory etc. are according to strong points such as groupings Reason, wherein one group of the least-significant byte of the data line of each memory chip, another group of the most-significant byte of data line, one group of address wire, control line, Line in every group is isometric.
- 4. the pcb board of deciphering machine control panel according to claim 1, it is characterised in that: kernel needed for bus plane chip The power supply area of power supply and peripheral power supply, Vtt are placed on bottom, and Vref is placed on the region specially marked in stratum, Vref's The decoupling capacitor of 0.1uf is connected on each pin；Double-core ARM cpu chip, DDR3 chip each power pins be all connected with one Storage capacitor, decoupling capacitor, filtered electrical is arranged in a filter capacitor, double-core ARM cpu chip, DDR3 chip and filter capacitor periphery Appearance, storage capacitor are set to the bottom of pcb board.
- 5. the pcb board of deciphering machine control panel according to claim 1, it is characterised in that: gigabit ethernet interface and gigabit 4 pairs of connecting lines are equipped between ethernet transceiver, which requires transmission data, and 4 pairs of connecting lines are required according to difference Distributing line requires to be routed, and each pair of line is that the two lines in one group, every group are isometric.
- 6. the pcb board of deciphering machine control panel according to claim 1 or 5, it is characterised in that: below gigabit ethernet interface Each layer not floor file and power supply.
- 7. the pcb board of deciphering machine control panel according to claim 1, it is characterised in that: double-core ARM cpu chip is provided with Extend mouth, extend the connecting line between mouth and double-core ARM cpu chip be distributed in the second layer of pcb board, third layer, the 4th layer and Layer 5, the second layer there also is provided JATG mouthfuls of line, the rest part floor file of the second layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820847808.7U CN208480056U (en) | 2018-06-01 | 2018-06-01 | A kind of pcb board of deciphering machine control panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820847808.7U CN208480056U (en) | 2018-06-01 | 2018-06-01 | A kind of pcb board of deciphering machine control panel |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111581134A (en) * | 2020-06-22 | 2020-08-25 | 中国第一汽车股份有限公司 | DDR4 internal memory for laser radar |
| CN111586969A (en) * | 2020-04-28 | 2020-08-25 | 中国科学院计算技术研究所 | Circuit wiring method, DDR4 internal memory circuit and electronic equipment |
| CN112399701A (en) * | 2020-09-27 | 2021-02-23 | 苏州浪潮智能科技有限公司 | Signal wire for improving return loss characteristic caused by equal length of differential wire signal |
-
2018
- 2018-06-01 CN CN201820847808.7U patent/CN208480056U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111586969A (en) * | 2020-04-28 | 2020-08-25 | 中国科学院计算技术研究所 | Circuit wiring method, DDR4 internal memory circuit and electronic equipment |
| CN111581134A (en) * | 2020-06-22 | 2020-08-25 | 中国第一汽车股份有限公司 | DDR4 internal memory for laser radar |
| CN112399701A (en) * | 2020-09-27 | 2021-02-23 | 苏州浪潮智能科技有限公司 | Signal wire for improving return loss characteristic caused by equal length of differential wire signal |
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