CN111581134A

CN111581134A - DDR4 internal memory for laser radar

Info

Publication number: CN111581134A
Application number: CN202010577067.7A
Authority: CN
Inventors: 王祎帆; 王杨; 隋建鹏; 赵晓雪; 王宗罡
Original assignee: FAW Group Corp
Current assignee: FAW Group Corp
Priority date: 2020-06-22
Filing date: 2020-06-22
Publication date: 2020-08-25

Abstract

The invention discloses a DDR4 memory for a laser radar, which comprises a control chip and a plurality of memory units, wherein the control chip is electrically connected with the memory units, one memory unit is connected with a first termination resistor through a first strip line in an address signal path, the resistance values of the first strip line and the first termination resistor are the same, one memory unit is connected with the control chip through a group of second strip lines in a differential clock signal path, one memory unit is connected with a two-termination resistor and a third termination resistor through a group of third strip lines, and every two memory units are connected through a group of fourth strip lines, wherein the resistance values of the second strip line and the third strip line are the same, and the resistance values of the second termination resistor and the third termination resistor are the same.

Description

DDR4 internal memory for laser radar

Technical Field

The embodiment of the invention relates to a storage technology, in particular to a DDR4 internal memory for a laser radar.

Background

With the progress of the intelligent internet technology, the automatic driving automobile gradually becomes popular in the market. Lidar is an important sensor in high-grade autonomous vehicles. The laser radar transmits a laser beam to a target object, then determines the distance of the target object according to the time difference between receiving and reflecting, and deduces the position information of the object according to the distance and the transmitting angle of the laser beam. In the actual use process, the set of coordinates of all the reflection points collected by the laser radar is called point cloud. Typically, a 16-line lidar has 30 ten thousand points per second to process; the number of points to be processed by the 32-line laser radar per second is 70 ten thousand; the 64 line lidar has 220 ten thousand points per second to process.

When the point cloud data needs to be processed, the point cloud data needs to be introduced into the laser radar controller through a FAKRA connector, and the point cloud data needing to be processed is read out from the DDR4 by the FPGA and then processed. At least 4 floating point operations and 3 trigonometric function operations are involved from the original distance information to the coordinate information of the actual object. Due to the huge amount of point cloud data, if the calculation power of a main chip is insufficient or the conditions such as DDR4 data transmission rate and the like cannot meet the requirements, the laser radar processing frame rate cannot meet the design index.

Disclosure of Invention

The invention provides a DDR4 memory for a laser radar, so that DDR4 meets the data read-write speed requirement of laser point cloud data processing; the signal transmission characteristic of a DDR4 PCB is improved.

The embodiment of the invention provides a DDR4 memory for laser radar, which comprises a control chip and a plurality of memory units, wherein the control chip is electrically connected with the memory units,

in an address signal path, a memory cell is connected with a first termination resistor through a group of first strip lines, the resistance values of the first strip lines and the first termination resistor are the same,

in the differential clock signal path, one memory cell is connected with the control chip through a group of second strip lines, one memory cell is connected with two termination resistors and a third termination resistor through a group of third strip lines, every two memory cells are connected through a group of fourth strip lines,

the second strip line and the third strip line have the same resistance, and the second terminating resistor and the third terminating resistor have the same resistance.

Further, the control chip and the memory unit are arranged on the top layer of the PCB, the first termination resistor, the second termination resistor and the third termination resistor are arranged on the bottom layer of the PCB,

the first strip line, the second strip line, the third strip line and the fourth strip line are arranged on a signal layer of the PCB, the first strip line, the second strip line and the third strip line are connected into the top layer and the bottom layer through via holes, and the fourth strip line is connected into the top layer through via holes.

Further, the PCB adopts a 16-layer structure, and sequentially comprises from top to bottom:

a top layer, a first ground layer, a first signal layer, a second ground layer, a second signal layer, a third ground layer, a third signal layer, a power supply layer, a fourth ground layer, a fourth signal layer, a fifth ground layer, a fifth signal layer, a sixth ground layer, a sixth signal layer, a seventh ground layer and a bottom layer,

wherein the second strip line, the third strip line and the fourth strip line are arranged in the same layer of the signal layer.

Furthermore, each stratum and each power supply layer are manufactured through a negative film process.

Further, in the 16-layer structure, prepregs and core boards are alternately arranged between every two adjacent layers.

Further, the distance between every two first strip lines arranged in the same signal layer is 3 times of the thickness of the medium layer,

the dielectric layer is a prepreg or a core board which is configured with the stratum corresponding to the signal layer.

Further, the first strip line is disposed on the second signal layer.

Further, the second strip line, the third strip line, and the fourth strip line are disposed in the first signal layer.

Furthermore, in the data signal path, the memory unit is connected with the data port of the control chip through a group of fifth strip lines, connected with the data chip selection port of the control chip through a group of sixth strip lines, and connected with the data mask port of the control chip through a group of seventh strip lines,

the fifth strip line, the sixth strip line, and the seventh strip line are disposed in the first signal layer, and the second strip line, the third strip line, and the fourth strip line have a pitch at least 3 times as large as a thickness of the dielectric layer,

the dielectric layer is a prepreg or a core board which is configured with a stratum corresponding to the first signal layer.

Further, the fifth strip line and the seventh strip line have the same resistance value.

Compared with the prior art, the invention has the beneficial effects that: in this embodiment, the address signal path, the clock signal path, and the data signal path in the DDR4 PCB are redesigned, and a routing topology of a strip line in the signal path and an impedance matching manner between the strip line and a terminating resistor are provided, so that the DDR4 can meet the data read-write speed requirement of laser point cloud data processing, and meanwhile, the signal transmission characteristic of the DDR4 PCB can be improved.

Drawings

FIG. 1 is a block diagram of the overall structure of an embodiment of a memory;

FIG. 2 is a diagram showing an example of an address signal path structure;

FIG. 3 is a schematic diagram of a differential clock signal path structure in an embodiment;

FIG. 4 is a diagram showing a structure of a data signal path in the embodiment;

FIG. 5 is a schematic diagram of a PCB hierarchy in an embodiment;

FIG. 6 is a test result chart A in the example;

FIG. 7 is a test result chart B in the example;

fig. 8 is a test result chart C in the example.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

DDR4 is the current mainstream memory standard, and in DDR4, the types of Signals involved in the interaction between the Control unit and the memory unit include Clock Signals (Clock Signals), Address Signals (Address Signals), command Signals (command Signals), Control Signals (Control Signals), Data Signals (Data Signals), and other Signals (other Signals).

In the embodiment, the address signal path, the clock signal path and the data signal path in the DDR4 PCB are mainly redesigned to improve the signal transmission quality, and simultaneously, the DDR4 meets the requirement of the data read-write speed in the laser radar point cloud data processing application scene.

Fig. 1 is a block diagram of an overall structure of an embodiment of a memory, fig. 2 is a schematic diagram of an address signal path structure in the embodiment, fig. 3 is a schematic diagram of a differential clock signal path structure in the embodiment, fig. 4 is a schematic diagram of a data signal path structure in the embodiment, referring to fig. 1 to 4, a DDR4 memory includes a control chip 100 and a plurality of memory units 200, and the control chip 100 is electrically connected to the memory units 200.

In this embodiment, the control chip 100 is an FPGA, and the memory unit 200 is an SDRAM.

Referring to fig. 2, in the address signal path, one memory cell 200 (memory cell 3) is connected to the first terminating resistor R1 through a set of first strip lines L4, and the first strip lines L4 have the same resistance as the first terminating resistor R1.

Referring to fig. 3, in the differential clock signal path, one memory cell 200 (memory cell 0) is connected to the controller chip 100 through a set of second strip lines L5, one memory cell 200 (memory cell 3) is connected to the second termination resistor R2 and the third termination resistor R3 through a set of third strip lines L9, and every two memory cells are connected to each other through a set of fourth strip lines (L6, L7, L8).

Referring to fig. 4, in the data signal path, the memory unit 200 is connected to a data port DQ (DQ0 … DQ3) of the controller chip 100 through a set of fifth strip lines L12, to a data chip select port DQs (DQs0 … DQs3) of the controller chip 100 through a set of sixth strip lines L11, and to a data mask port DM (DM0 … DM3) of the controller chip 100 through a set of seventh strip lines L10.

The second strip line L5 and the third strip line L9 have the same resistance, and the second terminating resistor R2 and the third terminating resistor R3 have the same resistance. The fifth strip line L12 has the same resistance as the seventh strip line L10.

Fig. 5 is a schematic diagram of a hierarchical structure of a PCB in an embodiment, and referring to fig. 5, in this embodiment, the PCB adopts a 16-layer structure, which sequentially includes, from top to bottom:

the multilayer optical waveguide comprises a top Layer1, a first stratum Layer2, a first signal Layer3, a second stratum Layer4, a second signal Layer5, a third stratum Layer6, a third signal Layer7, a power Layer8, a fourth stratum Layer9, a fourth signal Layer10, a fifth stratum Layer11, a fifth signal Layer12, a sixth stratum Layer13, a sixth signal Layer14, a seventh stratum Layer15 and a bottom Layer 16. In the 16-layer structure, prepregs 1 and cores 2 are alternately arranged between each two adjacent layers.

In this embodiment, as an implementation example, the first formation Layer2, the second formation Layer4, the third formation Layer6, the power supply Layer8, the fourth formation Layer9, the fifth formation Layer11, the sixth formation Layer13, and the seventh formation Layer15 are made by a negative film process.

For example, in the present embodiment, the control chip 100 and the memory cell 200 are disposed on the top Layer1, and the first termination resistor R1, the second termination resistor R2 and the third termination resistor R3 are disposed on the bottom Layer 16. The first strip line L4, the second strip line L5, the third strip line L9 and the fourth strip line (L6, L7, L8) are arranged in a signal Layer of the PCB, the first strip line L4, the second strip line L5, the third strip line L9 are connected to the top Layer1 and the bottom Layer16 through via holes, and the fourth strip line (L6, L7, L8) is connected to the top Layer1 through via holes.

In this embodiment, the effective address port of the control chip 100 is A [15:0], and accordingly, the PCB has 16 strip lines L0, L1, L2, L3 and a first strip line L4.

For the address signal path, in this embodiment, different strip lines L0, L1, L2, L3, or first strip line L4 may be disposed in different signal layers, but the routing topologies are similar, taking the strip lines L0, L1, L2, L3 disposed in the second signal Layer5 and the first strip line L4 as an example, the routing topologies are: stub stubs stub1, stub2-1, stub2-2, stub3-1, stub3-2, stub4-1, stub4-2, stub5-1 and stub5-2 are respectively led out of an address port of the control chip 100, an address port of the memory unit 0, an address port of the memory unit 1, an address port of the memory unit 2 and an address port of the memory unit 3 at the top Layer 1. Strip line L0 is connected to stub1 and stub2-1 at top Layer1, strip line L1 is connected to stub2-2 and stub3-1 at top Layer1, strip line L2 is connected to stub3-2 and stub4-1 at top Layer1, strip line L3 is connected to stub4-2 and stub5-1 at top Layer1, and first strip line L4 is connected to stub5-2 at top Layer1 and first termination resistor R1 at bottom Layer 16.

Preferably, the track width of the strip line L0 is 7.4mil, the track widths of the strip lines L1, L2 and L3 are 4.0mil, and the track width of the first strip line is 6.2 mil. The resistance of the strip line L0 is 36 ohms, the resistances of the strip lines L1, L2, L3 are 50 ohms, the resistance of the first strip line L4 is 39 ohms, and the resistance of the first terminating resistance R1 is 39 ohms.

Preferably, the distance between every two strip lines arranged in the same signal layer is 3 times the thickness of the dielectric layer. The medium layer is a prepreg 1 or a core plate 2 which is configured with a stratum corresponding to the signal layer. Illustratively, if a plurality of first strip lines L4 are arranged in the second signal Layer5, and the reference Layer corresponding to the second signal Layer5 is the fourth ground Layer9, the dielectric Layer is a core board between the power Layer8 and the fourth ground Layer9, and the distance between every two first strip lines L4 is at least three times the thickness of the core board.

Referring to fig. 3 and 5, for the differential clock signal path, in the present embodiment, the second terminating resistor R2 and the third terminating resistor R3 are disposed on the bottom Layer16, for example. The second strip line L5, the third strip line L9, and the fourth strip line (L6, L7, and L8) are disposed in the first signal Layer 3. In this embodiment, the clock port in the control chip 100 includes CK _ P and CK _ N, and accordingly, the PCB commonly has 2 strip lines L5, L6, L7, L8, and L9, and the routing topologies of the signal paths where CK _ P and CK _ N are located are the same, taking the signal path where the clock port includes CK _ P as an example, the routing topology is: at the top Layer1, short stubs stub6, stub7-1, stub7-2, stub8-1, stub8-2, stub9-1, stub9-2, stub10-1 and stub10-2 are respectively led out from the CK _ P port of the control chip 100, the CK _ P port of the memory unit 0, the CK _ P port of the memory unit 1, the CK _ P port of the memory unit 2 and the CK _ P port of the memory unit 3. Second strip line L5 is connected to stub6 and stub7-1 at top Layer1, respectively, strip line L6 is connected to stub7-2 and stub8-1 at top Layer1, respectively, strip line L7 is connected to stub8-2 and stub9-1 at top Layer1, respectively, strip line L8 is connected to stub9-2 and stub10-1 at top Layer1, respectively, and third strip line L9 is connected to stub10-2 at top Layer1, respectively, and second termination resistor R2 at bottom Layer16, respectively, by vias.

In a preferred embodiment, in the differential clock signal path, the width of the stub at the top Layer1 is 6.8mil, the width of the second strip line L5 is 6.0mil, the pitch between two second strip lines L5 is 4.5mil, the width of the fourth strip line (L6, L7, L8) is 4.5mil, the pitch between two fourth strip lines is 7.9mil, the width of the third strip line L9 is 6.0mil, and the pitch between two third strip lines L9 is 6.4 mil. When other strip lines are also arranged in the first signal Layer3, the spacing between the second strip line L5, the third strip line L9 and the fourth strip line (L6, L7, L8) and the other strip lines needs to be at least 3 times of the thickness of the dielectric Layer.

Preferably, the differential impedance of the second strip line L5 is 76 ohms, the differential impedance of the fourth strip line L6 is 90 ohms, the differential impedance of the fourth strip line (L6, L7, L8) is 90 ohms, the differential impedance of the third strip line is 76 ohms, the resistance of the second termination resistor R2 is 36 ohms, the resistance of the third termination resistor R3 is 36 ohms, the capacitance of the capacitor C1 is 10nF, and the VTT voltage is 0.6V.

Illustratively, in this embodiment, the termination modes of the second termination resistor R2, the third termination resistor R3 and the capacitor C1 are RC termination, when a differential clock signal just reaches the RC termination, the capacitor C1 charges with a time constant RC, a current flows through the second termination resistors R2 and R3, at this time, R2 and R3 play a role of parallel termination, and as time goes on, the voltage at two ends of the capacitor C1 is gradually stabilized, and at this time, no current flows through R2 and R3, so that the problem of excessive active parallel termination dc power consumption can be effectively reduced.

Referring to fig. 4 and 5, the control chip 100 includes four sets of data ports DQ (DQ0 … DQ3), four sets of data chip select ports DQs (DQs0 … DQs3), and four sets of data mask ports DM (DM0 … DM3) for data signal paths, and the control chip 100 is connected to one memory unit through one set of data ports, one set of data chip select ports, and one set of data mask ports. Illustratively, the effective address ports of a group of data ports DQ, e.g., DQ0, are DQ0[0:7], and correspondingly, a group of data ports DQ corresponds to 8 fifth striplines L12, a group of data chip select ports DQs includes one DQs _ N port and one DQs _ P port, and correspondingly, a group of data chip select ports DQs corresponds to 2 sixth striplines L11.

As an embodiment, the fifth strip line L12, the sixth strip line L11, and the seventh strip line L10 are disposed in the first signal Layer 3. In this embodiment, the data port DQ is the same as the data chip select port DQs and the data mask port DM in routing topology, taking a path where a fifth strip line L12 connected to a DQ0 port is located as an example, at the top Layer1, a stub11 and a stub12 are respectively led out from a DQ0 port of the control chip 100 and a DQ0 port of the memory unit 0, and the fifth strip line L12 is respectively connected to a stub11 and a stub12 at the top Layer1 through via holes.

Preferably, the resistance of the fifth strip line L12 is the same as that of the seventh strip line L10, specifically, the characteristic impedance of the fifth strip line L12 is 39 ohms, the characteristic impedance of the sixth strip line L11 is 76 ohms, and the characteristic impedance of the seventh strip line L10 is 39 ohms.

Illustratively, the data signal path is terminated by an on-chip odt (on Die termination), i.e., an on-board termination resistor is integrated inside the control chip 100.

In a write operation, different termination impedance values can be configured by controlling 8-10 bits of the register. Illustratively, when the configuration register MR1 is 000, the termination resistor is disabled, and when MR1 is 001, the termination resistor impedance is 60 ohms. When MR1 is 010, the termination resistance impedance is 120 ohms. When MR1 is 011, the termination resistance impedance is 40 ohms. At MR1 ═ 100, the termination resistance impedance was 240 ohms. When MR1 is 101, the termination resistance impedance is 48 ohms. At MR1 ═ 110, the termination resistance impedance was 80 ohms. When MR1 is 111, the termination resistance impedance is 34 ohms.

In a read operation, different output impedance values can be configured by controlling bits 1-2 of the register. When MR1 is 00, the output impedance is 34 ohms. When MR1 is 01, the output impedance is 48 ohms. When MR1 is 10, the output impedance is 40 ohms. When MR1 is 11, the output impedance is not set for the reserved option.

In this embodiment, an address signal path, a clock signal path, and a data signal path in the DDR4 PCB are redesigned, and a routing topology structure of a strip line in the signal path and an impedance matching manner between the strip line and a terminating resistor are provided, so that the data transmission rate of the DDR4 can reach 2666Mbps, the data read-write rate meets the requirement of laser point cloud data processing, and meanwhile, the signal transmission characteristic (signal integrity) of the DDR4 PCB can be improved by using the above-mentioned routing manner.

Fig. 6 is a test result diagram a in the embodiment, and referring to fig. 6, fig. 6 shows simulation test results of the data signal path and the differential clock signal path. As can be seen from fig. 6, the signal quality of the differential clock lines and address lines is better.

For the differential clock signal path, during testing, the signal frequency of the differential clock signals CK _ P and CK _ N is set to be 1333MHz, the test model of the control chip end is HP _ SSTL12_ DCI _ M _ OUT40, and the test model of the memory cell end is CLKIN _ 2666. For a single-ended clock signal, a high level threshold value is larger than 0.695V, a low level threshold value is smaller than 0.505V, an overshoot is not more than 1.5V, an undershoot is not smaller than-0.3V, and a cross point of CK _ P and CK _ N signals is between 0.49V and 0.71V. For differential signals of CK _ P and CK _ N, a high level threshold value is configured to be larger than 0.135V, and a low level threshold value is configured to be smaller than-0.135V.

For a data signal path, the transmission rate of an address signal is configured to be 1333Mbps, a test model of a control chip end is selected to be HP _ SSTL12_ DCI _ M _ OUT40, and a test model of a memory unit end is INPUT _ 2666. Aiming at the address signals, a high level threshold value is configured to be larger than 0.69V, a low level threshold value is configured to be smaller than 0.51V, the signal conversion rate is between 1V/ns and 7V/ns, the establishment time is larger than 96ps, and the retention time is smaller than 109 ns.

Fig. 7 is a test result graph B in the embodiment, fig. 8 is a test result graph C in the embodiment, fig. 7 shows a simulation test result of the data signal path at the time of write operation, and fig. 8 shows a simulation test result of the data signal path at the time of read operation.

IN a write operation, the signal transmission rate of the data port DQ is 2666Mbps, the test model of the control chip end is selected as HP _ POD12_ DCI _ F _ OUT40, and the test model of the memory unit end is selected as DQ _ IN _ ODT40_ 2666. IN a read operation, the signal transmission rate of the configuration data port DQ is 2666Mbps, the test pattern of the control chip side is selected as HP _ POD12_ DCI _ F _ OUT40_ IN40, and the test pattern of the memory cell side is selected as DQ _40_ 2666. The peak-to-peak value of the configuration data port DQ is larger than 150mV, the pulse width is larger than 0.58UI, the peak-to-peak value of the data signal eye mask is larger than 120mV, and the time width is larger than 0.22 UI. The signal setup time of the data port DQ is greater than one-half eye mask time width. The signal hold time of the data port DQ is greater than one-half eye mask time width.

IN a write operation, the signal frequencies of the data chip selection ports DQS _ P and DQS _ N are set to 1333MHz, the test model of the control chip side is selected to be HP _ POD12_ DCI _ F _ OUT40, and the model of the memory cell side is selected to be DQS _ IN _ ODT40_ 2666. IN a read operation, the signal frequencies of the data chip select ports DQS _ P and DQS _ N are set to 1333MHz, the model of the control chip side is HP _ POD12_ DCI _ F _ OUT40_ IN40, and the model of the memory cell side is DQS _40_ 2666. And configuring a high level threshold value to be more than 150mV and configuring a low level threshold value to be less than-150 mV for differential signals of the data chip selection ports DQS _ P and DQS _ N. In the write operation, the signaling rate of the data mask port DM is configured to 2666Mbps, the test model of the control chip side is selected to be HP _ POD12_ DCI _ F _ OUT40, and the model of the control chip side is selected to be DM _ ODT40_ 2666. IN a read operation, the signaling rate of the data mask port DM is 2666Mbps, the test model of the control chip is HP _ POD12_ DCI _ F _ OUT40_ IN40, and the model of the memory unit is DM _40_ 2666. The peak-to-peak value of the configuration DM signal is more than 150mV, the pulse width is more than 0.58UI, the peak-to-peak value of the data signal eye mask is more than 120mV, and the time width is more than 0.22 UI. The DM signal has a settling time greater than one-half eye mask time width. The retention time of the DM signal is greater than one-half eye mask time width.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. The DDR4 memory for the laser radar is characterized by comprising a control chip and a plurality of memory units, wherein the control chip is electrically connected with the memory units,

2. The DDR4 memory for lidar of claim 1, wherein the control chip, the memory unit are disposed on a top layer of a PCB, the first termination resistor, the second termination resistor, and the third termination resistor are disposed on a bottom layer of the PCB,

3. The DDR4 memory for lidar of claim 1, wherein the PCB is a 16-layer structure having, in order from top to bottom:

4. The DDR4 memory for lidar of claim 3, wherein each ground layer and power layer is fabricated by a negative film process.

5. The DDR4 memory for lidar of claim 3, wherein in the 16-layer structure, prepregs and core boards are arranged alternately between each two adjacent layers.

6. The DDR4 memory for lidar of claim 5, wherein each two of the first striplines disposed in a same signal layer are spaced 3 times a thickness of a dielectric layer,

7. The DDR4 memory for lidar of claim 3, wherein the first stripline is disposed at the second signal layer.

8. The DDR4 memory for lidar of claim 7, wherein the second stripline, third stripline, and fourth stripline are disposed at the first signal layer.

9. The DDR4 memory for lidar of claim 8, wherein in the data signal path, memory cells are coupled to the data port of the control chip via a set of fifth striplines, to the data chip select port of the control chip via a set of sixth striplines, and to the data mask port of the control chip via a set of seventh striplines,

10. The DDR4 memory for lidar of claim 9, wherein the fifth strip line and the seventh strip line have the same resistance.