CN107544319A - A kind of circuit structure of electromechanical integration equipment - Google Patents

Abstract

The invention discloses a kind of circuit structure of electromechanical integration equipment, including the first CPLD, the 2nd CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data wire；First CPLD is electrically connected with the first Low Voltage Differential Signal LVDS interface；2nd CPLD is electrically connected with the second Low Voltage Differential Signal LVDS interface；The first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface pass through clock line and data line electrical connection.The present invention utilizes LVDS technologies, realize 8 a small amount of lines, pass through the data packing and unpacking of CPLD integrated technologies, to transmit two separated by a distance local a large amount of signals, to reduce the routing complexity in electromechanical integration and miscellaneous equipment, while reliability to system, reduce troubleshooting time there is obvious effect.

Description

A kind of circuit structure of electromechanical integration equipment

Technical field

The present invention relates to circuit structure, and in particular to a kind of circuit structure of electromechanical integration equipment.

Background technology

With the raising of labor cost, it is desirable to automatically processing device become increasingly complex, while with embedded meter A large amount of popularizations of calculation machine control, distributed AC servo system become inexorable trend.Therefore in the dcs of complexity, wiring Complexity and reliability just become very prominent, traditional method, each generally outside signal needs a wire, from one Local (such as Main Control Tank) moves another place (such as scene) to, if a system has hundreds of signals, even thousands of, this agrees Surely great difficulty is carried out to remote wiring tape.Such as in embroidery machine, pattern sewing machine and vamp machine system, the signal at scene is arranged in Have：Head signal, framework four-way are offside, trimming, fastening wire, hooking, main shaft signal, main spindle's, frame position, clamp, etc., If all connected from main control CPU, it connects up to mix and well imagined, tradition generally requires master control to be positioned over scene, and this gives again The operability (figure shows, the operation of various data cards, network linking operation etc.) of master control makes troubles.

The content of the invention

The purpose of the present invention utilizes LVDS technologies, realizes a small amount of several threads, the packing and unpacking by data is being separated by Two substantial amounts of signals of localized transmissions of certain distance, to reduce the routing complexity in electromechanical integration and miscellaneous equipment.

The present invention is in view of the above-mentioned problems, provide a kind of circuit structure of electromechanical integration equipment.

According to an aspect of the invention, there is provided a kind of circuit structure of electromechanical integration equipment, including the first CPLD, 2nd CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data wire；It is described First CPLD is electrically connected with the first Low Voltage Differential Signal LVDS interface；2nd CPLD is electrically connected with the second Low Voltage Differential Signal LVDS interface；The first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface pass through clock line and number It is electrically connected with according to line.

Advantages of the present invention：

The present invention utilizes LVDS technologies, by the data packing and unpacking of CPLD integrated technologies, to transmit separated by a distance two Individual local a large amount of signals (such as 200), to reduce the routing complexity in electromechanical integration and miscellaneous equipment, while to system Reliability, reduce troubleshooting time there is obvious effect.

In addition to objects, features and advantages described above, the present invention also has other objects, features and advantages. Below with reference to figure, the present invention is further detailed explanation.

Brief description of the drawings

The accompanying drawing for forming the part of the application is used for providing a further understanding of the present invention, illustrative examples of the invention And its illustrate to be used to explain the present invention, do not form inappropriate limitation of the present invention.

Fig. 1 is a kind of electrical block diagram of electromechanical integration equipment of the present invention；

Fig. 2 is a kind of method of work structure flow chart of the circuit of electromechanical integration equipment of the present invention.

Embodiment

In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with drawings and Examples, to this hair It is bright to be further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and do not have to It is of the invention in limiting.

With reference to figure 1, a kind of circuit structure of electromechanical integration equipment as shown in Figure 1, including the first CPLD, second CPLD, the first Low Voltage Differential Signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data wire；Described first CPLD is electrically connected with the first Low Voltage Differential Signal LVDS interface；2nd CPLD is electrically connected with the second Low Voltage Differential Signal LVDS Interface；The first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface pass through clock line and data wire It is electrically connected with.

With reference to figure 2, the method for work of foregoing circuit structure as shown in Figure 2, comprise the following steps：

S1, when all multi signals will be sent to the second ground from the first ground, while there are all multi signals to be sent to the first ground from the second ground, The first CPLD at first packs to signal group, forms the serial data of a string of length；Add simultaneously at each serial data rear portion Upper check code, serial data is sent in a manner of one data bit of a clock pulses by using the high-frequency clock inside CPLD Go out；

S2, for the reliability of long-distance transmissions, by the first Low Voltage Differential Signal LVDS interface by signal synchronism output；

S3, second be located in first to the first ground transmission LVDS Low Voltage Differential Signals carry out level translation, using bring when Clock and data are located in second serially moves into the 2nd CPLD on the second ground；

S4, the second the 2nd CPLD being located in are after all signals are received, code of testing review；

S5, in the case of check code is incorrect, the reception value that local data group retains last time is constant；In the correct feelings of check code Under condition, the new data set of reception is located in second and showed；

S6 is identical with above-mentioned pattern when to be sent to the first ground from the second ground to signal group.

The general principle of the present invention is described below：It is preferable to have 100 (referring between 10-1000) signals from first point The second point (live board) that (master control) is sent away, while there are 100 collection information points to be sent to first from the second point of distant place Point, if at least wanting 200 lines using conventional method, it is clear that excessively complicated；If using this method, monolithic can be passed through CPLD (Complex programmable logical device) chips form 100 data the packet of one tape verifying sum, pass through LVDS (low-voltage differentials Signal), passed with the serial ports of high speed, also have the CPLD of a monolithic in other end, the tape verifying sum received Packet carries out CPLD unpackings, and point 100 independent signals show, 100 signal transmission being achieved that between two places； The also of this sort transmission of 100 signals of opposite direction, so just realize the mutual biography of 200 signals.

In LVDS serial ports transmittance process, in order to ensure the promptness of signal transmission, sufficiently high speed should be used, such as Each signal wire delay is no more than a ten thousandth second, then the standard baud rate of LVDS serial ports should be not less than 2MHz, can generally use The Internet Engineering Task speed of tens to hundreds of general MHz, it is easy to wire rod buying and implements.

LVDS represents differential signal, it is necessary to which both threads, consider two-way clock and data-signal, therefore the program needs altogether Want 8 lines.It can be shared with internet line.

The present invention utilizes LVDS technologies, realizes 8 a small amount of lines, by the data packing and unpacking of CPLD integrated technologies, To transmit two separated by a distance local a large amount of signals (such as 200), to reduce in electromechanical integration and miscellaneous equipment Routing complexity, while reliability to system, reduce troubleshooting time there is obvious effect.

The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.

Claims (1)

1. a kind of circuit structure of electromechanical integration equipment, it is characterised in that including the first CPLD, the 2nd CPLD, the first low pressure Differential signal LVDS interface, the second Low Voltage Differential Signal LVDS interface, clock and data wire；First CPLD is electrically connected with the One Low Voltage Differential Signal LVDS interface；2nd CPLD is electrically connected with the second Low Voltage Differential Signal LVDS interface；Described first Low Voltage Differential Signal LVDS interface and the second Low Voltage Differential Signal LVDS interface pass through clock line and data line electrical connection.