CN106299110B - The non-volatile memory device and manufacturing method of write operation voltage can be reduced - Google Patents
The non-volatile memory device and manufacturing method of write operation voltage can be reduced Download PDFInfo
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Abstract
The invention belongs to non-volatile memory technologies fields, provide a kind of non-volatile memory device and manufacturing method that can reduce write operation voltage.Non-volatile memory device of the invention, comprising: inverted cone shape first electrode；Storage medium layer, it includes first part and second part, wherein the first part is attached on the lateral surface of inverted cone shape first electrode, and non-parallel be arranged so that of the second part and the lateral surface of the inverted cone shape first electrode connect with the first part and form angle；And second electrode, it is formed in the inside of the angle formed between the first part and second part of the storage medium layer.Non-volatile memory device of the invention is reduced and uniformly, prepares simple, at low cost by forming the angle structure of storage medium layer, write operation voltage between the first electrode and the second electrode.
Description
Technical field
The invention belongs to non-volatile memory technologies fields, and writing for non-volatile memory device can be reduced by being related to one kind
Operate the memory element and its manufacturing method of voltage.
Background technique
Low-power consumption and high-density applications target for non-volatile memory semiconductor device, there are many exhibitions of research
Open, including from material, a series of exploration has been carried out on device architecture, in manufacturing method and in periphery circuit design.
Flash memory is the data of storage even if the representative for the non-volatile memory that can also be retained after power is turned off.Flash memory has
It is non-volatile, it is different from volatile memory.But flash memory has the shortcomings that low integrated level and needs big voltage operation.
Many researchs are carried out to nonvolatile storage now, these nonvolatile storages include magnetic random memory
(MRAM), ferroelectric RAM (FRAM), phase change random access memory devices (PRAM) and resistive ram
(RRAM)。
If operating voltage value required for storage unit to reduce, the size of the transistor of peripheral circuit can contract
It is small, it is possible thereby to improve the integrated number of storage unit on unit area.
With further miniatureization of memory device size, the fluctuation of device parameters and electrical parameter between storage unit
Aggravation, the reliability that this problem will lead to storage array reduce.Battle array can be improved to a certain extent by reducing write operation voltage
The reliability of column.Particularly, for resistive ram, apply initial breakdown voltage and be formed by conductive filament
It is randomly generated in storage medium layer, with the diminution of device size, what conductive filament generated is located proximate to device edge
Etching injury region a possibility that will increase, etching injury region formed conductive filament size can be larger, the electric current flowed through
Also can be larger, this will be unfavorable for the requirement of low-power consumption.Therefore, if conductive filament can be generated fixedly in device cell
Heart position, this will inhibit the size and its deviation of the initial breakdown voltage between each device cell, storage also can be improved
The reliability of array.
U.S. Patent No. US 2013,0112936A1, the entitled " Resistance of Zhiqiang Wei et al.
A kind of device architecture is proposed in the patent of change element and manufacturing method therefor " to set
Meter, as shown in figure 14.Electric field can be made to assemble in fixed position, so that initial breakdown occurs in fixed needle-like portion electrode
Position can control the filament region that resistance variations phenomenon occurs for the memory element of resistance-varying type
(filament) happening part.Thereby, it is possible to inhibit the initial breakdown voltage of each element, movement when resistance value it is inclined
Difference.As a result, it is possible to the surplus for needing to add the design size of electro-resistance element as deviation countermeasure be cut down, so can
Realize imperceptibility, the high capacity of storage device.
U.S. Patent No. US 2014,0061573A1, the entitled " Nonvolatile of Takumi Mikawa et al.
memory element,Nonvolatile memory device,and methods of manufacturing the
A kind of device structure design is proposed in the patent of same ", as shown in figure 15, conductive filament can be made to be formed in different two
Layer resistive dielectric layer is formed by stepped portions, and this stepped portions is in the center of memory element.And step
The storage medium film thickness of the high value at position reduces, and can reduce the initial breakdown voltage to form conductive filament.And it is conductive thin
The position that silk generates is fixed, and can reduce the deviation of the initial breakdown voltage between memory element.When the size of memory element contracts
Hour, centre is influenced very little by edge, can reduce the deviation of resistance value between different memory elements, and can be improved can
By property, imperceptibility, the high capacity of storage device can be realized.
It can be found that, it has been suggested that non-volatile memory device structure design, substantially by fixed conductive thin
The position that silk occurs reduces the deviation of write operation voltage and write operation voltage, realizes imperceptibility, the high capacity of storage device.
Summary of the invention
The object of the present invention is to provide a kind of non-volatile memory devices with new memory element structure.
To realize that object above or other purposes, the present invention provide following technical scheme.
It is an aspect of this invention to provide that providing a kind of non-volatile memory device comprising:
First electrode and second electrode, and the storage medium layer being placed between first electrode and second electrode.Wherein
One electrode is back taper, cone angle α, 60 °≤α≤80 °.Storage medium layer, including first part and second part, wherein institute
It states first part to be attached on the lateral surface of inverted cone shape first electrode, the second part is outer with the inverted cone shape first electrode
Non-parallel be arranged so that in side connect with the lower end of the first part and forms angle.Second electrode is formed in the storage
The inside of the angle formed between the first part and second part of dielectric layer.
In the embodiment of the foregoing description, the storage medium layer can be variable-resistance material, including as metal aoxidizes
The variable-resistance material of object, such as selected from AlOx, WOx, HfOx, TaOx, TiOx, SiO2, ZnOx, in NiOx, GeSbyTex
A kind of combination of material or different materials.
In foregoing description embodiment, the first electrode material can by be selected from Pt, Ag, Cu, TaN, TiN, Al, W or
One of its alloy material is formed.
In foregoing description embodiment, the second electrode material can by be selected from Pt, Ag, Cu, TaN, TiN, Al, W or
One of its alloy material is formed.
The present invention can not only as such electro-resistance element realize, additionally it is possible to as be used to manufacture such resistance
The manufacturing method for changing element is realized.
It is an aspect of this invention to provide that providing a kind of manufacturing method of non-volatile memory device comprising:
Inverted cone shape first electrode is formed in first medium layer；
To first medium layer progress selective etching so that the exposed shape in biggish upper part of the inverted cone shape first electrode
At pylon structure；
The conformal storage medium layer being covered on the pylon structure and first medium layer is deposited, to make the storage medium
Layer includes at least the first part that is attached on the lateral surface of inverted cone shape first electrode and outer with the inverted cone shape first electrode
The second part of the non-parallel setting in side, the first part connect with the second part and form angle；In the storage
The inside of the angle formed between the first part and second part of dielectric layer forms second electrode.
Deposit second electrode material layer；Chemical mechanical grinding is carried out to the second electrode material layer until the pylon knot
The upper surface of structure is exposed.
The manufacturing method of the non-volatile memory device and the rear end structure preparation process of cmos circuit are integrated；
Non-volatile memory device of the invention by forming storage medium layer between the first electrode and the second electrode
Angle structure, write operation voltage are reduced and uniformly, are prepared simple, at low cost and conveniently compatible with standard CMOS process.
Detailed description of the invention
From the following detailed description in conjunction with attached drawing, it will keep above and other purpose and advantage of the invention more complete
It is clear, wherein the same or similar element, which is adopted, to be indicated by the same numeral.
Fig. 1 is the cross-sectional view according to the structure of the non-volatile memory device of one embodiment of the invention.
Fig. 2A is the simulation according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
Simplify structure used by emulation.
Fig. 2 B is the simulation according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
Reduced parameter used by emulating.
Fig. 3 is the simulation knot according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
Fruit.
Fig. 4 A is the simulation according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
As a result.
Fig. 4 B is the simulation according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
As a result.
Fig. 5 A is the simulation according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
As a result.
Fig. 5 B is the simulation according to the electric field congregational rate of the structure of the non-volatile memory device of one embodiment of the invention
As a result.
Fig. 6 is the section view according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
Figure.
Fig. 7 is the section view according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
Figure.
Fig. 8 is the section view according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
Figure.
Fig. 9 is the section view according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
Figure.
Figure 10 is cutd open according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
View.
Figure 11 is cutd open according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
View.
Figure 12 is bowed according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
View.
Figure 13 is bowed according to the process of the manufacturing method of the structure of the non-volatile memory device of one embodiment of the invention
View.
Figure 14 is the non-volatile memory device cross-sectional view of the prior art.
Figure 15 is the non-volatile memory device cross-sectional view of the prior art.
Specific embodiment
What is be described below is some in multiple possible embodiments of the invention, it is desirable to provide to of the invention basic
Solution, it is no intended to confirm crucial or conclusive element of the invention or limit scope of the claimed.It is readily appreciated that, according to this
The technical solution of invention, in the case where not changing connotation of the invention, those of ordinary skill in the art can propose can be mutual
Other implementations of replacement.Therefore, following specific embodiments and attached drawing are only the examples to technical solution of the present invention
Property explanation, and be not to be construed as whole of the invention or be considered as to define or limit technical solution of the present invention.
It is detailed there is no being carried out to all multiple components shown in figure for the clear and concise of description in following description
Thin description.The disclosure for being fully able to realize of the invention is provided for those of ordinary skill in the art shown in the drawings of multiple components
Content.To those skilled in the art, perhaps multipart operation is all familiar and apparent.
Fig. 1 shows the sections of the non-volatile memory device 200 made by the experiment.Non-volatile memory device
200 be to be embedded in first electrode 21, storage medium layer 22, second electrode 23 in first medium layer 20 to constitute, later shape on it
At next layer of metal interconnecting wires 26, metal through-hole interconnection 27.Referring to Fig.1, the shape of first electrode 21 is back taper, and cone angle is by work
Skill preparation condition determines, can form the angle between 60 ° to 80 °.First electrode can be Pt, Ag, Cu, TaN, TiN, Al, W
The alloy of one or more of equal metals.Storage medium layer 22 is divided to for two parts, is respectively attached to first electrode 21 and is fallen
The first part 22a of cone cell lateral surface, and with the nonparallel second part 22b of 21 inverted cone shape lateral surface of first electrode.Storage
Dielectric material 22 can be the material of resistance variations type, such as aluminium oxide (AlOx), tungsten oxide (WOx), hafnium oxide (HfOx),
Tantalum oxide (TaOx), titanium oxide (TiOx), silica (SiO2), zinc oxide (ZnOx), one of nickel oxide (NiOx) material
Or the combination of different materials.The material composition of 22a and 22b is technique shallow lake that is identical, using when depositing storage medium material 22
Product mode has the characteristics that conformality covering, and the thickness of the part 22a and 22b is identical.Wherein 22a and 22b constitute angle 24.
The material of first electrode 21 is allowed a choice because of the difference of storage medium.For example, when storage medium 22 is AlOx, first electrode
21 can be using metals such as TaN, TiN, Al, W；And when storage medium 22 is SiO2, first electrode 21 can be using Ag, Cu etc.
Wave metal living.The material of storage medium 22 is also possible to germanium antimony tellurium alloy (GeSbyTex) phase-change material.When storage medium 22 is
When GST phase-change material, first electrode metal can choose the materials such as TiN, W, TiAlN, TiW.The thickness of storage medium 22 also because
The difference of material and can choose different-thickness value.Particularly, for resistance variations storage material, the thickness of storage medium 22
Degree is between 10nm to 100nm.Second electrode 23 is deposited on the outside of 22a and the top of 22b and 22.Second electrode 23 is selected from
One or several kinds of alloys of the metals such as Pt, Ag, Cu, TaN, TiN, Al, W.The thickness of second electrode 23 is without particular/special requirement, most
It is greater than 10nm less.The top of second electrode is interconnection metal 26.Interconnect metal 26 can it is identical as second electrode material can also be with
It is different.For Al interconnection architecture, interconnecting metal 26 can be Al.For Cu interconnection architecture, interconnecting metal 26 can be Cu.Mutual
Even the top of metal 26 is (N+1) layer metal through-hole interconnection 27.Above-mentioned all metals are carried out by first medium 20
Isolation.First medium 20 is layer insulation medium, such as the reduction by plasma TEOS or for the parasitic capacitance between wiring
Effectively constituted containing oxyfluoride (such as FSG) or low-k material.
By being made into structure as shown in Figure 1, when first electrode 21 and second electrode 22 apply offset programming signal respectively
When, the distribution of the electric field strength in storage medium layer 22 is heterogeneous.At 24 position of wedge angle, it will have electric field aggregation effect
Fruit.For resistance variations storage material, conductive filament can be formed in the maximum position of electric field strength.For phase transition storage
For, due to horn structure herein, highest current density, heating effect is significant, therefore can reduce writing for phase transition storage
Program voltage.
In order to verify electric field strength in the congregational rate of sharp angular position, Fig. 2~Fig. 5 is using COMSOL multiple physical field mould
Quasi- software carries out the electric-field intensity distribution under electrostatic field environment to the non-volatile memory device and calculates.This non-volatile is deposited
For storing up element 200, first electrode 21 is reverse tapered shape, storage medium 22 and 23 uniform ring of second electrode around being deposited on inverted cone shape
The side and peripheral region of structure.Therefore total is axisymmetry structure.A section is selected to carry out electric field strength
It simulates, the analog result in this plane can be promoted in stereochemical structure to come.
Fig. 2A is the section rough schematic view of non-volatile memory device 200, sets top electrode for first electrode, powers on
Pole applies offset programming signal；Lower electrode, lower electrode ground connection are set by second electrode.Fig. 2A is the first electrode 21 of Fig. 1, deposits
The simplification figure of 23 region storage media layer 22a and second electrode, rotates clockwise 30 ° for Fig. 2A, can be obtained Fig. 1's
Partial graphical.Fig. 2 B is the geometry division figure in COMSOL software to structure shown in Fig. 2A, abscissa and ordinate
Unit is nanometer.30nm wherein is set by the thickness of storage medium 22, this is for the storage medium of resistance-varying type
It is reasonably, to set 6.0 for the relative dielectric constant of storage medium 22, this stores several resistance variations studied extensively
Material, for AlOx, TaOx material, and rationally.0~300nm in abscissa in Fig. 2 B, in ordinate 0~700nm area
Domain is the second electrode region, and the region that abscissa is 300nm~330nm, ordinate is 300nm~400nm is that resistance variations are situated between
Matter region, abscissa be 330nm~600nm, ordinate from the trapezoid area of 300nm~700nm be first electrode area.Wherein
Angle between first electrode and second electrode is 70 °, i.e. the on-right angle acute angle of the right-angled trapezium of the second electrode region in Fig. 2 B
It is 70 °.Horn structure 24 is set as 70 °, this is reasonable for technique manufacture.When carrying out electric field simulation calculating, wherein
Top electrode applies program voltage 5V, and lower electrode ground connection is set as 0V.The setting of this voltage is for the non-easy of resistance variations type
It is reasonable for the property lost memory element.
Fig. 3 shows the result of static field simulation.Distribution of the electric field strength in storage medium 22 is not as the result is shown for this
Uniformly.Part except angle in storage medium 22a and 22b is referred to as sandwich structure part by us, by 24 institute of angle
Position be referred to as horn structure part.For simplified planar structure, the area approximation of sharp corner is electric herein in point
Field intensity levels off to infinity.For simplified stereochemical structure, the area approximation of sharp corner position is electric herein in line
Field intensity also levels off to infinity.But for the device manufactured in practice, sharp corner has real area, and herein
Area it is small compared with the area at other positions in storage medium.As shown in figure 3, electric-field intensity distribution is uniform at sandwich structure,
It is uniform that gray value is shown as in figure.At lower 24 position of wedge angle, electric field strength be increased dramatically, and exist shown in FIG as gray value
Wedge angle becomes larger at 24 position, as shown in coordinate is (330,300) in figure, the color of color around the point than other positions
It is deep.In order to further analyze the electric field strength variation at sandwich structure and at 24 position of wedge angle, We conducted further
Analysis, as shown in Figure 4 and Figure 5.
Fig. 4 shows the electric field strength analog result at sandwich position.It is vertical in Fig. 2 B that Fig. 4 A shows that we intercept
The position that coordinate value is 500nm carries out electric field strength calculating, as shown in the grey straight line in Fig. 4 A.Fig. 4 B is shown selected by Fig. 4 A
The electric-field intensity distribution at grey linear position selected.The results show that electric field strength is uniformly distributed in storage medium layer 22a,
Value is about 1.5*108V/m。
Fig. 5 shows the electric field strength analog result at 24 position of wedge angle.It is vertical in Fig. 2 B that Fig. 5 A shows that we intercept
The position that coordinate value is 300nm carries out electric field strength calculating, as shown in the grey straight line in Fig. 5 A.Fig. 5 B is shown selected by Fig. 5 A
The electric-field intensity distribution at grey linear position selected.The results show that at the angular position of storage medium layer 22a and 22b, electricity
The distributed nonlinear of field intensity, from first electrode to second electrode direction, electric field strength is by 1.5*108V/m is gradually increased, and is being leaned on
There is maximum at nearly second electrode position.In the case where simplifying situation, electric field strength is infinity at maximum position, although this is right
It is not applicable in actual conditions, but from the analog result it can be seen that the change procedure that electric field is gradually increased.Then we obtain
Conclusion, at 24 position of wedge angle in the storage medium 22 of the non-volatile memory device 200, compared in storage medium 22
Other positions, electric field strength is larger, plays the effect of aggregation.
Hereinafter, being illustrated referring to manufacturing method of the attached drawing to non-volatile memory device proposed by the invention.
Fig. 6 to Figure 11 is the manufacturing method cross-sectional view for indicating the major part of non-volatile memory device 200 of the invention,
The manufacturing method is compatible with standard CMOS logic manufacturing process.
Firstly, 31 left side is storage array part, and 31 right side is logic as shown in fig. 6,31 be truncation signal icon
Part.For logical gate, metal throuth hole 30 can be the contact metal connected with bottom transistor, be also possible to connect
The via metal of n-th layer and (N+1) layer metal interconnecting wires.For storage array, 21 be first electrode.Metal throuth hole 30
Be first medium 20 with the periphery of first electrode 20, first medium 20 is layer insulation medium, such as by plasma TEOS or
Oxyfluoride (such as FSG) is effectively contained for the reduction of the parasitic capacitance between wiring or low-k material is constituted.
It is introduced first against storage array part.The manufacturing process of first electrode 21 is first to deposit first medium layer
20, the hole of first electrode 21 is etched with the method for photoetching on first medium layer 20, this etching uses dry etching.It adopts
With certain process conditions, so that the hole etched is back taper, and the area of upper bottom surface is greater than bottom surface area.Later
21 metal material of first electrode is filled using sputtering or other deposition methods, after filling, using cmp method
It is processed by shot blasting, obtains structure as shown in FIG. 6.For logical gate, the preparation method and memory of metal 30 are contacted
The preparation method of partial first electrode 21 is substantially similar and prepares to be formed simultaneously, but wants to the shape of contact metal 30 without special
It asks.
Then, as shown in fig. 7, using a mask plates, 25 logical gate is blocked with photoresist, and only by 31 left sides
Storage array part carries out wet etching.Entire silicon wafer is placed in DHF solution or BHF solution, is etched away certain thickness
First medium layer 20.Etch thicknesses depend on the thickness of the storage medium layer 22 of non-volatile memory device, and to guarantee one
Determine the thickness of the second electrode 23 of thickness.Such as if it is desired to the minimum 20nm of the thickness of second electrode 23, and storage medium layer 22
With a thickness of 20nm, then the thickness fallen using wet etching will guarantee to be greater than 40nm.Pass through the structure obtained after the step
As shown in fig. 7, the inverted cone shape of first electrode 21, which understands some rotary table with specific thicknesses, is exposed to first medium layer 20
Outside.So far, the top view of the memory portion in 31 left side is as shown in figure 12,21 ordered arrangement of first electrode of back taper,
First medium 20 is filled in gap.
Then, as shown in figure 8, deposition storage medium layer 22.The deposition method of storage medium layer 22 is because of storage medium difference
And it is different, for example, by using a variety of methods such as sputtering method, technique for atomic layer deposition.Non-volatile memory element of the invention requires it
The deposition technique of storage medium layer 22, it is necessary to guarantee that the covering of storage medium layer 22 has good conformality.I.e. each
The cladding thickness for setting place is uniform.
Then, as shown in figure 9, after having deposited storage medium 22,23 metal material of second electrode is deposited.The thickness of deposition
Degree will at least cover the upper surface of first electrode.Later using the method for chemically mechanical polishing by silicon wafer polishing, until leaking out the
The upper surface of one electrode 21.For logical gate, second electrode 23 and storage medium layer 22 are removed, using chemically mechanical polishing side
Method is used cooperatively dry etching, until leaking out upper surface and the first medium layer 20 of first electrode 21.There cannot be second electrode 23
With the residual of storage medium 22.Obtain structure as shown in Figure 9.So far, the top view of storage array part is as shown in figure 13.
Then, as shown in Figure 10, for the storage array part in 31 left sides, storage unit first is defined with dry etching, it will
Isolated etching is carried out between different storage units.The size of storage unit is also defined in this step.This step needs
Using mask plate and to carry out photoetching process.Single storage unit must include first electrode 21, storage medium layer 22 and the
The size of two electrodes 23, the first electrode that the single storage unit is included can be the complete cross section of first electrode,
It is also possible to the partial cross sectional of first electrode；The storage medium layer 22 that the storage unit is included may include first electrode
The 22a and part 22b of entire lateral surface, are also possible to the 22a and part 22b of the portions of lateral side comprising first electrode；It is described
The area for the second electrode 23 that storage unit includes can surround the entire lateral surface of first electrode, can also be with circle segment first
The lateral surface of electrode.The cross-sectional shape of the storage unit can be circle be also possible to it is rectangular.By defined storage
After region etch falls other than the region of unit, first medium layer 20 is deposited.The thickness of the first medium layer 20 of deposit is big
In the sum of following two size.First size is the depth of hole caused by previous step etches；Second size is next
The height of layer metal interconnecting wires 26.After deposit first medium layer 20 finishes, cmp method is used to entire silicon wafer
It is polished, obtains structure as shown in Figure 10.
Then as shown in figure 11.N-th layer metal interconnecting wires deposition and definition are carried out, and forms (N+1) layer metal and leads to
Hole.It is illustrated by taking copper-connection manufacturing process as an example, carries out photoetching on the first medium layer 20 of previous step, etch n-th layer
After the shape of metal interconnecting wires, Cu interconnection line 26 is deposited using galvanoplastic.After deposition finishes, it is processed by shot blasting.It sinks later
Product first medium layer 20, thickness should be greater than the height of (N+1) layer metal throuth hole, carry out (N+1) using photoetching process later
The definition etching of layer metal throuth hole and (N+1) layer metal interconnecting wires, after etching, using galvanoplastic depositing Cu metal, it
It is processed by shot blasting afterwards using chemical mechanical polishing method.So far, non-volatile memory device 200 is compatible with standard logic process
Manufacturing process has finished.Logical gate later is identical with the manufacturing process of storage array part.Form the knot of Figure 11
The interconnection fabrication processes of aluminium interconnection architecture can also be used in structure.
In the non-volatile memory device of the embodiment of the present invention, storage medium layer can annular be enclosed in the electricity of back taper first
The side of pole, and can one horn structure of self-assembling formation between first electrode and second electrode.When the first and second electrodes point
Not Shi Jia program voltage when, the electric field strength of the sharp corner in storage medium layer close to second electrode is the largest, and compares sandwich
Electric field strength at structure is big.The presence of this horn structure assembles electric field strength at this, and conductive path is formed here,
The position occurred can be changed with fixed resistance, and the operation voltage of storage unit can be reduced, be conducive to imperceptibility and great Rong
Quantization.
Example above primarily illustrates the structure and manufacturing method of non-volatile memory device of the invention.Although only to it
In some embodiments of the present invention be described, but those of ordinary skill in the art are it is to be appreciated that the present invention can be
Implement without departing from its spirit in range in many other forms.Therefore, the example shown is considered as showing with embodiment
Meaning property and not restrictive, in the case where not departing from the spirit and scope of the present invention as defined in appended claims,
The present invention may cover various modification and replacement.
Symbol description:
200: non-volatile memory device proposed by the present invention；
20,104: first medium layer；
21,107: first electrode metal layer；
22a, 22b: storage medium layer；
23,105: second electrode metal layer；
24: horn structure；
25: photoresist；
26: the 1 layers of metal wiring layer or n-th layer metal wiring layer；
27: the 1st metal throuth hole or (N+1) a metal throuth hole of logical gate；
30: the contact metal or n-th via metal of logical gate；
31: truncation signal icon；
100,10: electro-resistance element；
101: substrate；
102: adhesion layer；
103: conductive layer；
106: resistance change layer.
Claims (9)
1. a kind of non-volatile memory device, comprising:
Inverted cone shape first electrode；
Storage medium layer comprising first part and second part, wherein the first part is attached to inverted cone shape first electrode
Lateral surface on, the lateral surface of the second part and the inverted cone shape first electrode is non-parallel to be arranged so that and described first
Part connects and forms angle；
Second electrode is formed in the interior of the angle formed between the first part and second part of the storage medium layer
Side；
The storage medium layer is selected from aluminium oxide (AlOx), tungsten oxide (WOx), hafnium oxide (HfOx), tantalum oxide (TaOx), oxidation
Titanium (TiOx), silica (SiO2), zinc oxide (ZnOx), nickel oxide (NiOx), one of germanium antimony tellurium alloy (GeSbyTex)
The combination of material or different materials；
The non-volatile memory device is resistance random storage, and the storage medium layer is resistive memory medium layer,
In, when the resistive memory medium layer is configured as the offset programming signal between the first electrode and two electrode,
The angle of the corresponding storage medium layer substantially positions the conductive filament formed for storing programming；
The first electrode is selected from by Pt, Ag, Cu, TaN, TiN, Al, W or wherein one of alloy material is formed；
The second electrode is selected from by Pt, Ag, Cu, TaN, TiN, Al, W or wherein one of alloy material is formed；
The inverted cone shape first electrode is formed in first medium layer and outside the biggish upper part of inverted cone shape first electrode
Dew forms pylon structure, the first part and second part and is formed by conformal be covered in the pylon structure, wherein first
Part surrounds the lateral surface of the upper part of the first electrode, and the second part is formed in the upper table of the first medium layer
Face.
2. non-volatile memory device as claimed in claim 1, wherein by the cone angle size that the inverted cone shape first electrode is arranged
The angular dimension of the angle is arranged.
3. such as the non-volatile memory device of claims 1 or 2, wherein the angle of the angle is greater than or equal to 60 ° and is less than
Or it is equal to 80 °.
4. non-volatile memory device as claimed in claim 1, wherein the thickness of the storage medium layer be greater than or equal to 10nm and
Less than or equal to 100nm.
5. non-volatile memory device as claimed in claim 1, wherein the non-volatile memory device is integrated setting CMOS electricity
In the rear end structure on road.
6. non-volatile memory device as claimed in claim 1, wherein the inverted cone shape first electrode is for connecting interconnection line layer
Metal via structure, the second electrode be the interconnection line layer a part.
7. such as the manufacturing method of any non-volatile memory device of claim 1 ~ 6 characterized by comprising
Inverted cone shape first electrode is formed in first medium layer；
To the first medium layer selective etching so that the exposed formation column in the biggish upper part of the inverted cone shape first electrode
Platform structure；
The conformal storage medium layer being covered on the pylon structure and first medium layer is deposited, to make the storage medium layer extremely
Few includes the first part being attached on the lateral surface of inverted cone shape first electrode and the lateral surface with the inverted cone shape first electrode
The second part of non-parallel setting, the first part connect with the second part and form angle；In the storage medium
The inside of the angle formed between the first part and second part of layer forms second electrode.
8. manufacturing method as claimed in claim 7, which is characterized in that in the step of forming the second electrode, comprising:
Deposit second electrode material layer；
Chemical mechanical grinding is carried out to the second electrode material layer until the upper surface of the pylon structure is exposed.
9. manufacturing method as claimed in claim 7, which is characterized in that the rear end structure system of the manufacturing method and cmos circuit
Standby technique is integrated；
Wherein, the first medium layer is metal interlamination medium layer, and the inverted cone shape first electrode is for connecting interconnection line layer
Metal via structure, the second electrode be the interconnection line layer a part.
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