CN106299110A - Non-volatile memory device and the manufacture method of write operation voltage can be reduced - Google Patents
Non-volatile memory device and the manufacture method of write operation voltage can be reduced Download PDFInfo
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Abstract
The invention belongs to non-volatile memory technologies field, it is provided that a kind of non-volatile memory device reducing write operation voltage and manufacture method.The non-volatile memory device of the present invention, including: inverted cone shape the first electrode；Storage medium layer, it includes Part I and Part II, wherein said Part I is attached on the lateral surface of inverted cone shape the first electrode, and be arranged so that non-parallel with the lateral surface of described inverted cone shape the first electrode of described Part II is connected with described Part I and forms angle；And second electrode, the inner side of the described angle formed between its Part I being formed at described storage medium layer and Part II.The non-volatile memory device of the present invention is by forming the angle structure of storage medium layer between the first electrode and the second electrode, and write operation voltage is reduced and uniformly, preparation is simple, low cost.
Description
Technical field
The invention belongs to non-volatile memory technologies field, relate to one and can reduce non-volatile
The memory element of the write operation voltage of memory element and manufacture method thereof.
Background technology
For low-power consumption and the high-density applications target of non-volatile memory semiconductor device, have
Multiple research launches, including on material, on device architecture, in manufacture method and peripheral circuit sets
A series of exploration has been carried out on meter.
Even if the data that flash memory is storage the most also can obtain the non-volatile memory retained
Represent.Flash memory has non-volatile, different from volatile memory.But, flash memory has low integrated
Spend and need the most voltage-operated shortcoming.
Nonvolatile storage having been carried out much research now, these nonvolatile storages include
Magnetic random memory (MRAM), ferroelectric RAM (FRAM), phase-change random access
Access memorizer (PRAM) and resistive ram (RRAM).
If the magnitude of voltage required for operation memory element reduces, then the transistor of peripheral circuit
Size just can reduce, and thus can improve the integrated number of memory element in unit are.
Along with the further micro of memory device size, the device parameters between memory element and electricity
Learning the fluctuation aggravation of parameter, this problem can cause the reliability of storage array to reduce.Reduce and write behaviour
Make voltage and can improve the reliability of array to a certain extent.Particularly, resistor random-access is deposited
For access to memory, the conductive filament that applying initial breakdown voltage is formed is in storage medium layer
Randomly generating, along with reducing of device size, what conductive filament produced is located proximate to device edge
The probability in etching injury region can increase, etching injury region forms the size meeting of conductive filament
Relatively big, the electric current flowed through also can be relatively big, and this will be unfavorable for the requirement of low-power consumption.Therefore, if conducting electricity
Filament can produce the center at device cell regularly, this can suppress each device
The size of the initial breakdown voltage between unit and deviation thereof, it is possible to improve the reliable of storage array
Property.
The U.S. Patent No. US 2013,0112936A1 of Zhiqiang Wei et al., entitled
The patent of " Resistance change element and manufacturing method therefor "
In propose a kind of device structure design, as shown in figure 14.So that electric field is in fixing position
Put gathering so that initial breakdown occurs in the position of fixing needle-like portion electrode, for resistance-varying type
Memory element for, can control occur resistance variations phenomenon filament region (filament)
Happening part.Thereby, it is possible to resistance when suppressing the initial breakdown voltage of each element, action
The deviation of value.The design to electro-resistance element is needed as deviation countermeasure as a result, it is possible to cut down
The surplus that size is added, it is possible to realize the storage granular of device, high capacity.
The U.S. Patent No. US 2014,0061573A1 of Takumi Mikawa et al., entitled
“Nonvolatile memory element,Nonvolatile memory device,and methods of
Manufacturing the same " patent in propose a kind of device structure design, such as Figure 15 institute
Show, so that conductive filament is formed at the stage portion that different two-layer resistive dielectric layers is formed
Position, and this stepped portions is in the center of memory element.And the high resistant of stepped portions
The storage medium thickness of value reduces, and can reduce the initial breakdown voltage forming conductive filament.And
The position that conductive filament produces is fixed, and can reduce the inclined of initial breakdown voltage between memory element
Difference.When the size reduction of memory element, centre is affected the least by edge, can subtract
Between little different memory element, the deviation of resistance value, can improve reliability, it is possible to realize storage device
Granular, high capacity.
It appeared that, it has been suggested that the structure design of non-volatile memory device, substantially logical
Cross position that fixing conductive filament occurs to reduce write operation voltage and the deviation of write operation voltage, real
The granular of existing storage device, high capacity.
Summary of the invention
It is an object of the invention to, it is provided that a kind of have the non-volatile of new memory element structure and deposit
Storage element.
For realizing object above or other purposes, the present invention provides techniques below scheme.
It is an aspect of this invention to provide that provide a kind of non-volatile memory device, comprising:
First electrode and the second electrode, and storage Jie being placed between the first electrode and the second electrode
Matter layer.Wherein the first electrode is inverted cone, and its cone angle is α, 60 °≤α≤80 °.Storage medium
Layer, including Part I and Part II, wherein said Part I is attached to inverted cone shape the first electricity
On the lateral surface of pole, described Part II is non-parallel with the lateral surface of described inverted cone shape the first electrode to be set
Put to such an extent as to be connected with the lower end of described Part I and form angle.Second electrode is formed at described
The inner side of the described angle formed between Part I and the Part II of storage medium layer.
In embodiment described before, described storage medium layer can be variable-resistance material, bag
Include the variable-resistance material such as metal-oxide, be selected from
A kind of material in AlOx, WOx, HfOx, TaOx, TiOx, SiO2, ZnOx, NiOx, GeSbyTex
Or the combination of different materials..
In the most described embodiment, described first electrode material can be by being selected from
A kind of material in Pt, Ag, Cu, TaN, TiN, Al, W or its alloy is formed.
In the most described embodiment, described second electrode material can be by being selected from
A kind of material in Pt, Ag, Cu, TaN, TiN, Al, W or its alloy is formed.
The present invention can not only realize as such electro-resistance element, additionally it is possible to as being used for making
The manufacture method making such electro-resistance element realizes.
It is an aspect of this invention to provide that provide the manufacture method of a kind of non-volatile memory device,
Comprising:
Inverted cone shape the first electrode is formed in first medium layer；
First medium layer is carried out selective etching so that described inverted cone shape the first electrode bigger upper
End portion exposes formation pylon structure；
Deposit the conformal storage medium layer being covered on this pylon structure and first medium layer, thus
Make that described storage medium layer at least includes being attached on the lateral surface of inverted cone shape the first electrode first
Part and the Part II of the non-parallel setting of lateral surface with described inverted cone shape the first electrode, described the
A part of and described Part II is connected and forms angle；Part I in described storage medium layer
And the inner side of the described angle formed between Part II forms the second electrode.
Deposit the second electrode material layer；Described second electrode material layer is carried out cmp straight
Upper surface to described pylon structure exposes.
The manufacture method of this non-volatile memory device and the rear end structure of cmos circuit prepare work
Skill is mutually integrated；
The non-volatile memory device of the present invention is by being formed between the first electrode and the second electrode
The angle structure of storage medium layer, write operation voltage is reduced and uniformly, preparation is simple, cost
Low and convenient compatible with standard CMOS process.
Accompanying drawing explanation
From combine accompanying drawing described further below, it will make the present invention above and other purpose and
Advantage is more fully apparent from, and wherein, same or analogous key element is adopted and is indicated by the same numeral.
Fig. 1 is the section view of the structure of the non-volatile memory device according to one embodiment of the invention
Figure.
Fig. 2 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The simplification structure that the analog simulation of congregational rate is used.
Fig. 2 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The reduced parameter that the analog simulation of congregational rate is used.
Fig. 3 is that the electric field of the structure of the non-volatile memory device according to one embodiment of the invention gathers
The analog result of collection effect.
Fig. 4 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 4 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 5 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 5 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 6 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Fig. 7 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Fig. 8 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Fig. 9 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 10 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 11 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 12 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The top view of the operation of method.
Figure 13 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The top view of the operation of method.
Figure 14 is the non-volatile memory device sectional view of prior art.
Figure 15 is the non-volatile memory device sectional view of prior art.
Detailed description of the invention
Be described below is that the multiple of the present invention may some in embodiments, it is desirable to provide to this
Bright basic understanding, it is no intended to confirm that the crucial of the present invention or conclusive key element or limit is wanted
The scope of protection.Easy to understand, according to technical scheme, in the reality not changing the present invention
Under matter spirit, one of ordinary skill in the art can propose other the realization sides that can mutually replace
Formula.Therefore, detailed description below and accompanying drawing are only the examples to technical scheme
Property explanation, and be not to be construed as the whole of the present invention or be considered as the restriction to technical solution of the present invention
Or limit.
In explained below, clear and simple and clear for describe, not all many to shown in figure
Individual parts are described in detail.It is that those of ordinary skill in the art carry shown in the drawings of multiple parts
The disclosure being fully able to realize for the present invention.To those skilled in the art, many
The operation of parts is all to be familiar with and obvious.
Fig. 1 represents the cross section of the non-volatile memory device 200 made by this experiment.Non-
Volatile memory elements 200 is to embed the first electrode 21, storage medium in first medium layer 20
Layer the 22, second electrode 23 is constituted, and is formed on next layer of metal interconnecting wires 26, metal afterwards
Through-hole interconnection 27.With reference to Fig. 1, the first electrode 21 be shaped as inverted cone, cone angle is by technique system
Standby conditional decision, can form the angle between 60 ° to 80 °.First electrode can be
The alloy of one or more in the metals such as Pt, Ag, Cu, TaN, TiN, Al, W.Storage medium layer 22
It is divided into two parts, is respectively attached to the Part I 22a of the first electrode 21 inverted cone shape lateral surface,
And with the first electrode 21 inverted cone shape lateral surface nonparallel Part II 22b.Storage medium material
22 can be the material of resistance variations type, such as aluminium oxide (AlOx), tungsten oxide (WOx),
Hafnium oxide (HfOx), tantalum oxide (TaOx), titanium oxide (TiOx), silicon oxide (SiO2), oxygen
Change zinc (ZnOx), a kind of material in nickel oxide (NiOx) or the combination of different materials.22a
It is identical with the material composition of 22b, the technique deposit used during deposition storage medium material 22
Mode has conformality and covers feature, and the thickness of 22a and 22b part is identical.Wherein 22a
Angle 24 is constituted with 22b.The material of the first electrode 21 has selected because of the difference of storage medium
Select.Such as, when storage medium 22 is AlOx, the first electrode 21 can use TaN, TiN,
The metals such as Al, W；And when storage medium 22 is SiO2, the first electrode 21 can use Ag,
The ripple metal alive such as Cu.The material of storage medium 22 can also be germanium antimony tellurium alloy (GeSbyTex)
Phase-change material.When storage medium 22 is GST phase-change material, the first electrode metal can select
The materials such as TiN, W, TiAlN, TiW.The thickness of storage medium 22 is also because of the difference of material
Different-thickness value can be selected.Particularly, for resistance variations storage material, storage medium
The thickness of 22 is between 10nm to 100nm.Second electrode 23 is deposited on outside and the 22b of 22a
And the top of 22.Second electrode 23 selected from Pt, the one of the metal such as Ag, Cu, TaN, TiN, Al, W
Kind or several alloys.The thickness of the second electrode 23 is without particular/special requirement, minimum more than 10nm.
Second electrode be arranged above interconnect metal 26.Interconnection metal 26 can be identical with the second electrode material
Can also be different.For Al interconnection architecture, interconnection metal 26 can be Al.Cu is interconnected
System, interconnection metal 26 can be Cu.Interconnection metal 26 be arranged above (N+1) layer gold
Belong to through-hole interconnection 27.Above-mentioned all metals are all to be isolated by first medium 20.First
Medium 20 is layer insulation medium, such as by plasma TEOS or for the parasitism between wiring
The reduction of electric capacity is effectively constituted containing oxyfluoride (such as FSG) or low-k material.
By making structure as shown in Figure 1, when the first electrode 21 and the second electrode 22 are executed respectively
When being biased programming signal, the distribution of the electric field intensity in storage medium layer 22 is heterogeneous.
In wedge angle 24 position, it will there is electric field congregational rate.For resistance variations storage material,
Conductive filament can be formed in the position that electric field intensity is maximum.For phase transition storage, due to this
The horn structure at place, highest current density, heats is notable, therefore can reduce phase change memory
Device write program voltage.
In order to verify the electric field intensity congregational rate in wedge angle position, Fig. 2～Fig. 5 is to use
This non-volatile memory device is carried out under electrostatic field environment by COMSOL multiple physical field simulation softward
Electric-field intensity distribution calculate.For this non-volatile memory device 200, the first electrode 21
For reverse tapered shape, storage medium 22 and the second electrode 23 uniform ring are around being deposited on inverted cone shape structure
Side and peripheral region.Therefore total is axisymmetry structure.A section is selected to carry out
The simulation of electric field intensity, the analog result in this plane can be promoted in stereochemical structure and come.
Fig. 2 A is the section rough schematic view of non-volatile memory device 200, is arranged by the first electrode
For upper electrode, upper electrode applies offset programming signal；Second electrode is set to bottom electrode, lower electricity
Pole ground connection.Fig. 2 A is first electrode 21 of Fig. 1, storage medium layer 22a and the second electrode 23
The simplification figure of region, turns clockwise Fig. 2 A 30 °, i.e. can get the part of Fig. 1
Figure.Fig. 2 B is the geometry division figure in COMSOL software to the structure shown in Fig. 2 A,
The unit of its abscissa and vertical coordinate is nanometer.Wherein the thickness of storage medium 22 is set to
30nm, this is rational for the storage medium of resistance-varying type, by storage medium 22
Relative dielectric constant is set to 6.0, and this is for several widely studied resistance variations storage materials,
For AlOx, TaOx material, also it is reasonable.In Fig. 2 B in abscissa 0～300nm, vertical sit
In mark, the region of 0～700nm is the second electrode region, and abscissa is 300nm～330nm, vertical coordinate
Region for 300nm～400nm is resistance variations areas of dielectric, and abscissa is 330nm～600nm, vertical
Coordinate is first electrode area from the trapezoid area of 300nm～700nm.Wherein the first electrode and second
Angle between electrode is 70 °, i.e. in Fig. 2 B, the on-right angle of the right-angled trapezium of the second electrode region is sharp
Angle is 70 °.Horn structure 24 is set to 70 °, and this, for technique manufactures, is rational.
Carry out electric field simulation calculate time, wherein go up electrode applying program voltage 5V, bottom electrode ground connection,
It is set to 0V.This voltage arrange for resistance variations type non-volatile memory device and
Speech, is rational.
Fig. 3 shows the result of static field simulation.This result display electric field intensity is at storage medium 22
In be unevenly distributed.Part outside angle in storage medium 22a and 22b is claimed by we
For sandwich structure part, the position at angle 24 place is referred to as horn structure part.Right
For the planar structure simplified, the area approximation of sharp corner is in point, and electric field intensity levels off to herein
Infinitely great.Similarly for simplify stereochemical structure for, the area approximation of sharp corner position in line,
Electric field intensity also levels off to infinity herein.But for the device manufactured in reality, sharp corner
There is real area, and area herein is little compared with the area at other positions in storage medium.As
Shown in Fig. 3, at sandwich structure, electric-field intensity distribution is uniform, is shown as gray value in the drawings
Homogeneous.In lower wedge angle 24 position, electric field intensity is increased dramatically, shown in FIG as gray value
Become big, as in figure, coordinate is shown in (330,300), around this point in wedge angle 24 position
Color is deeper than the color of other positions.In order to analyze at sandwich structure further and wedge angle 24
Put the electric field intensity change at place, We conducted and further analyze, as shown in Figure 4 and Figure 5.
Fig. 4 shows the electric field intensity analog result of sandwich position.Fig. 4 A shows us
The position that ordinate value is 500nm intercepted in Fig. 2 B carries out electric field intensity calculating, such as Fig. 4 A
In Lycoperdon polymorphum Vitt straight line shown in.Fig. 4 B shows the electric field at the Lycoperdon polymorphum Vitt linear position selected by Fig. 4 A
Intensity distributions.Result shows, in storage medium layer 22a, electric field intensity is uniformly distributed, and value is big
It is about 1.5*108V/m。
Fig. 5 shows the electric field intensity analog result of wedge angle 24 position.Fig. 5 A shows us
The position that ordinate value is 300nm intercepted in Fig. 2 B carries out electric field intensity calculating, such as Fig. 5 A
In Lycoperdon polymorphum Vitt straight line shown in.Fig. 5 B shows the electric field at the Lycoperdon polymorphum Vitt linear position selected by Fig. 5 A
Intensity distributions.Result shows, at the angular position of storage medium layer 22a and 22b, and electric-field strength
The distributed nonlinear of degree, from the first electrode to the second electrode direction, electric field intensity is by 1.5*108V/m
It is gradually increased, at the second electrode position, maximum is occurring.Maximum position in the case of simplifying
Put place's electric field intensity for infinity, although this is inapplicable for practical situation, but from this analog result
It can be seen that the change procedure that electric field is gradually increased.Then we conclude that, non-volatile at this
Wedge angle 24 position in the storage medium 22 of property memory element 200, compared to storage medium 22
In other positions, electric field intensity is relatively big, serves the effect of gathering.
Hereinafter, referring to the drawings the manufacture method of non-volatile memory device proposed by the invention is entered
Row explanation.
Fig. 6 to Figure 11 is the major part of the non-volatile memory device 200 representing the present invention
Manufacture method sectional view, this manufacture method is compatible with standard CMOS logic manufacturing process.
First, as shown in Figure 6,31 is to block signal icon, and the left side of 31 is storage array portion
Point, the right side of 31 is logical gate.For logical gate, metal throuth hole 30 can be with
The contacting metal that bottom transistor connects, it is also possible to be to connect n-th layer and (N+1) layer metal
The via metal of interconnection line.For storage array, 21 is the first electrode.Metal throuth hole 30
Being first medium 20 with the periphery of the first electrode 20, first medium 20 is layer insulation medium, example
As by plasma TEOS or for the effective fluorine-containing oxidation of reduction of parasitic capacitance between wiring
Thing (such as FSG) or low-k material are constituted.
It is introduced first against storage array part.The manufacture process of the first electrode 21 is, first
Deposition first medium layer 20, etches the first electrode by the method for photoetching on first medium layer 20
The hole of 21, this etching uses dry etching.Use certain process conditions so that etch
Hole be inverted cone, and the area of upper bottom surface is more than bottom surface area.Afterwards use sputtering or
Other deposition process fill the first electrode 21 metal material, after filling, use chemical machinery
Finishing method is processed by shot blasting, obtains structure as shown in Figure 6.For logical gate, it connects
The preparation method touching metal 30 is substantially similar with the preparation method of the first electrode 21 of memory portion
And prepare formation, but to the shape of contacting metal 30 without particular/special requirement simultaneously.
Then, as it is shown in fig. 7, use a mask plates, 25 logical gate is hidden with photoresist
Gear, and only the storage array part on the left of 31 is carried out wet etching.Whole silicon chip is placed in DHF
In solution or BHF solution, etch away certain thickness first medium layer 20.Etch thicknesses takes
Certainly in the thickness of storage medium layer 22 of non-volatile memory device, and certain thickness to be ensured
The thickness of the second electrode 23.If such as requiring the minimum 20nm of thickness of the second electrode 23,
And the thickness of storage medium layer 22 is 20nm, then the thickness using wet etching to fall to ensure greatly
In 40nm.By the structure that obtains after this step as it is shown in fig. 7, the back taper of the first electrode 21
Shape is understood some round platform with specific thicknesses and is exposed to the outside of first medium layer 20.So far,
As shown in figure 12, the first electrode 21 of inverted cone has the top view of the memory portion in the left side of 31
Sequence arranges, and first medium 20 is filled in gap.
Then, as shown in Figure 8, deposition storage medium layer 22.The deposition side of storage medium layer 22
Method is different because storage medium is different, multiple for example with sputtering method, technique for atomic layer deposition etc.
Method.The non-volatile memory element of the present invention requires the deposition technique of its storage medium layer 22, must
Need ensure that the covering of storage medium layer 22 has good conformality.I.e. covering at each position
Lid thickness is uniform.
Then, as it is shown in figure 9, after having deposited storage medium 22, deposit the second electrode 23
Metal material.The thickness of deposition at least to cover the upper surface of the first electrode.Use chemistry machine afterwards
The method of tool polishing is by silicon wafer polishing, until spilling the upper surface of the first electrode 21.For logic
Part, removes the second electrode 23 and storage medium layer 22, uses cmp method, joins
Close and use dry etching, until spilling upper surface and the first medium layer 20 of the first electrode 21.No
Can there be the second electrode 23 and the residual of storage medium 22.Obtain structure as shown in Figure 9.So far,
The top view of storage array part is as shown in figure 13.
Then, as shown in Figure 10, for the storage array part on the left of in the of 31, dry etching is first used
Definition memory element, carries out isolated etching by between different memory element.The size of memory element
It is defined the most in this step.This step needs use mask plate and carry out photoetching process.Single
Individual memory element must comprise the first electrode 21, storage medium layer 22 and the second electrode 23, institute
The size stating the first electrode that single memory element is comprised can be the complete horizontal stroke of the first electrode
Cross section, it is also possible to be the partial cross sectional of the first electrode；The storage that described memory element is comprised is situated between
Matter layer 22 can comprise 22a and part 22b of the first whole lateral surface of electrode, it is also possible to is to comprise
The 22a of the portions of lateral side of the first electrode and part 22b；The second electricity that described memory element comprises
The area of pole 23 can be around the whole lateral surface of the first electrode, it is also possible to circle segment the first electricity
The lateral surface of pole.The shape of cross section of described memory element can be circle can also be square.?
After being fallen by region etch beyond the region of defined memory element, deposit first medium layer
20.The thickness of the first medium layer 20 of deposit is greater than following two size sum.First chi
Very little is the degree of depth of hole produced by previous step etching；Second size is next layer of metal interconnecting wires
The height of 26.After deposit first medium layer 20 is complete, chemical machinery is used to throw whole silicon chip
Light method is polished, and obtains structure as shown in Figure 10.
The most as shown in figure 11.Carry out n-th layer metal interconnecting wires deposition and definition, and form the
(N+1) layer metal throuth hole.Illustrate as a example by copper-connection manufacturing process, in the of previous step
Carry out photoetching on one dielectric layer 20, after etching the shape of n-th layer metal interconnecting wires, use electricity
Plating method deposition Cu interconnection line 26.Deposit complete after, be processed by shot blasting.Deposit first afterwards
Dielectric layer 20, thickness should be greater than the height of (N+1) layer metal throuth hole, uses photoetching work afterwards
Skill carries out the definition etching of (N+1) layer metal throuth hole and (N+1) layer metal interconnecting wires,
After etching, use galvanoplastic depositing Cu metal, use chemical mechanical polishing method to carry out afterwards
Polishing.So far, non-volatile memory device 200 manufactures stream with the compatible of standard logic process
Journey is the most complete.Logical gate afterwards is identical with the manufacturing process of storage array part.Shape
The structure becoming Figure 11 is used as the interconnection fabrication processes of aluminum interconnection architecture.
In the non-volatile memory device of the embodiment of the present invention, storage medium layer can annular be enclosed in
The side of inverted cone the first electrode, and can self-assembling formation one between the first electrode and the second electrode
Horn structure.When the first and second electrodes apply program voltage respectively, close in storage medium layer
The electric field intensity of the sharp corner of the second electrode is maximum, than the electric field intensity at sandwich structure place
Greatly.The existence of this horn structure makes electric field intensity at this assemble, and conductive path is formed here,
The position that can occur with fixed resistance change, and the operation voltage of memory element can be reduced, have
It is beneficial to granular and high capacity.
Example above primarily illustrates structure and the manufacturer of the non-volatile memory device of the present invention
Method.Although only some of them embodiments of the present invention being described, but this area being common
Technical staff it is to be appreciated that the present invention can without departing from its spirit with scope in many other
Form is implemented.Therefore, the example shown and embodiment are considered schematic and non-limiting
, in the case of without departing from spirit and scope of the present invention as defined in appended claims,
The present invention may contain various amendments and replacement.
Symbol description:
200: the non-volatile memory device that the present invention proposes；
20,104: first medium layer；
21,107: the first electrode metal layer；
22a, 22b: storage medium layer；
23,105: the second electrode metal layers；
24: horn structure；
25: photoresist；
26: the 1 layers of metal wiring layer or n-th layer metal wiring layer；
27: the 1st metal throuth hole or (N+1) individual metal throuth hole of logical gate；
30: the contacting metal of logical gate or n-th via metal；
31: block signal icon；
100,10: electro-resistance element；
101: substrate；
102: adhesion layer；
103: conductive layer；
106: resistance change layer.
Claims (14)
1. a non-volatile memory device, including:
Inverted cone shape the first electrode；
Storage medium layer, it includes Part I and Part II, the attaching of wherein said Part I
On the lateral surface of inverted cone shape the first electrode, described Part II and described inverted cone shape the first electrode
Non-parallel being arranged so that of lateral surface is connected with described Part I and forms angle；
Second electrode, shape between its Part I being formed at described storage medium layer and Part II
The inner side of the described angle become.
2. non-volatile memory device as claimed in claim 1, it is characterised in that described storage
Dielectric layer be selected from aluminium oxide (AlOx), tungsten oxide (WOx), hafnium oxide (HfOx), tantalum oxide (TaOx),
Titanium oxide (TiOx), silicon oxide (SiO2), zinc oxide (ZnOx), nickel oxide (NiOx), germanium
A kind of material in antimony tellurium alloy (GeSbyTex) or the combination of different materials.
3. non-volatile memory device as claimed in claim 1, it is characterised in that described non-easily
The property lost memory element is resistance random storage, and described storage medium layer is resistance-change memory medium
Layer, wherein, described resistive memory medium layer is configured at described first electrode and described two electrodes
Between offset programming signal time, in the angle of corresponding described storage medium layer substantially position formation use
Conductive filament in storage programming.
4. non-volatile memory device as claimed in claim 1, wherein said first electrode is selected from
By Pt, a kind of material in Ag, Cu, TaN, TiN, Al, W or wherein alloy is formed.
5. non-volatile memory device as claimed in claim 1, wherein said second electrode is selected from
By Pt, a kind of material in Ag, Cu, TaN, TiN, Al, W or wherein alloy is formed.
Non-volatile memory device the most according to claim 1, wherein, described inverted cone shape the first electricity
Pole is formed in first medium layer and shape is exposed in the bigger upper part of inverted cone shape the first electrode
Becoming pylon structure, described Part I and Part II are covered in shape in this pylon structure by conformal
Become, wherein the lateral surface of the upper part of described first electrode of Part I encirclement, described second
Divide the upper surface being formed at described first medium layer.
Non-volatile memory device the most according to claim 6, wherein, by arranging described back taper
The cone angle size of shape the first electrode arranges the angular dimension of described angle.
8. according to the non-volatile memory device of claim 1 or 7, wherein, the angle of described angle
Degree is more than or equal to 60 ° and less than or equal to 80 °.
9. non-volatile memory device as claimed in claim 1, the thickness of wherein said storage medium layer
More than or equal to 10nm and less than or equal to 100nm.
10. non-volatile memory device as claimed in claim 1, wherein said non-volatile memories unit
Part is integrated arranging in the rear end structure of cmos circuit.
The non-volatile memory device of 11. such as claim 10, wherein said inverted cone shape the first electrode
For the metal via structure for connecting interconnection line layer, described second electrode is the one of this interconnection line layer
Part.
The manufacture method of 12. 1 kinds of non-volatile memory devices, it is characterised in that including:
Inverted cone shape the first electrode is formed in first medium layer；
To described first medium layer selective etching so that described inverted cone shape the first electrode bigger upper
End portion exposes formation pylon structure；
Deposit the conformal storage medium layer being covered on this pylon structure and first medium layer, thus
Make that described storage medium layer at least includes being attached on the lateral surface of inverted cone shape the first electrode first
Part and the Part II of the non-parallel setting of lateral surface with described inverted cone shape the first electrode, described the
A part of and described Part II is connected and forms angle；Part I in described storage medium layer
And the inner side of the described angle formed between Part II forms the second electrode.
13. manufacture methods as claimed in claim 12, it is characterised in that forming described second
In the step of electrode, including:
Deposit the second electrode material layer；
Described second electrode material layer is carried out cmp until described pylon structure upper
Surface exposed.
14. manufacture methods as claimed in claim 12, it is characterised in that described manufacture method with
The rear end structure preparation technology of cmos circuit is mutually integrated；
Wherein, described first medium layer is metal interlamination medium layer, and described inverted cone shape the first electrode is
For connecting the metal via structure of interconnection line layer, described second electrode is of this interconnection line layer
Point.
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