CN102971848B - Resistive random access memory device and method - Google Patents

Resistive random access memory device and method Download PDF

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Publication number
CN102971848B
CN102971848B CN201180032458.XA CN201180032458A CN102971848B CN 102971848 B CN102971848 B CN 102971848B CN 201180032458 A CN201180032458 A CN 201180032458A CN 102971848 B CN102971848 B CN 102971848B
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hole
electrode
random access
access memory
metal
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CN102971848A (en
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约瑟夫·N·格里利
约翰·A·斯迈思
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/028—Formation of the switching material, e.g. layer deposition by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Abstract

A kind of method that the present invention comprises high density resistor formula random access memory RRAM device and makes high density RRAM device. A kind of method of the RRAM of formation device comprises to form and has the resistive element at metal-metallic oxide interface. Forming described resistive element is included in the first electrode top formation insulating materials and forms through hole in described insulating materials. Conformally fill described through hole and described metal material is planarized in described through hole with metal material. Optionally process a part for the described metal material in described through hole to form metal-metallic oxide interface in described through hole. Above described resistive element, form the second electrode.

Description

Resistive random access memory device and method
Technical field
The present invention generally relates to semiconductor memory system, method and system, and more particularly relate to resistance-type withMachine access memory (RRAM) device and method.
Background technology
Resistive element can be used as semiconductor switch or memory component (for example, the memory cell of storage arrangement) andOther application. Storage arrangement is the internal semiconductor integrated electric in being provided as computer or other electronic installation conventionallyRoad. There are many dissimilar memories, comprise random access memory (RAM), read-only storage (ROM), movingState random access memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), flash memory, resistance canTransition storage (for example, phase change random access memory devices (PCRAM)) and resistive random access memory (RRAM) etc.
In modern semiconductors application of installation, for example, by numerous packs (, in Semiconductor substrate) to single little districtTo form integrated circuit. Along with the size of integrated circuit reduces, must be by tightr to the assembly and the device that form described circuitBe positioned at together to defer to limited free space. Along with described industry makes every effort to active in the per unit area of larger densityAssembly, effectively and accurately forming and isolating between circuit unit becomes more important.
Answer the needs of high memory density, high reliability and low power consumption, the electricity by storage arrangement as broad rangeThe nonvolatile memory of son application. Nonvolatile memory can be used for personal computer, portable memory stick, solid-state drivingMoving device (SSD), personal digital assistant (PDA), digital camera, cellular phone, portable music player are (for example,MP3 player), in movie player and other electronic installation etc. Program code and system data (for example, basic input/Output system (BIOS)) be conventionally stored in non-volatile memory device.
Non-volatile resistance-type memory (for example, RRAM device) is stored data by the resistance variations that makes resistive element.RRAM device can be due to height in the case of the read/write cyclic durability restriction without charge storage type memorySeparation between resistance states (HRS) and low resistance state (LRS) and relative large resistance ratios and have and surpass other typeSome beneficial characteristics of storage arrangement, for example, low power consumption, high-speed and fabulous bit resolution.
Can reach predetermined lasting time and write data into selected RRAM device by apply predetermined voltage with predetermined polarity.Can use two types of handover operation RRAM devices: one pole or bipolar. One pole switching relates to use and has identical voltageThe length of polarity and short pulse are programmed and are wiped. Compare, bipolar switching is used short pulse, but programmes and wipe arteries and veinsPunching has opposite polarity.
Previously having adopted multiple variable-resistance material in memory cell method, comprise and utilize spinning moment characteristicSTT-RAM, the PCRAM that relates to the phase transformation of chalcogen compound, Ag ion tranmission techniques, NiO and copper ion are carriedMaterial. But previously the many technology in method and technology did not manifest good ratio adjustment. Patterning is to reduced sizeNot always possible, and along with memory cell dimensions reduces, in the etch-damaged phase that becomes forming in memory cellTo larger problem.
For the many previous method of implementing storage arrangement mainly by semi-conducting material for memory component, it is right to retainContact and conductor use metal. Relate to that the previous method of metal etch can be because of bad metal etch speed, high treatment temperatureUse and the use of additional energy source and being hindered. These methods due to bad etch uniformity, expensive, add establishStandby complexity and integrity problem and infeasible for the semiconductor batch of large substrate is processed. Use metal to realizeHindered the effort of making high density RRAM device compared with these and other difficulty in small-feature-size.
Summary of the invention
The method that the present invention comprises a kind of resistive random access memory (RRAM) device and makes RRAM device.A kind of method of the RRAM of formation device comprises to form and has the resistive element at metal-metallic oxide interface. Form instituteStating resistive element is included in the first electrode top formation insulating materials and forms through hole in described insulating materials. Use metalMaterial is conformally filled described through hole and described metal material is planarized in described through hole. Described metal filledly also can beOptionally or from bottom upwards. Optionally process a part for the described metal material in described through hole to lead to describedIn hole, form metal-metallic oxide interface. Above described resistive element, form the second electrode.
Brief description of the drawings
Fig. 1 illustrates according to the schematic cross-section of the RRAM device of one or more embodiment of the present inventionFigure.
Fig. 2 A and 2B illustrate forming in the single damascene process of use according to one or more embodiment of the present inventionThe cross-sectional view of the semiconductor structure during RRAM device.
Fig. 2 C illustrates forming in the single damascene process of use according to one or more embodiment of the present inventionThe plane of the semiconductor structure during RRAM device.
Fig. 3 A and 3B illustrate forming in the single damascene process of use according to one or more embodiment of the present inventionDuring RRAM device at the cross-sectional view of complanation semiconductor structure after bit line with isolation.
Fig. 4 A and 4B illustrate forming in use dual damascene process according to one or more embodiment of the present inventionThe cross-sectional view of the semiconductor structure during RRAM device.
Fig. 5 A and 5B illustrate forming in use dual damascene process according to one or more embodiment of the present inventionDuring RRAM device at the cross-sectional view of complanation semiconductor structure after bit line with isolation.
Fig. 6 is according to the perspective view of the crosspoint resistive memory array of one or more embodiment of the present invention.
Detailed description of the invention
In describing in detail below of the present invention, with reference to forming the appended graphic of a part of the present invention, and appended graphicIn with way of illustration show can how to put into practice one or more embodiment of the present invention. Fully describe this in detailOne or more embodiment with make those skilled in the art can put into practice of the present invention one or moreEmbodiment, and should be appreciated that, can utilize other embodiment and can in the situation that not deviating from scope of the present invention, make process,Electricity or mechanical alteration.
Fig. 1 illustrates according to the schematic cross section of RRAM device of the present invention. According to of the present invention one orMore than one embodiment, in Fig. 1, illustrated structure is to be embodied as below 40 nanometers of two-terminal RRAM deviceMetal oxide (MOx) unit. Described two-terminal RRAM device can be made by the technique that comprises the following: logicalThe conformal in hole is metal filled, the complanation (for example, CMP) of conductor (for example, line) isolation, selective oxidation (for example, withThe active area that formation comprises metal-metallic oxide interface) and top electrode pattern. Method of the present invention and structure compriseThrough making to there is the resistive element at TiN-TiON and Cu-CuOx interface. But embodiments of the invention are not limitIn this and can use other metal to make, as below further described. Describe according to RRAM of the present invention about Fig. 1The structure of device, and describe according to respective production method of the present invention about Fig. 2 to 5.
RRAM device 100 cross sections demonstrated in Figure 1 can comprise substrate 102, on substrate 102, are formed with oxidationThing material (for example, pad oxide) 104. Substrate 102 can be any physical material (example that can apply semiconductor device on itAs, silicon (Si)) or technique in the material that uses similarly. On oxide material 104, (for example, can form nitrideSilicon nitride (SiN)) material 106. In a part of SiN material 106, can form oxide material 108, andOn another part of SiN material 106, can form functional metal materials 110. Functional metal materials 110 can through implement withFor adhering to, stress is eliminated or other is applicable to functional (for example, burying digital line (BDL)) etc. At functional metal materialsOn 110, can form conductive metallic material 112 (for example, tungsten), wherein conductive metallic material 112 and functional metal materials110 form bottom electrode 113. In various embodiments, described bottom electrode also can be used as the word line of memory array.SiN district 111 can be between oxide material 108 and bottom electrode 113. Can on conductive metallic material 112Form resistive element 117, resistive element 117 comprises Part I 116 (contiguous conductive metallic material 112) and secondPart 118 (contiguous Part I 116).
According to one or more embodiment of the present invention, the Part I 116 of resistive element 117 can be by conductive goldBelong to material (for example, Cu, TiN) and form, and the Part II 118 of resistive element 117 can be by described conducting metal materialThe oxide (for example, CuOx, TiOxNy) of material forms. For instance, the Part I 116 of resistive element 117Can be formed and Part II can be formed by TiON by TiN. Or resistive element 117 can be through forming to have copper (Cu)Part I 116 and cupric oxide (CuOx) Part II 118. According to various embodiment, Part I 116 is by comprising goldMaterial (for example, metal, comprise the mixture as at least one metal of metal nitride or the metal silicide) shape belonging toBecome, and Part II 118 forms by metal oxide oxide, for instance, described in containing to form by oxidation packageThe material of the metal of Part I. Part I 116 can be by noble metal, palladium, platinum, ruthenium, metal nitride or its combinationForm, and the corresponding oxide of Part II 118 material that is described Part I. This clearly demarcated embodiment is not strictBe limited to previous materials, and conductive component can be by forming as other material that is suitable for its application. Real according to one or moreExecute example, resistive element for example, through forming to make Part I can be metal (, correspondence as metal oxide and Part IIMetal).
As demonstrated in Figure 1, can in the through hole 119 being for example formed at, in insulating materials 114 (, dielectric), form electricityResistive element 117, insulating materials 114 is formed on the conductive metallic material 112 of oxide material 108 and the first electrodeSide. As used herein, being formed at certain material " top " can comprise and be formed at least in part described material top.Insulating materials 114 can be formed by (for instance) SiN or oxide material. As can be seen in Figure 1, through hole 119 shapesBe formed in insulating materials 114 with make resistive element 117 will with electrode (for example, the conducting metal material of bottom electrode 113Material 112) contact.
Can by with metal material optionally filling vias form resistive element 117. Can use conformal metal filledFill the through hole 119 being formed in insulating materials 114. Metal filled (and the illustrated structure in Fig. 1 of conformalApplying of middle other shown metal material) can use atom material deposition (ALD), physical vapour deposition (PVD) (PVD), changeLearn vapour deposition (CVD), supercritical fluid deposition (SFD) or realize for other the applicable thin-film technique that applies metal.Useful damascene process applies and removes less desirable metal material, as below further discussed. According to some enforcementExample, available metal material is filling vias upwards from bottom.
According to one or more embodiment, RRAM device of the present invention can be made as to the device below 40 nanometers.So, through hole 119 can have the size that is less than 40 nanometers by the bracket instruction in Fig. 1 (for instance, it can be directlyFootpath). RRAM device below 40 nanometers can (for instance) be made to have an appointment and be less than 1/2nd to four points of device sizeOne of through hole. In various embodiments, RRAM device of the present invention can be made as and there is 20 of through hole 119 and receiveThe device that rice is following, through hole 119 has the size that is less than approximately 10 nanometers by the bracket instruction in Fig. 1. Real at otherExecute in example, RRAM device of the present invention can be made as to the device below 15 nanometers with through hole 119, through hole 119There is the size that is less than approximately 5 nanometers by the bracket instruction in Fig. 1. Resistive element Part I and Part II itBetween distribution can be by controlling in order to the technique of metal of filling through conformal being optionally oxidized in through hole 119. For example, through conformal fill metal can by be exposed to gas cluster ion beam (GCIB) or by through select logical to controlUnder the condition of the position at the metal-metallic oxide interface in hole, carry out plasma oxidation (for example, groove flat plane antenna (SPA)Plasma oxygen metallization processes) and be oxidized. According to various embodiment, just occurring at the temperature of remarkable thermal oxide of metal lower than it(for example,, under relative low temperature degree) realizes the metal material being optionally oxidized in through hole.
After being suitably oxidized conformal metal charge, can (in it, form in resistive element 117 and insulating materials 114The through hole 119 that contains resistive element 117) top formation top electrodes 121. Suppose to have the TiN of being formed with Part I116 and the RRAM device 100 of the resistive element 117 of TiON Part II 118, top electrodes 121 can soFormed by the TiN120 that is directly formed at resistive element 117 and insulating materials 114 tops. On TiN material 120Square one-tenth tungsten 122, TiN120 and tungsten 122 form the second electrode 121.
According to one or more embodiment of the present invention, through hole 119 can have at least one chi that is less than 40 nanometersVery little, and in certain embodiments, RRAM device can be the device below 20 nanometers or below 15 nanometers, wherein through hole119 have at least one size of 1/2nd of the size that is less than RRAM device. Forming resistive element 117When TiN Part I 116 and TiON Part II 118, use conformal metal filled. But, embodiments of the inventionBe not limited to relate to after metal filled to form the conformal of metal material at metal-metallic oxide interface through oxidation. According to extremelyA few embodiment, puts upside down bottom (for example, first) electrode 113 and top (for example, the from orientation demonstrated in Figure 1Two) orientation of electrode 121 and resistive element 117. , above substrate, form the second electrode. Can be then by heavyLong-pending metal (for example, TiN), be oxidized to form metal oxide (for example, TiON), follow-uply followed corresponding metal (exampleAs, TiN) another deposit to form resistive element. Can above described resistive element, form the first electrode. FirstConductive metallic material 112 parts of electrode and the TiN120 of the first electrode and the second electrode part are respectively through arranging with neighbourBe bordering on resistive element 117.
As described about ad hoc structure demonstrated in Figure 1, the resistive element of RRAM device can be by providing oneMaterial (for example, metal, metal oxide (MOx), transition metal oxide (TMO) and the metal nitrogen of above resistance statesCompound etc.) form. Described RRAM device can utilize resistor transition characteristic, by the electricity of described resistor transition characteristic materialRoot resistance changes according to the change applying of voltage and/or electric current.
Resistive element can have by semiconductive (for example,, nominally electric insulation) and be also a kind of or a kind of of weak ion conductorThe active region that above material forms. The material of described active region can trustship and the conveying ion that serves as adulterant withControl electronics flowing through described material. Also ion can be carried to lack (for example, the ion room) that is interpreted as specific ionConveying, electric current is understood in this movement in " the electric hole " that lack being similar to by representing electronics. , ion room is aobviousNow for move with the direction of the opposite direction of corresponding ion on edge. Ion or its room can be serves as in cation or anionThe ion of one.
According to the previous method of one, can be for example, by being deposited on certain initial characteristic (, the concentration in ion room) upper differentTwo kinds of dispersed materials form the active region of resistive element. The operation of resistive element can relate to ion room from firstPart is crossed over the conveying to the material of Part II of border between two parts of resistive element. Described active region because ofThis comprise (for instance) for delivery of and trustship serve as adulterant ion to control mobile main material and the use of electronicsIn the auxiliary material that ionic dopants source is provided for described main material.
In the multiple application that metal can be used for comprising semiconductor device applications. Some material character (for example, lower electricity of metalThe stress migration resistance of resistance rate, good electrical migration performance and increase) in semiconductor application, be desirable and soluble metal existsUse in interconnection line and contact. The material character of some metals (for example titanium (Ti) and copper (Cu)) provides and surpasses other metalThe advantage of (for example, aluminium (Al)). For instance, can allow signal quickly by reducing RC time delay compared with low resistanceMobile.
But, metal (for example, Cu) is incorporated in the multi-layer metallization framework of semiconductor device and can be used for metalThe special disposal method of patterning. Metal (for example, Cu) can be difficult to carry out dry-etching. Therefore, developed for metalThe process program of patterning, for example damascene process. The feature of method for embedding based in etching dielectric substance, fill out with metalFill described feature and pass through chemical-mechanical planarization (CMP) complanation top surface. Dual damascene scheme is by contact and interconnection lineBoth are integrated in single processing scheme.
Fig. 2 A and 2B illustrate forming in the single damascene process of use according to one or more embodiment of the present inventionThe cross-sectional view of the structure during RRAM device. Fig. 2 C illustrates according to one or more enforcements of the present inventionThe plane of the semiconductor structure during using single damascene process formation RRAM device of example. Fig. 2 A is illustrated in formationDuring RRAM device in Fig. 2 C indicated position along the cross-sectional view (Z of the semiconductor structure 230 of X-Z planeThe vertical axis of instruction in three-dimensional coordinate system), and Fig. 2 B is showed in position indicated in Fig. 2 C along Y-Z planeThe cross-sectional view of semiconductor structure 232. Notice that Fig. 2 C is not the horizontal section of RRAM device, this is because bit line is ledBody and word line conductor are all non-intersect in any common plane. But, Fig. 2 C with plane show bit line conductors 242,The orientation of word line conductor 234 and bit line dielectric 236 is with looking of being shown in each in while indicator diagram 2A and 2BThe position of figure and orientation.
Semiconductor structure 230 and 232 displayings are formed at word line conductor 234 and word line dielectric substance 238 (institute in Fig. 2 BShow) top bit line dielectric 236. Before realizing the configuration of showing in Fig. 2 A and 2B, patterning bit line electricityMedium 236 (for example, forming therein through hole) and conformally deposit therein resistance-type element stack material 240. Subsequently,The metal material 242 that deposition forms bit line conductors above resistance-type element stack material 240 is to realize Fig. 2 A and 2BMiddle structure 230 and 232 of showing respectively.
Fig. 3 A and 3B illustrate forming in the single damascene process of use according to one or more embodiment of the present inventionDuring RRAM device at the cross-sectional view of complanation semiconductor structure after bit line with isolation. Fig. 3 A is illustrated in formationDuring RRAM device for example, in (, indicated in Fig. 2 C with respect to the position and the orientation that intersect bit line conductors and word line conductorDescribed position and orientation) locate along the cross-sectional view of the semiconductor structure 330 of X-Z plane, and Fig. 3 B be showed in respect toIntersect the position of bit line conductors and word line conductor and orientation (for example, in Fig. 2 C indicated described position and orientation) and locate edgeThe cross-sectional view of the semiconductor structure 332 of Y-Z plane.
The assembly that semiconductor structure 330 and 332 comprises corresponding to the similar assembly of showing in Fig. 2 A and 2B, comprises:Bit line dielectric 336, it is formed at word line conductor 334 and word line dielectric substance 338 (showing in Fig. 3 B) top;Bit line dielectric 336; Resistance-type element stack material 340; And metal material 342, it is deposited on resistance-type element stackMaterial 340 tops. Structure 230 and 232 complanations (for example, passing through CMP) are to realize difference in Fig. 3 A and 3BThe structure 330 and 332 of showing. As gone out from Fig. 3 A and 3B observable, complanation has removed resistance-type element stack material340 and metal material 342 be deposited on the volume outside through hole. In this way, complanation is by metal bit line and resistance-type listUnit's stack material is isolated into and is contained in completely in the through hole being previously formed in bit line dielectric 336. Fig. 2 and 3 illustratesSingle damascene process situation.
Fig. 4 A and 4B illustrate forming in use dual damascene process according to one or more embodiment of the present inventionThe cross-sectional view of the semiconductor structure during RRAM device. Fig. 4 A be illustrated in form during RRAM device in respect toIntersect the position of bit line conductors and word line conductor and orientation (for example, in Fig. 2 C indicated described position and orientation) and locate edgeThe cross-sectional view of the semiconductor structure 460 of X-Z plane, and Fig. 4 B is showed in respect to crossing bit line conductors and word line and leadsThe position of body and orientation (for example, in Fig. 2 C indicated described position and orientation) are located along the semiconductor structure of Y-Z plane462 cross-sectional view.
Semiconductor structure 460 and 462 is similar to the structure 230 and 232 of showing in Fig. 2 A and 2B, and additional etching stopsOnly material 444. Semiconductor structure 460 and 462 comprises and is formed at word line conductor 434 and word line dielectric substance 438 (figureIn 4B, show) top bit line dielectric 436. Before realizing the configuration of showing in Fig. 4 A and 4B, deposition positionThe bottom part of line dielectric 436, above the part of the bottom of bit line dielectric 436, deposition etch stops material 444,Wherein above etch stop material 444, deposit the top part of bit line dielectric 436. Bit line dielectric 436 and etchingStop material 444 " interlayer " patterned with form therein through hole and remove bit line dielectric 436 at etch stopTop part in the select location of material 444 tops. In through hole and etch stop material 444 through expose portionTop conformally deposits resistance-type element stack material 440, subsequently deposited gold above resistance-type element stack material 440Belong to material 442 to realize the structure 460 and 462 of showing respectively in Fig. 4 A and 4B.
Fig. 5 A and 5B illustrate forming in use dual damascene process according to one or more embodiment of the present inventionDuring RRAM device at the cross-sectional view of complanation semiconductor structure after bit line with isolation. Fig. 5 A is illustrated in formationDuring RRAM device for example, in (, indicated in Fig. 2 C with respect to the position and the orientation that intersect bit line conductors and word line conductorDescribed position and orientation) locate along the cross-sectional view of the semiconductor structure 560 of X-Z plane, and Fig. 5 B be showed in respect toIntersect the position of bit line conductors and word line conductor and orientation (for example, in Fig. 2 C indicated described position and orientation) and locate edgeThe cross-sectional view of the semiconductor structure 562 of Y-Z plane.
The assembly that semiconductor structure 560 and 562 comprises corresponding to the similar assembly of showing in Fig. 4 A and 4B, comprises:Bit line dielectric 536, it has the middle etch being positioned at wherein and stops material 544, and bit line dielectric 536 is formed at wordLine conductor 534 and word line dielectric substance 538 (showing in Fig. 5 B) top; Bit line dielectric 536; Resistance-type unitStack material 540; And metal material 542, it is deposited on resistance-type element stack material 540 tops. Fig. 4 A and 4BMiddle shown structure 460 and 462 complanations (for example, passing through CMP) are shown respectively to realize in Fig. 5 A and 5BStructure 560 and 562. As gone out from Fig. 5 A and 5B observable, complanation has removed resistance-type element stack material 540And metal material 542 be deposited on the volume outside through hole. In this way, complanation is by metal bit line and resistance-type stack of cellsLaminate materials is isolated into and is contained in completely in the through hole being previously formed in bit line dielectric 536. Fig. 4 and 5 illustrate due toBit line dielectric 536 arrange (for example, bit line dielectric 536 with etch stop material 544 " interlayer ") institute through dividingThe dual damascene process situation causing.
The replacement scheme of the desired method for embedding of the present invention is for to carry out pattern etched to metal material. Pattern etched workSkill relates to: in deposit metallic material above substrate, use patterned hard mask or photic anti-above described metal materialErosion agent, use reactive ion etching (RIE) technique described metal material to be carried out to pattern etched and in patterned metalMaterial top deposit dielectric material. Metal is carried out to pattern etched and can there is the mosaic technology of surpassing, this be because ofFor the thin metal pattern of etching also then deposits on described metal pattern dielectric substance than obtaining barrier material and metalEasier with the little characterized openings in filling dielectric film fully.
Use gas (for example, chlorine) to carry out etching metal material (for example, Cu, Al). Be the chlorine that contains of admixture of gasBody comprises argon (Ar). For realizing anisotropic etching, by Cl2For example, with other chlorine-containing gas (, Cl2、HCl、BCl3、SiCl4、CHCl3、CCl4And combination) mix, this is because use separately Cl2Can cause isotropic etching. UseChlorine plasma carries out etching to metal material and by the energetic ion in plasma to metal material (for example, relates toCuClx) carry out physically splash plating. But there are several shortcomings in the method. For instance, by the etch-rate of the methodVery low and apply locular wall and this through jet-plating metallization material and need to carry out periodic purge to described chamber. With chlorine plasmaWhen etching high aspect ratio features, can run into another shortcoming and be deposited on again in feature side-wall through jet-plating metallization material product, in instituteThe effect of stating feature side-wall place physically splash plating reduces. In addition, implement described work when the temperature (200 degrees Celsius of >) raising is lowerSkill when increasing the volatibility of etched metal material, can occur due to the corruption due to the etch residues accumulating on surfaceErosion. The in the situation that cleaning step removing these residues after not by etching, even protective material is being put on through erosionAfter carving feature top, it also can cause the lasting corrosion of metal.
One for example, by gas (, chlorine) etching in order to the metal material of making resistive element 117 of the present invention is replacedBe metal material (for example,, with chemistry and/or mechanical system) described in complanation for scheme. For instance, can use CMPTo be planarized in through hole in order to the metal material that forms resistive element 117. , can chemistry and/or mechanical systemRemove the metal material extending to outside through hole. Similarly, can chemistry and/or mechanical system planarized semiconductor structure to moveExcept the metal material in through hole and some materials of forming through hole are to make metal material in through hole and the opening of through holeRoughly become plane. In the time adopting chemistry and/or mechanical planarization technology etc. to make RRAM device of the present invention, can useSingly inlay and dual damascene process method.
As mentioned above, be optionally oxidized resistive element (for example, demonstrated in Figure 1 117) and form secondPoints 118 and the metal-metal that therefore forms between Part I 116 and the Part II 118 of resistive element 117 be oxidizedThing interface 115. With the configuration of controlling resistance formula element whereby of abundant accuracy control selective oxidation processes, comprise electricityThe physics chi of the resistance ratios between resistance, at least two resistance states and each in Part I and Part IIVery little.
In one or more embodiment of the present invention, can make RRAM device, wherein resistive element 117Part I 116 and Part II 118 Limited Current (example fully can be provided provide in its low resistance stateAs, to realize desirable electricity usage level and/or be held in thermal limit) resistance. For instance, resistive elementA kind of resistance that provides at least 1000 ohm in its low resistance state that is configured in of 117. In addition, in various realities of the present inventionExecute in example, can form RRAM device, wherein the Part I of resistive element and Part II are configured to use and draw3 volts of programming pulses getting approximately 1 milliampere are less than-2 volts of erasing pulses of 1.5 milliamperes about 1000 resistance ratio are provided with drawingRate. , the switching between two resistance states can cause the resistance of approximately three orders of magnitude to change (for example,, from approximately 1,000 EuropeNurse arrives approximately 1,000,000 ohm). In certain embodiments, can form RRAM device, wherein first of resistive elementPart and Part II be configured to use draw approximately 0.1 milliampere 3 volts of programming pulses with draw be less than 0.3 milliampere-2Volt erasing pulse provides about 100 resistance ratios. , the switching between two resistance states under reduced-current valueCan cause the resistance of approximately two orders of magnitude to change (for example,, from approximately 1,000 ohm to approximately 100,000 ohm).
According to one or more embodiment, resistive element 117 can be formed in a through hole, described through hole have toSize (for example, the width of through hole and/or diameter) below few 40 nanometers. In certain embodiments, resistance-type unitThe part that part 117 can be used as RRAM device (for example, the device below 20 nanometers) is formed to have and is less than 10 nanometersThe through hole of at least one size in. In other embodiments, resistive element 117 (for example, can be used as RRAM deviceDevice below 15 nanometers) a part be formed in the through hole with at least one size that is less than 5 nanometers. Resistance-typeElement can completely be contained in through hole and form by occupying the whole volume of through hole or its certain part. , in some enforcementIn example, can make conformal metal deposit incomplete filling vias. The CMP of the metal material outside through hole removes and will cause metalMaterial is limited to through hole, but recessed a little from the surface around insulating materials. Still optionally oxidation is recessed into metal,As described previously. Form subsequently the second electrode (for example, TiN part), the second electrode material will extend in through hole withContact with recessed resistive element.
In other embodiments, resistive element is through forming to extend to outside through hole. For instance, Part I and secondAt least one in part may extend into the outer distance in from approximately 10 dusts to the scope of approximately 50 dusts of through hole. As hereinInstitute use, the size in the scope from about first size to the approximately second size mean some embodiments of the present invention betweenIn scope from described first size to described the second size (except other extra embodiment). Equally, can select subsequentlyThe metal material of property ground oxidation resistive element and form the second electrode above at least described resistive element. The second electrodeTiN material will conformally be deposited on the extending to around the Part II outside through hole of resistive element.
The selective oxidation processes of controlling the metal of conformal deposit in through hole is determined and is formed respectively first of resistive elementThe distribution of the through hole volume of part and Part II. According to some embodiment, control selective oxidation to make resistance-type unitThe Part II of part occupy be less than through hole volume 40 (40%) approximately percent. In certain embodiments, control and selectProperty is oxidized that Part II is occupied and is less than 25 (25 approximately percent of distance between the first electrode and the second electrode%). As used herein, the percentage that is set fourth as approximately given percentage means some embodiments of the present invention and is configured toThere is the characteristic (except other extra embodiment) of described given percentage.
In various embodiments, the Part II of resistive element (for example, TiON) has edge at the first electrode and the second electricityThe degree of depth in from approximately 10 dusts to the scope of approximately 100 dusts of the size of the through hole extending between the utmost point. At some embodimentIn, the Part II (for example, TiON) of resistive element has along the through hole extending between the first electrode and the second electrodeThe degree of depth in from approximately 20 dusts to the scope of approximately 80 dusts of size.
According to one or more embodiment of the present invention, the RRAM device of making as described above can be used as depositingThe memory cell of reservoir array, described RRAM Plant arrangement becomes cross-point arrangement. In addition so storage of structure,Device array can be incorporated in various electronic memories, calculation element and other equipment and computing system.
Fig. 6 is according to the perspective view of the crosspoint resistive memory array of one or more embodiment of the present invention.Crosspoint resistive memory array 670 can comprise multiple bottoms (, first) electrode 676 and multiple top (, second)Electrode 676. Bottom electrode 676 can be through layout and along first direction parallel to each other and the second electrode 676 can be through layout and edgeSecond direction is parallel to each other. Described first direction and described second direction can (but needn't) be perpendicular to one another. But, first partyTo and second direction can through orientation with make bottom electrode and top electrodes intersected with each other with set up multiple joinings (for example, hand overCrunode), can between described joining, form resistive element 674.
Top electrodes 676 is similar to top electrodes demonstrated in Figure 1 121, and can be as previously for top electrodes 121With with describing make. Bottom electrode 676 is similar to bottom electrode demonstrated in Figure 1 113, and can be as previously the end of forPortion's electrode 113 with describing make. Resistive element 674 is similar to resistive element demonstrated in Figure 1 117, andCan be as previously described and made to comprise metal part and metal oxide part for resistive element 117. Come for exampleSay, crosspoint resistive memory array 670 can comprise multiple memory cells, and each memory cell is as about figure1 with describing make RRAM device. Can put upside down bottom (, first) electrode 676, top (, second) electrode676 and position and/or the layout of resistive element, the putting upside down of the metal that comprises resistive element and metal oxide part,As described previously.
Can by change voluntarily system (for example, computer-controlled semiconductor fabrication equipment) make structure as described above,Circuit and device. For instance, on nonvolatile computer-readable media, can store and can carry out to cause dress by processorStandby or device is carried out the instruction of the preparation method stated herein. Except other action, described instruction also can cause halfConductor making apparatus carries out following operation: above substrate, depositing the first electrode, above at least described the first electrode, depositingInsulating materials, in described insulating materials, form through hole, at least in described through hole the metallic compliant material of deposition bag,The institute that comprises in described through hole is isolated in described through hole, optionally processed to the described compliant material that comprises described metalThe described material of stating metal with oxidation package containing a part for the described material of described metal and comprise described metal described inDeposition second electrode above oxidized portion of material.
Describe the device, the method and system that are used to form RRAM device herein, and in particular, described shapeOne-tenth can operate the metal material place at the metal-metallic oxide interface to switch between two or more resistance statesReason. Although illustrated and described specific embodiment herein, be understood by those skilled in the art that, through meterCalculate to realize the alternative specific embodiment of being shown of layout of identical result. The present invention intends to contain one of the present inventionOr change or the variation of more than one embodiment. Should be understood that non-limiting mode is made above theory with illustrative approachBright. After checking above explanation, it will be apparent to those skilled in the art that the combination of above embodiment and tool not hereinOther embodiment of volume description. The scope of one or more embodiment of the present invention comprise wherein use above structure andOther application of method. Therefore, the scope of one or more embodiment of the present invention should be with reference to appended claimsFour corner together with the equivalent of authorizing these a little claims is determined.
In aforementioned embodiments, for simplifying object of the present invention, various features are combined in single embodiment together.The method of the present invention should not be construed as of the present invention the disclosed embodiment of reflection and must use than being clearly set forth in each powerThe intention of more feature during profit requires. But, as above claims reflect: invention subject matter is to be less than listAll features of individual disclosed embodiment. Therefore, hereby above claims are incorporated in embodiment, wherein everyOne claim is independently as independent embodiment.

Claims (26)

1. a method that forms resistive random access memory RRAM device (100), it comprises:
Form the first oxide material (104) in substrate (102) top;
Form nitride material (106) in described the first oxide material (104) top;
Part top at described nitride material (106) forms the second oxide material (108);
A different piece top at described nitride material (106) forms the first electrode (113,676);
Form resistive element (117,674) in described the first electrode (113,676) top, wherein form described resistance-type unitPart (117,674) comprises:
Form insulating materials at described the second oxide material (108) and described the first electrode (113,676) top(114)；
In the described insulating materials (114) of described the first electrode (113,676) top, form through hole (119);
Conformally fill described through hole (119) with metal material;
Described metal material is planarized in described through hole (119); And
A part (116) of optionally processing the described metal material in described through hole (119) is with at described through hole(119) in, form metal-metallic oxide interface (115); And
Form the second electrode (121,672) in described resistive element (117,674) and described insulating materials (114) top.
2. form according to claim 1 the method for resistive random access memory RRAM device (100), whereinThe described part (116) of optionally processing the described metal material in described through hole (119) comprises: optionally described in oxidationThe described part (116) of metal material.
3. form according to claim 2 the method for resistive random access memory RRAM device (100), whereinAt the temperature that remarkable thermal oxide just occurs lower than it, realize and to be optionally oxidized described metal material in described through holeDescribed part (116).
4. form according to claim 3 the method for resistive random access memory RRAM device (100), whereinThe described part (116) that is optionally oxidized the described metal material in described through hole (119) comprises: plasma oxidation.
5. form according to claim 2 the method for resistive random access memory RRAM device (100), whereinThe described part (116) that is optionally oxidized the described metal material in described through hole (119) comprises: groove flat plane antenna SPAPlasma oxygen metallization processes.
6. according to forming resistive random access memory RRAM dress described in arbitrary claim in claim 1 to 5Put the method for (100), wherein optionally process described part (116) bag of the described metal material in described through hole (119)Contain: the described part (116) of the described metal material in described through hole (119) is optionally exposed to gas cluster ion beamGCIB。
7. according to forming resistive random access memory RRAM dress described in arbitrary claim in claim 1 to 5Put the method for (100), wherein conformally fill described through hole (119) with metal material and comprise: conformally fill institute with TiNState through hole (119).
8. form according to claim 7 the method for resistive random access memory RRAM device (100), whereinThe described part (116) of optionally processing the described metal material in described through hole (119) forms in described through hole (119)TiN-TiON interface (115).
9. according to forming resistive random access memory RRAM dress described in arbitrary claim in claim 1 to 5Put the method for (100), wherein conformally fill described through hole (119) with metal material and comprise: conformally fill described logical with copperHole (119).
10. form according to claim 9 the method for resistive random access memory RRAM device (100), itsIn optionally process the described metal material in described through hole (119) described part (116) form Cu-CuOx interface(115)。
11. according to forming resistive random access memory RRAM dress described in arbitrary claim in claim 1 to 5Put the method for (100), wherein realize with described metal material conformal with the supercritical fluid deposition SFD of metal materialDescribed through hole (119) is filled on ground.
12. 1 kinds of resistive random access memory RRAM devices (100), it comprises:
The first oxide material (104);
Nitride material (106), it is formed on the top of described the first oxide material (104);
The second oxide material (108), it is formed on the top of a part for described nitride material (106);
The first electrode (113,676), it is formed on the top of another part of described nitride material (106);
Insulating materials (114), it is formed on the upper of described the second oxide material (108) and described the first electrode (113,676)Side;
The second electrode (121,672); And
Resistive element (117,674), it is contained in the through hole (119) being formed in described insulating materials (114), described logicalExtend between described the first electrode (113,676) and described the second electrode (121,672) in hole (119), described resistance-type unitPart (117,674) comprises Part I (116) and Part II (118), and described Part I (116) is the metallic material of bagAnd what described Part II (118) was the described material that comprises described metal passes through to be optionally oxidized in described through hole (119)The oxide that forms of the described material that comprises described metal, to form metal-metallic oxide interface in a position(115), described metal-metallic oxide interface (115) make the described resistive element (117,674) can be two or moreBetween resistance states, switch, in described resistance states, described resistive element (117,674) has and differs each other at leastThe resistance value of two orders of magnitude,
Wherein, described the second electrode (121,672) is formed on described resistive element (117,674) and described insulating materials (114)Top.
13. according to the RRAM device (100) of resistive random access memory described in claim 12, and wherein saidA part (116) is selected from noble metal.
14. resistive random access memory RRAM devices according to claim 13 (100), described noble metalFor palladium, platinum or ruthenium.
15. according to the RRAM device (100) of resistive random access memory described in claim 12, and wherein saidA part (116) is that Cu and described Part II (118) are CuOx.
16. according to the RRAM device (100) of resistive random access memory described in claim 12, and wherein saidA part (116) is that TiN and described Part II (118) are TiON.
17. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 12 to 16Put (100), the described Part I (116) of wherein said resistive element (117,674) and described Part II (118) are through joiningPut to use and draw 3 volts of programming pulses of 1 milliampere and be less than-2 volts of erasing pulses of 1.5 milliamperes 1000 electricity is provided with drawingResistance ratio.
18. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 12 to 16Put (100), the described Part I (116) of wherein said resistive element (117,674) and described Part II (118) are through joiningPut to use and draw 3 volts of programming pulses of 0.01 milliampere and be less than-2 volts of erasing pulses of 0.03 milliampere and provide 100 with drawingResistance ratios.
19. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 12 to 16Put (100), wherein said Part II (118) be less than described through hole (119) volume 40 (40%) percent.
20. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 12 to 16Put (100), wherein said the first electrode (113,676) comprises and is deposited on the tungsten material (112) of burying digital line (110) top,Described the first electrode (113,676) is through arranging to make described tungsten material (112) and described resistive element (117,674)Described Part I (116) contact.
21. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 12 to 16Put (100), the tungsten of the volume that wherein said the second electrode (121,672) comprises TiN (122) top that is deposited on a volume(120), described the second electrode (121,672) is through arranging to make described TiN (122) and described resistive element (117,674)Described Part II (118) contact.
22. 1 kinds of resistive random access memory RRAM devices (100), it comprises:
The first oxide material (104);
Nitride material (106), it is formed on the top of described the first oxide material (104);
The second oxide material (108), it is formed on the top of a part for described nitride material (106);
The first electrode (113,676), it is formed on the top of another part of described nitride material (106);
Insulating materials (114), it is formed on the upper of described the second oxide material (108) and described the first electrode (113,676)Side;
The second electrode (121,672), has through hole (119) in described insulating materials (114), described through hole (119) is describedBetween one electrode (113,676) and described the second electrode (121,672), extend; And
Resistive element (117,674), it is formed at least described through hole (119) and comprises Part I (116) and secondPartly (118), described Part I (116) is the material that comprises metal material, described Part II (118) is for described in comprisingThe described material that comprises described metal that passes through to be optionally oxidized in described through hole (119) of the described material of metal formsOxide, with one position form metal-metallic oxide interface (115), described metal-metallic oxide interface (115)Described resistive element (117,674) can be switched between two or more resistance states, at described resistance statesIn, described resistive element (117,674) has the resistance value that differs each other at least two orders of magnitude,
Wherein, described the second electrode (121,672) is formed on described resistive element (117,674) and described insulating materials (114)Top.
23. according to the RRAM device (100) of resistive random access memory described in claim 22, wherein said electricityDescribed Part I (116) and the described Part II (118) of resistive element (117,674) are configured to make it not occupyThe whole volume of described through hole (119), in wherein said the first electrode (113,676) and described the second electrode (121,672)At least one extend in described through hole (119) and contact with described resistive element (117,674).
24. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 22 to 23Put (100), the described Part I (116) of wherein said resistive element (117,674) and described Part II (118) are through joiningPut to make it to occupy at least whole volume of described through hole (119), wherein said Part I (116) and described Part II(118) at least one in extend to described through hole (119) outer and with described the first electrode (113,676) or described the second electrodeOne contact in (121,672).
25. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 22 to 23Put (100), wherein said resistive element (117,674) is through arranging to make described Part II (118) in described through hole (119)Be formed at described Part I (116) top.
26. dresses of the RRAM according to resistive random access memory described in arbitrary claim in claim 22 to 23Put (100), wherein said resistive element (117,674) is through arranging to make described Part I (116) in described through hole (119)Be formed at described Part II (118) top.
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Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8269203B2 (en) 2009-07-02 2012-09-18 Actel Corporation Resistive RAM devices for programmable logic devices
US8223539B2 (en) 2010-01-26 2012-07-17 Micron Technology, Inc. GCIB-treated resistive device
US8241944B2 (en) * 2010-07-02 2012-08-14 Micron Technology, Inc. Resistive RAM devices and methods
WO2013125421A1 (en) * 2012-02-21 2013-08-29 株式会社村田製作所 Resistance switching device and method for manufacturing same
US9112138B2 (en) 2012-06-14 2015-08-18 Micron Technology, Inc. Methods of forming resistive memory elements
US9337210B2 (en) 2013-08-12 2016-05-10 Micron Technology, Inc. Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors
US9112148B2 (en) 2013-09-30 2015-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM cell structure with laterally offset BEVA/TEVA
KR102114202B1 (en) 2013-11-25 2020-05-26 삼성전자주식회사 Non volatile memory device and method of forming the same
US9331088B2 (en) * 2014-03-25 2016-05-03 Sandisk 3D Llc Transistor device with gate bottom isolation and method of making thereof
US9178144B1 (en) 2014-04-14 2015-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM cell with bottom electrode
US9263577B2 (en) 2014-04-24 2016-02-16 Micron Technology, Inc. Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors
US9472560B2 (en) 2014-06-16 2016-10-18 Micron Technology, Inc. Memory cell and an array of memory cells
US9159829B1 (en) 2014-10-07 2015-10-13 Micron Technology, Inc. Recessed transistors containing ferroelectric material
US9209392B1 (en) 2014-10-14 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM cell with bottom electrode
US9305929B1 (en) 2015-02-17 2016-04-05 Micron Technology, Inc. Memory cells
US9853211B2 (en) 2015-07-24 2017-12-26 Micron Technology, Inc. Array of cross point memory cells individually comprising a select device and a programmable device
US10134982B2 (en) 2015-07-24 2018-11-20 Micron Technology, Inc. Array of cross point memory cells
US10270451B2 (en) 2015-12-17 2019-04-23 Microsemi SoC Corporation Low leakage ReRAM FPGA configuration cell
US9990993B2 (en) 2016-09-29 2018-06-05 Microsemi SoC Corporation Three-transistor resistive random access memory cells
US10147485B2 (en) 2016-09-29 2018-12-04 Microsemi Soc Corp. Circuits and methods for preventing over-programming of ReRAM-based memory cells
US9704573B1 (en) 2016-09-30 2017-07-11 Microsemi SoC Corporation Three-transistor resistive random access memory cells
WO2018106450A1 (en) 2016-12-09 2018-06-14 Microsemi Soc Corp. Resistive random access memory cell
US10396145B2 (en) 2017-01-12 2019-08-27 Micron Technology, Inc. Memory cells comprising ferroelectric material and including current leakage paths having different total resistances
CN111033624B (en) 2017-08-11 2023-10-03 美高森美SoC公司 Circuit and method for programming a resistive random access memory device
CN111418078B (en) * 2017-09-29 2024-03-05 昕原半导体(上海)有限公司 Resistive random access memory and fabrication technique
JP2019161106A (en) * 2018-03-15 2019-09-19 東芝メモリ株式会社 Method for manufacturing semiconductor storage device
US10446746B1 (en) 2018-05-01 2019-10-15 International Business Machines Corporation ReRAM structure formed by a single process
US10559625B1 (en) * 2018-08-08 2020-02-11 International Business Machines Corporation RRAM cells in crossbar array architecture
US10553789B1 (en) 2018-10-29 2020-02-04 International Business Machines Corporation Fully aligned semiconductor device with a skip-level via
US11170834B2 (en) 2019-07-10 2021-11-09 Micron Technology, Inc. Memory cells and methods of forming a capacitor including current leakage paths having different total resistances
TWI754175B (en) * 2019-10-03 2022-02-01 華邦電子股份有限公司 Method for ripening resistive random access memory
US11737289B2 (en) 2020-12-09 2023-08-22 International Business Machines Corporation High density ReRAM integration with interconnect
US11812675B2 (en) 2021-09-21 2023-11-07 International Business Machines Corporation Filament confinement in resistive random access memory
US11856878B2 (en) 2021-11-06 2023-12-26 International Business Machines Corporation High-density resistive random-access memory array with self-aligned bottom electrode contact

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3219909B2 (en) * 1993-07-09 2001-10-15 株式会社東芝 Method for manufacturing semiconductor device
US7405158B2 (en) * 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
KR100829556B1 (en) * 2002-05-29 2008-05-14 삼성전자주식회사 Magneto-resistive Random access memory and method for manufacturing the same
US7018917B2 (en) * 2003-11-20 2006-03-28 Asm International N.V. Multilayer metallization
KR100645064B1 (en) 2005-05-23 2006-11-10 삼성전자주식회사 Metal oxide resistive ram and manufacturing method thereof
JP4843259B2 (en) 2005-06-10 2011-12-21 シャープ株式会社 Method for manufacturing variable resistance element
WO2007013174A1 (en) 2005-07-29 2007-02-01 Fujitsu Limited Resistance storage element and nonvolatile semiconductor storage device
US7834338B2 (en) * 2005-11-23 2010-11-16 Sandisk 3D Llc Memory cell comprising nickel-cobalt oxide switching element
JP4017650B2 (en) * 2005-12-02 2007-12-05 シャープ株式会社 Variable resistance element and manufacturing method thereof
JP3989506B2 (en) * 2005-12-27 2007-10-10 シャープ株式会社 Variable resistance element, manufacturing method thereof, and semiconductor memory device including the same
US20070202677A1 (en) 2006-02-27 2007-08-30 Micron Technology, Inc. Contact formation
US20070218665A1 (en) 2006-03-15 2007-09-20 Marvell International Ltd. Cross-point memory array
JP5263856B2 (en) 2006-07-26 2013-08-14 独立行政法人産業技術総合研究所 Switching element and manufacturing method thereof
US7935242B2 (en) 2006-08-21 2011-05-03 Micron Technology, Inc. Method of selectively removing conductive material
JP4344372B2 (en) * 2006-08-22 2009-10-14 シャープ株式会社 Semiconductor memory device and driving method thereof
US8143661B2 (en) * 2006-10-10 2012-03-27 Spansion Llc Memory cell system with charge trap
WO2008075412A1 (en) * 2006-12-19 2008-06-26 Fujitsu Limited Resistance change device and process for producing the same
US7521358B2 (en) * 2006-12-26 2009-04-21 Lam Research Corporation Process integration scheme to lower overall dielectric constant in BEoL interconnect structures
US7667220B2 (en) 2007-01-19 2010-02-23 Macronix International Co., Ltd. Multilevel-cell memory structures employing multi-memory with tungsten oxides and manufacturing method
JP5152173B2 (en) 2007-03-01 2013-02-27 富士通株式会社 Semiconductor device and manufacturing method thereof
US7800094B2 (en) * 2007-06-11 2010-09-21 Macronix International Co., Ltd. Resistance memory with tungsten compound and manufacturing
US20090095985A1 (en) 2007-10-10 2009-04-16 Samsung Electronics Co., Ltd. Multi-layer electrode, cross point memory array and method of manufacturing the same
US8445913B2 (en) 2007-10-30 2013-05-21 Spansion Llc Metal-insulator-metal (MIM) device and method of formation thereof
KR100929730B1 (en) 2007-12-27 2009-12-03 주식회사 동부하이텍 Nonvolatile Memory Cell Manufacturing Method
US7791057B2 (en) * 2008-04-22 2010-09-07 Macronix International Co., Ltd. Memory cell having a buried phase change region and method for fabricating the same
US8134865B2 (en) * 2008-05-06 2012-03-13 Macronix International Co., Ltd. Operating method of electrical pulse voltage for RRAM application
KR20090126530A (en) * 2008-06-04 2009-12-09 삼성전자주식회사 Resistance random access memory
US20100051896A1 (en) 2008-09-02 2010-03-04 Samsung Electronics Co., Ltd. Variable resistance memory device using a channel-shaped variable resistance pattern
US20100051577A1 (en) 2008-09-03 2010-03-04 Micron Technology, Inc. Copper layer processing
US8072793B2 (en) 2008-09-04 2011-12-06 Macronix International Co., Ltd. High density resistance based semiconductor device
US8313661B2 (en) * 2009-11-09 2012-11-20 Tokyo Electron Limited Deep trench liner removal process
US8223539B2 (en) 2010-01-26 2012-07-17 Micron Technology, Inc. GCIB-treated resistive device
US8241944B2 (en) * 2010-07-02 2012-08-14 Micron Technology, Inc. Resistive RAM devices and methods

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US9419219B2 (en) 2016-08-16
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US20140319446A1 (en) 2014-10-30
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