KR101297088B1 - 3-dimensional non-volatile memory device and method of fabricating the same - Google Patents

Abstract

Embodiments of the present invention relate to a three-dimensional nonvolatile memory device and a manufacturing method thereof. A nonvolatile memory device according to an embodiment includes: a plurality of wiring stacks including a plurality of conductive lines stacked in a vertical direction on a substrate and spaced apart from each other; An information recording film formed on sidewalls of the wiring stacks and electrically connected to the plurality of conductive lines; A non-volatile that extends across the plurality of conductive lines while sandwiching the information recording film between the plurality of conductive lines and includes at least a portion of the information recording film in regions intersecting the plurality of conductive lines. Channel films in which memory cells are defined; And a gate insulating film in contact with the channel films, and a gate electrode formed on the gate insulating film to control electrical conductivity of each channel film, thereby controlling electrical connection between the nonvolatile memory cells and the respective channel films. It may include control gate structures.

Description

3-dimensional non-volatile memory device and method of manufacturing the same {3-dimensional non-volatile memory device and method of fabricating the same}

The present invention relates to a three-dimensional nonvolatile memory technology, and more particularly, to a nonvolatile memory device and a manufacturing method thereof.

In recent years, the demand for portable digital applications such as digital cameras, MP3 players, personal digital assistants (PDAs), and cellular phones is increasing, and the nonvolatile memory market is rapidly expanding. As the flash memory device, which is a programmable nonvolatile memory, has reached the limit of scaling, a nonvolatile memory device using a material film that can be reversibly converted into a nonvolatile memory that can replace it has attracted attention.

In general, the degree of integration of a semiconductor memory device is an important factor in determining the price of a product. Accordingly, there is a growing demand for improving the degree of integration of semiconductor memory devices. In general, the degree of integration of a semiconductor memory device is largely determined by the planar area occupied by a unit memory cell, and thus is greatly influenced by the level of fine pattern formation technology. However, as a high level of miniaturization technology is required, the degree of integration is gradually reaching its limit due to the difficulty of semiconductor manufacturing equipment and / or semiconductor manufacturing process.

In order to overcome this limitation, a semiconductor memory device having a three-dimensional structure has recently been proposed. However, problems such as process instability and / or reliability of a product due to the new structure have been generated, and studies for solving these problems have been conducted.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a three-dimensional nonvolatile memory device having a simple structure and capable of high integration in response to a demand for continuous high integration.

Another object of the present invention is to provide a manufacturing method capable of easily and reliably manufacturing a three-dimensional nonvolatile memory device having the aforementioned advantages.

According to an aspect of the present invention, there is provided a nonvolatile memory device including: a plurality of conductive stacks stacked in a vertical direction on a substrate, the wiring stacks being spaced apart from each other; An information recording film formed on sidewalls of the wiring stacks and electrically connected to the plurality of conductive lines; A non-volatile that extends across the plurality of conductive lines while sandwiching the information recording film between the plurality of conductive lines and includes at least a portion of the information recording film in regions intersecting the plurality of conductive lines. Channel films in which memory cells are defined; And a gate insulating film in contact with the channel films, and a gate electrode formed on the gate insulating film to control electrical conductivity of each channel film, thereby controlling electrical connection between the nonvolatile memory cells and the respective channel films. It may include control gate structures.

The information recording film may include first and second information recording films disposed on sidewalls of the wiring stacks adjacent to each other and opposing each other. In this case, the channel films extend across the plurality of conductive lines while sandwiching the plurality of conductive lines of the neighboring wiring stacks and the first and second information recording films, respectively, and the plurality of conductive lines. First and second channel films defining nonvolatile memory cells including at least a portion of the first and second information recording films in intersecting regions, wherein the control gate structure comprises the first and second channel films; The first and second channel layers may be disposed in contact with each other to have a common control gate structure.

The information recording film may include a phase change material, a variable resistive material, a programmable metallizing cell (PMC) material, a magnetic material, or a combination thereof. The plurality of conductive lines may operate as one of a word line and a bit line, respectively, and the channel layer may operate as the other of the word line and the bit line.

The wiring stacks may further include interlayer insulating layer patterns for electrically separating the plurality of conductive lines, and the plurality of conductive lines may be recessed from side surfaces of the interlayer insulating layer patterns.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including alternately repeatedly stacking first insulating layers and first conductive layers on a substrate; Continuously patterning the stacked first insulating layers and the first conductive layers to form wiring stacks including a plurality of conductive lines and interlayer insulating layer patterns therebetween and spaced apart from each other; Forming an information recording film on a surface including opposite sidewalls of said wiring stacks; A non-volatile that extends across the plurality of conductive lines while sandwiching the information recording film between the plurality of conductive lines and includes at least a portion of the information recording film in regions intersecting the plurality of conductive lines. Forming channel films in which memory cells are defined; And a gate insulating film in contact with the channel films, and a gate electrode formed on the gate insulating film to control electrical conductivity of each channel film, thereby controlling electrical connection between the nonvolatile memory cells and the respective channel films. Forming control gate structures.

In some embodiments, forming the information recording film includes conformally forming an information recording material layer on the wiring stacks; Forming a second insulating film filling the trenches between the wiring stacks; And planarizing the second insulating layer until the surfaces of the wiring stacks are exposed.

The forming of the channel films may include forming a first through hole contacting the information recording film to penetrate the second insulating film in a vertical direction; And filling the first through hole with a semiconductor material. In this case, the forming of the control gate structures may include forming a second through hole contacting the channel layers to penetrate the second insulating layer in a vertical direction; Forming the gate insulating layer in contact with the channel layer in the second through hole; And forming the gate electrode to contact the gate insulating layer in the second through hole.

In another embodiment, the forming of the control gate structures may include forming a second through hole penetrating the second insulating film between the wiring stacks in a vertical direction; The method may include forming the gate electrode surrounded by the gate insulating layer and the gate insulating layer in the second through hole. In this case, the forming of the channel films may include forming a first through hole penetrating the second insulating film in a vertical direction so as to contact the information recording film and the gate insulating film; And filling the first through hole with a semiconductor material.

According to a nonvolatile memory device according to an embodiment of the present invention, a diode is formed in three-dimensionally arranged nonvolatile memory cells by a signal line such as a bit line by a channel film and a control gate electrode for controlling its electrical conductivity. Since it is possible to prevent crosstalk between adjacent memory cells without combining a rectifying device such as the above, a highly integrated three-dimensional nonvolatile memory device can be provided.

In addition, according to the manufacturing method of the nonvolatile memory device according to the embodiment of the present invention, the nonvolatile memory device can be manufactured easily and reliably due to the advantages of the aforementioned nonvolatile memory device.

1A and 1B are perspective views schematically illustrating a cell array of three-dimensional nonvolatile memory devices according to embodiments of the present invention.
2 is a circuit diagram of a three-dimensional nonvolatile memory device according to an embodiment of the present invention.
3A and 3B are cross-sectional views showing the structure of an information recording film of a memory cell according to various embodiments of the present invention.
4A to 4L are perspective views sequentially illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.
5 is a block diagram illustrating an example of an electronic system including a nonvolatile memory device according to example embodiments.
FIG. 6 is a block diagram illustrating an example of a memory card including a 3D nonvolatile memory device according to example embodiments. FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings like reference numerals refer to like elements. In addition, as used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the scope of the invention. In addition, although described in the singular in this specification, a plural form may be included unless the singular is clearly indicated in the context. Also, as used herein, the terms "comprise" and / or "comprising" specify the shapes, numbers, steps, actions, members, elements and / or presence of these groups mentioned. It does not exclude the presence or addition of other shapes, numbers, operations, members, elements and / or groups.

Reference herein to a layer formed “on” a substrate or other layer refers to a layer formed directly on or above the substrate or other layer, or formed on an intermediate layer or intermediate layers formed on the substrate or other layer. It may also refer to a layer. It will also be appreciated by those skilled in the art that structures or shapes that are "adjacent" to other features may have portions that overlap or are disposed below the adjacent features.

As used herein, the terms "below," "above," "upper," "lower," "horizontal," or " May be used to describe the relationship of one constituent member, layer or regions with other constituent members, layers or regions, as shown in the Figures. It is to be understood that these terms encompass not only the directions indicated in the drawings, but also other directions of the device.

In the following, embodiments of the present invention will be described with reference to cross-sectional views schematically showing ideal embodiments (and intermediate structures) of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein. In addition, reference numerals of members in the drawings refer to the same members throughout the drawings.

1A and 1B are perspective views schematically illustrating a cell array of three-dimensional nonvolatile memory devices 100A and 100B according to embodiments of the present invention, and FIG. 2 is a three-dimensional view according to an embodiment of the present invention. A circuit diagram of a nonvolatile memory device.

Referring to FIG. 1A, the nonvolatile memory device 100A includes a plurality of conductive lines WL1 and WL2 stacked on a substrate 10 in a vertical direction, for example, a z direction. As illustrated in FIG. 1A, the plurality of conductive lines WL1 and WL2 may be conductive patterns extending in a first direction (eg, x direction) parallel to the main surface of the substrate 10. The plurality of conductive lines WL1 and WL2 are spaced apart from each other in parallel with each other in a second direction (eg, y direction) and a third direction (eg, z direction) different from the x direction. ) Can be arranged in three dimensions.

Electrical separation between the plurality of conductive lines WL1 and WL2 may be achieved by the interlayer insulating layer patterns 20P1, 20P2, and 20P3 disposed therebetween. The stacked structure in the z direction of the plurality of conductive lines WL1 and WL2 and the interlayer insulating layer patterns 20P1, 20P2, and 20P3 defines a plurality of wiring stacks ST on the substrate 10, and a plurality of wirings. The stacks ST may be spaced two-dimensionally at regular intervals in the y direction.

In the illustrated three-dimensional array structure of the plurality of conductive lines WL1 and WL2, the plurality of conductive lines WL1 and WL2 are repeatedly arranged four times in the y direction, but this is an exemplary example of the nonvolatile memory device. It may be repeated 2 or 5 times or more depending on the capacity. In addition, although the plurality of conductive lines WL1 and WL2 are repeatedly arranged twice in the z direction, this is exemplary and may be repeatedly arranged more than three times.

In the illustrated embodiment, the plurality of conductive lines WL1 and WL2 have a solid shape, but are limited thereto and may have, for example, a hollow pipe shape. In addition, the surfaces of the plurality of conductive lines WL1 and WL2 may have a three-dimensional pattern such as a groove to locally define a programming area of the nonvolatile information recording film SL, which will be described later. It will be described later with reference.

The nonvolatile memory device 100 may include a data storage layer SL formed on sidewalls of the wire stacks ST and electrically connected to the plurality of conductive lines WL1 and WL2. . The information recording film SL is disposed on both sidewalls of the wiring stacks ST, as shown in FIG. 1A, so that the plurality of conductive lines WL1 and WL2 of the wiring stacks ST are disposed on both sidewalls. The information recording film SL may be electrically connected in common. In addition, the information recording film SL may be disposed on both sidewalls of the adjacent wiring stacks SL to face each other, and in this specification, the opposing information recording films SL may be respectively arranged in the first information recording film. This is referred to as SL1 and second information recording film SL2.

The information recording film SL may include a phase change material, a variable resistive material, a programmable metallization cell (PMC), a magnetic material, or a combination thereof for providing a nonvolatile solid state memory cell. However, it is not limited to these materials and may include other programmable materials. The structure of the information recording film SL and the materials constituting the same will be described later with reference to FIGS. 3A and 3B.

On one surface of the information recording film SL opposite to the plurality of conductive lines WL1 and WL2, a channel film CH including a channel and a control gate structure GS for controlling the electrical conductivity of the channel are in turn. Can be provided. The channel film CH may define intersections with the plurality of conductive lines WL1 and WL2 by extending across the plurality of conductive lines WL1 and WL2, as shown by the cut-out portion of FIG. 1A. . As shown, one channel film CH extends a plurality of conductive lines WL1 and WL2 stacked vertically with respect to the substrate 10, that is, extending in the z direction and crossing points arranged in the z direction. define. In addition, since the channel film CH is arranged two-dimensionally in the x direction and the y direction on the substrate, the intersection points are arranged three-dimensionally, and thus the memory cells defined at the intersection points are also three. Can be arranged dimensionally.

The channel film CH providing the channel may include, for example, a single crystal or polycrystalline semiconductor material. For example, the semiconductor material may include group III-V semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium compounds, GaAs, and InP. However, these materials are illustrative, and the present invention is not limited thereto. For example, the channel film CH may also be provided with a channel by a semiconductor material such as carbon nanotubes or graphene or a metal oxide. If necessary, the channel film CH may be doped with an impurity element to form a suitable N-type or P-type semiconductor.

In order to control the electrical conductivity of the channel film CH, the control gate structure GS is disposed to be in contact with the channel film CH, and the control gate structure GS connects the gate insulating film GI and the gate electrode GE. It may include. The control gate structure GE also extends in the z direction along the channel film CH and may be two-dimensionally spaced apart in the x and y directions on the substrate 10. The material of the gate insulating layer GI and the gate electrode GS may include silicon oxide and a conductive material such as polysilicon or metal, respectively.

The gate insulating layer GI may have a structure surrounding the gate electrode GE, as shown in FIG. 1A, but this is exemplary. For example, the gate insulating film GI may be formed only on the channel film CH by thermally oxidizing an exposed surface of the semiconductor film, which is the channel film CH.

As in the embodiment shown in FIG. 1A, when the first and second information recording films SL1 and SL2 are provided in the adjacent wiring stacks SL facing each other, they are in contact with these films SL1 and SL2. The first channel film CH1 and the second channel film CH2 may be formed, respectively. In this case, when the control gate structure GS is disposed between these films CH1 and CH2 such that the control gate structure GS is disposed in common contact with the first channel film CH1 and the second channel film CH2 facing each other, GS may operate as a common control gate structure GS. Since the common control gate structure GS can control the electrical conductivity of the first channel film CH1 and the second channel film CH2 in common with a single control gate structure, the integrated control circuit and the circuit of the nonvolatile memory device are controlled. There is an advantage to simplify the configuration.

As described above, intersection points are defined by the channel layers CH1 and CH2 intersecting the plurality of conductive lines WL1 and WL2, and regions located at the intersection points of the information recording film SL are in units. Memory cells may be defined. In operation, the plurality of conductive lines WL1 and WL2 may operate as word lines, and the channel films CH1 and CH2 whose electrical conductivity may be controlled by the control gate structure GS may operate as bit lines. . Alternatively, the plurality of conductive lines WL1 and WL2 may operate as bit lines, and the channel layers CH1 and CH2 may operate as word lines. The unit memory cells may be randomly accessed by selecting a plurality of conductive lines and a control gate structure GS electrically connected to each of these cells to apply a suitable signal.

In the above-described embodiments, since the conduction state of the channel films CH1 and CH2 may be turned on / off by a control gate structure coupled thereto, a conventional crossbar type resistive random access memory (ReRAM) or phase change. In a random access memory (PcRAM), rectifying elements such as diodes, which have been applied to prevent interference between adjacent cells, may be omitted.

In some embodiments, the nonvolatile memory device 100 may connect the wiring structures to electrically connect the conductive lines WL1 and WL2, the channel films CH, and the driving circuit of the control gate structure GS. It may further include. For example, for electrical connection of the control gate structure GS, as shown in FIG. 1A, the wiring structure may include lower redistribution structures CL1, CL2, and CL3 formed on the substrate 10. The lower redistribution structures CL1, CL2, and CL3 may be conductive patterns such as impurity regions or metal wires formed in the substrate 10.

The impurity region may be previously formed on the substrate 10 before forming the memory cell array MA. An additional layer cp may be formed for ohmic contact between the lower redistribution structures CL1, CL2, and CL3 and the gate electrode GE. The lower redistribution structures CL1, CL2, CL3 may have suitable configurations to individually access the gate electrode structures GS, and may be exposed at different lengths at the edges of the cell region to achieve electrical connection. have. Likewise, the ends of the channel films CH may have a suitable lower redistribution structure.

Referring to FIG. 1B, a 3D nonvolatile memory device 100B according to another embodiment of the present invention has a wiring structure for electrically connecting the nonvolatile memory device 100 and the control gate structure GS shown in FIG. 1A. There is a difference in the configuration of the other members, the other member may be substantially the same as the member of Figure 1a.

The control gate structure GS for controlling the channel layers CH1 and CH2 intersecting the plurality of conductive lines W1 and W2 for accessing the memory cells has a conductive plug formed on the memory cell array MA. And electrically connected to suitable top redistribution structures via the bridges CP. If necessary, these upper redistribution structures and lower redistribution structures may be applied in combination with each other, and may have stacked redistribution structures by varying heights of the conductive plugs. In addition, it will be understood that the wiring structure for the channel film may be formed in common or separately from the above-described control gate structure GS.

Referring to FIG. 2 of the circuit diagram 100C of the cell array of the nonvolatile memory devices 100A and 100B described above in conjunction with FIGS. 1A and 1B, the word lines WL1, WL2, and WL3 are divided into a plurality of conductive lines. The lines WL1 and WL2 may correspond, and the bit lines BL1 and BL2 may correspond to the channel film CH. In addition, the gate electrodes for controlling the bit lines BL1 and BL2 may be connected to the redistribution structure and accessed individually. The word lines and bit lines described above may be referred to interchangeably, and the present invention is not limited by these terms.

The number of bit lines BL1 and BL2 and word lines WL1, WL2 and WL3 may be appropriately determined according to the memory capacity and the driving method. For example, the number of bit lines BL1 and BL2 and the word lines WL1, WL2, and WL3 is 2 ^{m in} the number of memory cells in each of the x, y, and z directions forming a three-dimensional array. Natural number), and may be designed based on appropriate block and page units to enable fast variable-length access (byte-addressable). According to one embodiment of the present invention, since two memory cells connected to both sides by one control gate structure GS may be commonly controlled, high integration may be achieved.

Memory cells M1, M2, and M3, which are implemented by the information recording layer SL of FIG. 1A, are electrically connected to the intersections of the word lines WL1, WL2, and WL3 and the bit lines BL1 and BL2. Memory cells M1, M2, M3 may be a single resistive memory element as shown, but this is exemplary. For example, as described below with reference to FIGS. 3A and 3B, the programming resistance level is R1 by connecting a plurality of resistance memory elements in series or in parallel, for example, through various configurations of the information recording film SL. It may be provided in various ways, such as <R2 <R3 <R4, whereby a memory cell capable of storing multi-bit information, such as multi-bit information such as 00, 01, 10, and 11, may be implemented.

3A and 3B are cross-sectional views showing the structure of the information recording film SL of the memory cell M according to various embodiments of the present invention.

Referring to FIG. 3A, the information recording film SL is sandwiched between the conductive lines WL1 and WL and the channel film CH. Since the channel film CH extends across the conductive lines WL1 and WL2, intersection points (or intersection regions) can be defined, and portions of the intersection points of the information recording film SL are each non- Volatile memory cells M1 and M2 may be defined.

Operation characteristics of the nonvolatile memory cells M1 and M2 may be determined by the information recording film SL. As described above, the information recording film SL may include a phase change material, a variable resistive material, a programmable metallization cell, a magnetic material, or a combination thereof for providing a nonvolatile solid state memory cell.

The phase change material is a material that can be reversibly converted from an amorphous state to a crystalline state or vice versa, and thus has different resistance values. In general, the phase change material has high resistance in an amorphous state and low resistance in a crystalline state. The phase change material may include, for example, a chalcogenide-based compound such as any one or combination of GeSbTe-based materials, ie, GeSb ₂ Te ₃ , Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te ₄ , or a combination thereof. have. Or, there is a different phase change material, GeTeAs, GeSnTe, SeSnTe, GaSeTe, GeTeSnAu, SeSb2, InSe, GeTe, BiSeSb, PdTeGeSn, InSeTiCo, InSbTe, In ₃ SbTe _2, GeTeSb _2, GeTe ₃ Sb, GeSbTePd or AgInSbTe, These are merely exemplary and the present invention is not limited thereto. In addition, to the above materials, a material further doped with an impurity element, for example, a nonmetallic element such as B, C, N, or P may be applied.

In another embodiment, the information recording film SL may include the variable resistive material whose electrical resistance value may be reversibly changed by an electrical signal. The variable resistive material is a material that can be reversibly converted between a low resistance state and a high resistance state, similar to the phase change material described above. As an example of the variable resistance _{material, SrTiO 3, SrZrO 3, Nb} : Fe lobe, such as SrTiO ₃ Sky teugye oxide or _{TiO x, NiO, TaO x,} HfO x, AlO x, ZrO x, CuO x, NbO x, and TaO _x , Transition metal oxides such as GaO _x , GdO _x , MnOx, PrCaMnO, and ZnONIO _x .

The perovskite oxide and the transition metal oxide exhibit switching characteristics of resistance values according to electrical pulses. To explain these switching characteristics, various mechanisms related to conductive filaments, interfacial effects and trap charges have been proposed, but these mechanisms are not clear. However, these materials can be applied as the information recording film SL because they commonly have a factor having some kind of hysterisis affecting the current caused by electrons in a microstructure suitable for nonvolatile memory applications.

The hysteresis may have characteristics distinguished according to a unipolar resistance material and a bipolar resistance material irrespective of the polarity of the applied voltage, but the present invention is not limited thereto. For example, the nonvolatile information recording film SL may be made of only a monopolar resistive material or may be made of only a bipolar resistive material. Alternatively, the nonvolatile information recording film SL may be designed for multi-bit driving by including a laminated structure of a film made of the unipolar resistive material and a film made of the bipolar resistive material.

In another embodiment, the information recording film SL may include a programmable metallization cell. For example, the plurality of conductive lines WL1 and WL2 are electrochemically active, for example, oxidizable silver (Ag), terulium (Te), copper (Cu), tantalum (Ta), titanium ( A metal electrode such as Ti) or a relatively inert metal electrode such as tungsten (W), gold (Au), platinum (Pt), palladium (Pd), and rhodium (Rh) The information recording film SL may be implemented by disposing a programmable metallization cell PMC including an electrolyte material having super ion regions between the lines WL1 and WL2 and the channel film CH.

The PMC material may exhibit resistance change or switching characteristics through physical rearrangement of super ion regions in the electrolyte material. The electrolyte material having the super ion regions may be, for example, a base glass material such as germanium selenium compound (GeSe) material. The GeSe compound may also be referred to as chalcogenide glass or chalcogenide material. Such GeSe compounds include Ge ₃ Se ₇ , Ge ₄ Se _6, or Ge ₂ Se ₃ . In other embodiments, other known materials may be used.

In another embodiment, the information recording film SL may comprise the magnetic material. The magnetic material may be, for example, a composition comprising a combination of Mg, Ni, CO, and / or Fe. In this case, the nonvolatile information recording film SL may include a Giant Magneto Resistive (GMR) structure or a Tunneling Magneto Resistance (TMR) structure. In the case of the tunneling magnetoresistive structure, the nonvolatile information recording film SL may include a magnetic tunneling junction obtained by a laminated structure of a suitable insulating film together with a film made of these magnetic material, and known Spin torque transfer memory can be implemented.

The materials described above with respect to the above-described nonvolatile information recording film SL may have a single layer or a plurality of stacked structures. For example, as shown in FIG. 3A, the nonvolatile information storage film SL may include a stack structure of the films 41 and 42 made of the above materials. For example, the nonvolatile information recording film SL may include two or more films 41 selected from the above-described phase change material film, change material, variable resistive material, programmable metallization cell (PMC), and magnetic material. 42). The stacked structure may be combined with each other, and may be connected in series or in parallel between the conductive lines WL1 and WL2 and the channel film CH.

In terms of design, adjacent memory cells M1, M2 are used to prevent cell separation of adjacent memory cells M1, M2 and / or crosstalk therebetween, for example, thermal interference in the case of a phase change memory. The spacing d between the conductive lines WL1 and WL2 that determines the spacing of can be appropriately designed. In another embodiment, crosstalk may be reduced by reducing the programming area of the information storage layer SL to effectively increase the distance between the memory cells M1 and M2. For example, as illustrated in FIG. 3B, the plurality of conductive lines WL1 and WL2 may be recessed from the side surfaces of the interlayer insulating layer patterns 20P1, 20P2, and 20P3 of the wiring stack ST by r. . This etching process may be achieved through isotropic etching of the plurality of conductive lines WL1 and WL2 after forming the wiring stacks (see ST in FIG. 4C), which will be described later. As such, when the programming area is reduced, the driving power of the nonvolatile memory device may also be reduced.

4A to 4L are perspective views sequentially illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention. With regard to the constituent members of these figures having the same reference numerals as the constituent members described above with reference to FIGS. 1A to 3B, reference may be made to the foregoing disclosure unless contradictory.

Referring to FIG. 4A, a substrate 10 is provided. Substrate 10 may include, for example, silicon-based structures such as silicon, silicon-on-insulator (SOI), silicon-germanium, or silicon-on-sapphire (SOS), or germanium, and gallium-arsenic compound materials. The same III-V semiconductor material may be included. Alternatively, the substrate 10 may include other materials than the semiconductors described above, and these materials are exemplary only, and the present invention is not limited to these materials.

The cell array region and the core region may be defined in the substrate 10, and since the above-described memory cell array MA has a three-dimensional structure, the cell array region and the core region may have a step difference. For example, the cell array region may be defined by etching in the depth direction of the substrate 10 rather than the core region, whereby the cell array region and the core region may have a step difference. Such a step is useful for forming a wiring structure for connecting a plurality of conductive lines used as word lines with an external circuit. In some embodiments, on the substrate 10, as described above with reference to FIG. 1A, lower redistribution structures CL1, CL2, CL3 for electrical connection of the control gate structure (see GS of FIG. 1A) are provided. It may be further formed. If necessary, a wiring structure for electrically connecting the aforementioned channel films may be further formed, and the wiring structure may be common to the lower redistribution structures CL1, CL2, and CL3.

Referring to FIG. 4B, the first insulating layers 20L1, 20L2, and 20L3 and the first conductive layers WD1 and WD2 are alternately and repeatedly stacked on the substrate 10 in order. The number and thickness of these films can be appropriately selected. The first insulating films 20L1, 20L2, and 20L3 may be, for example, insulating films such as silicon oxide, silicon nitride, and / or silicon oxynitride, for example, by plasma enhanced chemical vapor deposition or chemical vapor deposition. Can be formed.

The thicknesses of the first conductive layers WD1 and WD2 may be the same. The first conductive layers WD1 and WD2 may be formed by physical vapor deposition or chemical vapor deposition such as sputtering. The first conductive films WD1 and WD2 become a plurality of conductive lines (see WL1 and WL2 in FIG. 1A) through a process of forming the wiring stacks ST, which will be described later. For example, the first conductive films WD1 and WD2 may have high conductivity. Metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si) , Copper (Cu), nickel (Ni), cobalt (Co), or molybdenum (Mo), or an alloy thereof. Alternatively, the first conductive films WD1 and WD2 may be formed of conductive nitrides (eg, TiN, MoN, etc.), conductive oxygen nitrides (eg, TiON, etc.), or a combination thereof (eg, TiSiN, TiAlON, etc.) may be included. These materials are exemplary and the present invention is not limited thereto. For example, the first conductive films WD1 and WD2 may be poly-doped polysilicon films. Further, the first conductive films WD1 and WD2 may include other suitable materials capable of forming a reliable interface with the nonvolatile information recording film SL.

A mask film having a line pattern may be provided on a result of repeatedly stacking the first insulating layers 20L1, 20L2, and 20L3 and the first conductive layers WD1 and WD2. The line pattern of the mask layer may extend in a first direction (eg, x direction) parallel to the substrate 10.

Referring to FIG. 4C, the stacked first insulating layers 20L1, 20L2, and 20L3 and the first conductive layers WD1 and WD2 are successively patterned by using a mask layer Mask as an etching mask. And a plurality of wiring stacks ST spaced apart in parallel to each other in a second direction different from the x direction (eg, the y direction). The patterning process may be performed through a dry etching process such as reactive ion etching. In the wiring stacks ST, a plurality of first interlayer insulating layer patterns 20P1, 20P2, and 20P3 derived from the first insulating layers 20L1, 20L2, and 20L3 and a plurality of first conductive layers WD1 and WD2 may be formed. Conductive lines WL1 and WL2 are repeatedly stacked.

Alternatively, the plurality of conductive lines WL1 and WL2 may be recessed by r from the side surfaces of the interlayer insulating layer patterns 20P1, 20P2, and 20P3 of the wiring stack ST. The recess process may be achieved through isotropic etching using an etching selectivity of the plurality of conductive lines WL1 and WL2 with respect to the interlayer insulating layer patterns 20P1, 20P2 and 20P3. In this case, the information recording film described later can be locally provided in the recessed groove so that the program region can be substantially limited to less than or equal to the thickness of the conductive lines WL1 and WL2, thereby reducing the crosstalk between the driving power and the adjacent cells. There is an advantage that can be prevented.

Referring to FIG. 4D, the information recording material layer SM is conformally formed on the wiring stacks ST. As a result, the information recording material layer SM can be formed to have a uniform thickness on the sidewalls that face each other of the wiring stacks ST. The illustrated information recording material layer SM may be a single layer or a stacked structure composed of a plurality of layers including a metal layer for electrodes and nonvolatile memory films such as a phase change material, as described with reference to FIGS. 3A and 3B. have.

Referring to FIG. 4E, a second insulating film 30 is formed next to fill trenches TC between the plurality of wiring stacks ST on which the information recording material layer SM is formed, and is indicated by arrow A. FIG. As such, a planarization process may be performed. The planarization process may be performed up to the highest pattern 20P3 among the first interlayer insulating layer patterns 20P1, 20P2, and 20P3, as illustrated, but the present invention is not limited thereto. As a result, as shown in FIG. 4F, the first and second information recording films SL1 and SL2 facing each other formed on the sidewalls of the wiring stacks ST are defined, and the space therebetween is defined as the second insulating film. 30 can be filled.

Referring to FIG. 4G, first through holes H1 penetrating the second insulating film 30 in the vertical direction (ie, the z direction) in contact with the first information recording film SL1 and / or the second information recording films. ). Subsequently, channel layers CH1 and CH2 CH are formed to fill the first through holes H1. Thereby, the information recording films SL1 and SL2 between the plurality of conductive lines WL1 and WL2; The channel films CH1 and CH2 CH may be formed to extend across the plurality of conductive lines WL1 and WL2 while sandwiching the SL.

Referring to FIG. 4I, second through holes H2 penetrating the second insulating film 30 in the vertical direction (that is, the z direction) are formed in contact with the channel films CH. The second through holes H2 may penetrate to a depth that exposes the contact pads CP of the lower redistribution structures CL1, CL2, and CL3. In this case, the through holes H2 are formed to penetrate through the information recording film SL existing on the bottom surface.

In some embodiments, the second through holes H2 may be formed in common contact with the first and second channel films CH1 and CH2 facing each other, as shown. As a result, as will be described later, a common control gate structure capable of controlling the electrical conductivity of the first and second channel layers CH1 and CH2 in common with one control gate structure GS can be achieved.

Referring to FIG. 4J, a gate insulating layer GI may be formed on the channel layers CH. As illustrated in FIG. 4J, the gate insulating layer GI may be formed by conformally depositing an insulating layer on the entire sidewall of the second through hole H2. In another embodiment, the gate insulating layer GI may be formed by thermally oxidizing the surfaces of the channel layers H3 exposed through the second through holes H2. In this case, the gate insulating film GI may be locally disposed only on the channel films H3. Thereafter, the gate electrode (see GE of FIG. 1) may be formed by forming a conductive film filling the space H3 in the second through hole H2 defined by the gate insulating film GI.

4K and 4L are manufacturing methods according to another embodiment in contrast to the order of the unit manufacturing process shown in FIGS. 4G-4J. Referring to FIG. 4K, unlike FIG. 4G, the second through holes H2 may be formed before the first through holes H1. Subsequently, referring to FIG. 4L, a gate insulating film GI filling the second through hole H2 and a gate electrode GE surrounded by the gate insulating film GI are formed. Subsequently, first through holes H1 penetrating the second insulating film 30 in the vertical direction may be formed to contact the information recording film SL and the gate insulating film GI. Thereafter, the channel film CH may be formed by filling the inside of the through holes H1 with a semiconductor material.

As described above, after the channel film CH and the control gate structure GS are completed, a nonvolatile memory device may be completed by completing the wiring structure for connection with an external circuit, if necessary. 4A through 4L describe the nonvolatile memory device 100A shown in FIG. 1, but those skilled in the art will further form a suitable upper redistribution structure to obtain the nonvolatile memory device 100B shown in FIG. 1B. I will understand.

The above-described three-dimensional nonvolatile memory device may be implemented in the form of a system on chip (SOC) together with other heterogeneous devices, for example, a logic processor, an image sensor, and an RF device, in one wafer chip. There will be. Alternatively, the wafer chip on which the 3D nonvolatile memory device is formed and the other wafer chip on which the heterogeneous devices are formed may be bonded by using an adhesive or a wafer bonding technique to form a single chip.

In addition, the 3D nonvolatile memory devices according to the above embodiments may be implemented as various types of semiconductor packages. For example, the 3D nonvolatile memory device according to the embodiment of the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in Line Package (PDIP), Die in Waffle Pack, Die in Wafer FoSM, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) Alternatively, the package may be packaged in a Wafer-Level Processed Stack Package (WSP). The package in which the 3D nonvolatile memory device is mounted according to embodiments of the present invention may further include a controller and / or a logic element for controlling the 3D nonvolatile memory device.

5 is a block diagram illustrating an example of an electronic system 1100 including a nonvolatile memory device according to example embodiments.

Referring to FIG. 5, an electronic system 1100 according to an embodiment of the present invention may include a controller 1110, an input / output device (I / O) 1120, a memory device 1130, an interface 1140, and a bus ( bus 1150). The controller 1110, the input / output device 1120, the memory device 1130, and / or the interface 1140 may be coupled to each other through the bus 1150.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The memory device 1130 may include at least one of the three-dimensional nonvolatile memory devices disclosed in the first and second embodiments described above. In addition, the memory device 1130 may have a hybrid structure further including other types of semiconductor memory devices (for example, DRAM devices and / or SRAM devices). The interface 1140 may perform functions to transmit data to or receive data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 may further include a high speed DRAM and / or an SRAM as an operation memory for improving the operation of the controller 1110.

The electronic system 1100 may include a personal digital assistant (PDA) portable computer, a tablet PC, a wireless phone, a mobile phone, and a digital music player. It can be applied to a digital music player, a memory card, or any electronic product capable of transmitting and / or receiving information in a wireless environment.

FIG. 6 is a block diagram illustrating an example of a memory card 1200 including a 3D nonvolatile memory device according to example embodiments.

Referring to FIG. 6, a memory card 1200 according to an embodiment of the present invention includes a memory device 1210. The memory device 1210 may include at least one of the three-dimensional nonvolatile memory devices disclosed in the first and second embodiments described above. In addition, the memory device 1210 may further include other types of semiconductor memory devices (eg, DRAM devices and / or SRAM devices). The memory card 1200 may include a memory controller 1220 that controls the exchange of data between the host and the storage device 1210.

The memory controller 1220 may include a processing unit 1222 for controlling the overall operation of the memory card. In addition, the memory controller 1220 may include an SRAM 1221 used as an operating memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225. The host interface 1223 may include a data exchange protocol between the memory card 1200 and the host. The memory interface 1225 can connect the memory controller 1220 and the memory device 1210. In addition, the memory controller 1220 may further include an error correction block (ECC) 1224. Error correction block 1224 can detect and correct errors in data read from storage device 1210. [ Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. Memory card 1200 may be used as a portable data storage card.

The above-described nonvolatile memory device may be implemented as a solid state disk (SSD) that can replace a hard disk of a computer system. In this case, the three-dimensional nonvolatile memory device according to the embodiment of the present invention may be highly integrated to provide petascale computing performance and to enable high-speed data input and output.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

100A, 100B: Cell Array of Three-Dimensional Nonvolatile Memory Devices
100C: Schematic diagram of a three-dimensional nonvolatile memory device
WL1, WL2: a plurality of conductive lines
0P1, 20P2, 20P3: interlayer insulating film patterns
ST: wiring stacks CH1, CH2, CH: channel film
GE: gate electrode GI: gate insulating film
GS: control gate structure

Claims (12)

A plurality of wiring stacks extending in a horizontal direction and stacked in a vertical direction on the substrate and spaced apart from each other;
An information recording film formed on sidewalls of the wiring stacks and electrically connected to the plurality of conductive lines;
At least a portion of the information recording film extends in a vertical direction to intersect the plurality of conductive lines and intersects the plurality of conductive lines, while sandwiching the information recording film between the plurality of conductive lines. Channel films in which non-volatile memory cells are formed; And
A gate insulating film formed on one surface opposite to the plurality of conductive lines of the channel films, and a gate insulating film formed on one surface opposite to the channel film of the gate insulating film to control electrical conductivity of each channel film, thereby controlling the non-volatile memory And a control gating structure having a gate electrode for controlling an electrical connection between cells and each channel film. The method of claim 1,
The information recording film includes first and second information recording films disposed on sidewalls of the wiring stacks adjacent to each other and opposing each other,
The channel films extend in a vertical direction to intersect the plurality of conductive lines, while sandwiching the plurality of conductive lines of the neighboring wiring stacks and the first and second information recording films, respectively, and the plurality of conductive lines. First and second channel films in which regions of the nonvolatile memory cells including at least a portion of the first and second information recording films are defined in regions that intersect the first and second information recording films.
And the control gate structure is a common control gate structure of the first and second channel layers disposed in contact with the first and second channel layers. The method of claim 1,
And the information recording film comprises a phase change material, a variable resistive material, a programmable metallizing cell (PMC) material, a magnetic material, or a combination thereof. The method of claim 1,
And the plurality of conductive lines operate in any one of a word line and a bit line, respectively, and the channel layer operates in the other of the word line and the bit line. The method of claim 1,
The wiring stacks further include interlayer insulating layer patterns for electrically separating the plurality of conductive lines,
And the plurality of conductive lines are recessed from side surfaces of the interlayer insulating layer patterns. Alternately stacking first insulating films and first conductive films alternately on a substrate;
Continuously patterning the stacked first insulating layers and the first conductive layers to form wiring stacks including a plurality of conductive lines and interlayer insulating layer patterns therebetween and spaced apart from each other;
Forming an information recording film on a surface including opposite sidewalls of said wiring stacks;
A non-volatile that extends across the plurality of conductive lines while sandwiching the information recording film between the plurality of conductive lines and includes at least a portion of the information recording film in regions intersecting the plurality of conductive lines. Forming channel films in which memory cells are defined; And
A gate insulating film in contact with the channel films, and a gate electrode formed on the gate insulating film to control electrical conductivity of each of the channel films, thereby controlling electrical connection between the nonvolatile memory cells and the respective channel films. Forming gate structures. 7. The method of claim 6, wherein the forming of the information recording film comprises:
Conformally forming an information recording material layer on the wiring stacks;
Forming a second insulating film filling the trenches between the wiring stacks; And
Planarizing the second insulating film until the surfaces of the wiring stacks are exposed. The method of claim 7, wherein the forming of the channel film,
Forming a first through hole in contact with the information recording film and penetrating the second insulating film in a vertical direction; And
And filling the first through hole with a semiconductor material. The method of claim 8, wherein forming the control gate structures comprises:
Forming a second through hole contacting the channel layers to penetrate the second insulating layer in a vertical direction;
Forming the gate insulating layer in contact with the channel layer in the second through hole; And
And forming the gate electrode in the second through hole so as to contact the gate insulating layer. The method of claim 7, wherein forming the control gate structures,
Forming a second through hole penetrating the second insulating film between the wiring stacks in a vertical direction; And
And forming the gate electrode surrounded by the gate insulating film and the gate insulating film in the second through-hole. The method of claim 10, wherein the forming of the channel film,
Forming a first through hole penetrating the second insulating film in a vertical direction so as to contact the information recording film and the gate insulating film; And
And filling the first through hole with a semiconductor material. The method according to claim 6,
And the information recording film comprises a phase change material, a variable resistive material, a programmable metallization cell material, a magnetic material, or a combination thereof.

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