CN106298832A - A kind of non-volatile memory device and manufacture method - Google Patents
A kind of non-volatile memory device and manufacture method Download PDFInfo
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- CN106298832A CN106298832A CN201510319361.7A CN201510319361A CN106298832A CN 106298832 A CN106298832 A CN 106298832A CN 201510319361 A CN201510319361 A CN 201510319361A CN 106298832 A CN106298832 A CN 106298832A
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Abstract
The invention belongs to non-volatile memory technologies field, it is provided that a kind of non-volatile memory device reducing write operation voltage and manufacture method.The non-volatile memory device of the present invention, including: inverted cone shape the first electrode；Storage medium layer, it includes Part I, Part II and Part III, wherein said Part I is attached on the lateral surface of inverted cone shape the first electrode, the described Part II lower end that be arranged so that with described Part I non-parallel with the lateral surface of described inverted cone shape the first electrode is connected and is formed the first angle, and the described Part III upper end that be arranged so that with described Part I non-parallel with the lateral surface of described inverted cone shape the first electrode is connected and forms the second angle；On second electrode, its first angle being formed at described storage medium layer and the second angle.The non-volatile memory device of the present invention is by forming the angle structure of storage medium layer between the first electrode and the second electrode, and write operation voltage is reduced and uniformly, preparation is simple, low cost.
Description
Technical field
The invention belongs to non-volatile memory technologies field, relate to one and can reduce non-volatile
The memory element structure design of the write operation voltage of memory element and manufacture method thereof.
Background technology
For low-power consumption and the high-density applications target of non-volatile memory semiconductor device, have
Multiple research launches, including on material, on device architecture, in manufacture method and peripheral circuit sets
A series of exploration has been carried out on meter.
Even if the data that flash memory is storage the most also can obtain the non-volatile memory retained
Represent.Flash memory has non-volatile, different from volatile memory.But, flash memory has low integrated
Spend and need the most voltage-operated shortcoming.
Nonvolatile storage having been carried out much research now, these nonvolatile storages include
Magnetic random memory (MRAM), ferroelectric RAM (FRAM), phase-change random access
Access memorizer (PRAM) and resistive ram (RRAM).
If the magnitude of voltage required for operation memory element reduces, then the transistor of peripheral circuit
Size just can reduce, and thus can improve the integrated number of memory element in unit are.
Along with the further micro of memory device size, the device parameters between memory element and electricity
Learning the fluctuation aggravation of parameter, this problem can cause the reliability of storage array to reduce.Reduce and write behaviour
Make voltage and can improve the reliability of array to a certain extent.Particularly, resistor random-access is deposited
For access to memory, the conductive filament that applying initial breakdown voltage is formed is in storage medium layer
Randomly generating, along with reducing of device size, what conductive filament produced is located proximate to device edge
The probability in etching injury region can increase, etching injury region forms the size meeting of conductive filament
Relatively big, the electric current flowed through also can be relatively big, and this will be unfavorable for the requirement of low-power consumption.Therefore, if conducting electricity
Filament can produce the center at device cell regularly, this can suppress each device
The size of the initial breakdown voltage between unit and deviation thereof, it is possible to improve the reliable of storage array
Property.
The U.S. Patent No. US 2013,0112936A1 of Zhiqiang Wei et al., entitled
The patent of " Resistance change element and manufacturing method therefor "
In propose a kind of device structure design, as shown in figure 13.So that electric field is in fixing position
Put gathering so that initial breakdown occurs in the position of fixing needle-like portion electrode, for resistance-varying type
Memory element for, can control occur resistance variations phenomenon filament region (filament)
Happening part.Thereby, it is possible to resistance when suppressing the initial breakdown voltage of each element, action
The deviation of value.The design to electro-resistance element is needed as deviation countermeasure as a result, it is possible to cut down
The surplus that size is added, it is possible to realize the storage granular of device, high capacity.
The U.S. Patent No. US 2014,0061573A1 of Takumi Mikawa et al., entitled
“Nonvolatile memory element,Nonvolatile memory device,and methods of
Manufacturing the same " patent in propose a kind of device structure design, such as Figure 14 institute
Show, so that conductive filament is formed at the stage portion that different two-layer resistive dielectric layers is formed
Position, and this stepped portions is in the center of memory element.And the high resistant of stepped portions
The storage medium thickness of value reduces, and can reduce the initial breakdown voltage forming conductive filament.And
The position that conductive filament produces is fixed, and can reduce the inclined of initial breakdown voltage between memory element
Difference.When the size reduction of memory element, centre is affected the least by edge, can subtract
Between little different memory element, the deviation of resistance value, can improve reliability, it is possible to realize storage device
Granular, high capacity.
It appeared that, it has been suggested that the structure design of non-volatile memory device, substantially logical
Cross position that fixing conductive filament occurs to reduce write operation voltage and the deviation of write operation voltage, real
The granular of existing storage device, high capacity.
Summary of the invention
It is an object of the invention to, it is provided that a kind of have the non-volatile of new memory element structure
Memory element.
For realizing object above or other purposes, the present invention provides techniques below scheme.
It is an aspect of this invention to provide that provide a kind of non-volatile memory device, comprising:
First electrode and the second electrode, and storage Jie being placed between the first electrode and the second electrode
Matter layer.Wherein the first electrode is inverted cone, and its cone angle is α, 60 °≤α≤80 °.Storage medium
Layer, including Part I, Part II and Part III, wherein said Part I is attached to down
On the lateral surface of taper the first electrode, described Part II and the outside of described inverted cone shape the first electrode
The non-parallel lower end being arranged so that with described Part I, face is connected and is formed the first angle, described
The lateral surface of Part III and described inverted cone shape the first electrode is non-parallel to be arranged so that and described the
The upper end of a part connects and forms the second angle；
Second electrode is formed at outside storage medium, around surrounding storage medium layer.First electrode and
Second electrode is kept apart by storage medium layer.
In embodiment described before, described storage medium layer can be variable-resistance material, bag
Include such as Metal Oxide Varistor material, be selected from AlOx, WOx, TaOx, SiO2,
The materials such as HfOx, TiOx, GeSbyTex.
In the most described embodiment, described first electrode material can be by being selected from
A kind of material in Pt, Ag, Cu, TaN, TiN, Al, W or its alloy is formed.
In the most described embodiment, described second electrode material can be by being selected from
A kind of material in Pt, Ag, Cu, TaN, TiN, Al, W or its alloy is formed.
It is an aspect of this invention to provide that provide the manufacture method of a kind of non-volatile memory device,
Comprising:
Inverted cone shape the first electrode is formed in first medium layer；
To first medium layer-selective etching so that the bigger upper end of described inverted cone shape the first electrode
Part exposes formation pylon structure；Deposit conformal being covered on this pylon structure and first medium layer
Storage medium layer, so that storage medium layer at least includes the outside being attached to inverted cone shape the first electrode
Part I on face and second of the non-parallel setting of lateral surface of described inverted cone shape the first electrode
Dividing and Part III, described Part I is connected with the lower end of described Part I and forms the first folder
Angle, described Part I is connected with the upper end of described Part III and forms the second angle；Described
The second electrode is formed on first angle of storage medium layer and the second angle.
Deposit the second electrode material layer；Second electrode material layer patterned etch is retained and is attached to back taper
Part I on the lateral surface of shape the first electrode, it is formed at the upper surface of described first medium layer
Part II and be formed at Part III on the upper surface of described inverted cone shape the first electrode.
This manufacture method is mutually integrated with the rear end structure preparation technology of cmos circuit；
Wherein, described first medium layer is metal interlamination medium layer, and described inverted cone shape the first electrode is
For connecting the metal via structure of interconnection line layer, described second electrode is of this interconnection line layer
Point.
The non-volatile memory device of the present invention is by being formed between the first electrode and the second electrode
The angle structure of storage medium layer, program voltage is reduced and uniformly, and be simple to manufacture, cost
Low and convenient compatible with standard CMOS process.
Accompanying drawing explanation
From combine accompanying drawing described further below, it will make the present invention above and other purpose and
Advantage is more fully apparent from, and wherein, same or analogous key element is adopted and is indicated by the same numeral.
Fig. 1 is the section view of the structure of the non-volatile memory device according to one embodiment of the invention
Figure.
Fig. 2 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The simplification structure that the analog simulation of congregational rate is used.
Fig. 2 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The reduced parameter that the analog simulation of congregational rate is used.
Fig. 3 is that the electric field of the structure of the non-volatile memory device according to one embodiment of the invention gathers
The analog result of collection effect.
Fig. 4 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 4 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 5 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 5 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 6 A is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 6 B is the electric field of the structure of the non-volatile memory device according to one embodiment of the invention
The analog result of congregational rate.
Fig. 7 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Fig. 8 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Fig. 9 is the manufacturer of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 10 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 11 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 12 is the manufacture of the structure of the non-volatile memory device according to one embodiment of the invention
The sectional view of the operation of method.
Figure 13 is an existing non-volatile memory device sectional view.
Figure 14 is existing another non-volatile memory device sectional view.
Detailed description of the invention
Be described below is that the multiple of the present invention may some in embodiments, it is desirable to provide to this
Bright basic understanding, it is no intended to confirm that the crucial of the present invention or conclusive key element or limit is wanted
The scope of protection.Easy to understand, according to technical scheme, in the reality not changing the present invention
Under matter spirit, one of ordinary skill in the art can propose other the realization sides that can mutually replace
Formula.Therefore, detailed description below and accompanying drawing are only the examples to technical scheme
Property explanation, and be not to be construed as the whole of the present invention or be considered as the restriction to technical solution of the present invention
Or limit.
In explained below, clear and simple and clear for describe, not all many to shown in figure
Individual parts are described in detail.It is that those of ordinary skill in the art carry shown in the drawings of multiple parts
The disclosure being fully able to realize for the present invention.To those skilled in the art, many
The operation of parts is all to be familiar with and obvious.
Fig. 1 represents the cross section of the non-volatile memory device 200 made by this experiment.Non-
Volatile memory elements 200 is to embed the first electrode 21, storage medium in first medium layer 20
Layer the 22, second electrode 23 is constituted, and is formed on next layer of metal interconnecting wires 26, metal afterwards
Through-hole interconnection 27.With reference to Fig. 1, the first electrode 21 be shaped as inverted cone, cone angle is by technique system
Standby conditional decision, can form the angle between 60 ° to 80 °.First electrode can be
The alloy of one or more in the metals such as Pt, Ag, Cu, TaN, TiN, Al, W.Storage medium layer 22
Be divided into three parts, be respectively attached to the first electrode 21 inverted cone shape lateral surface Part I 22a,
Be deposited on the first electrode 21 inverted cone shape upper bottom surface Part II 22b and with the first electrode 21
Inverted cone shape lateral surface nonparallel Part III 22c.Storage medium material 22 can be resistance variations
The material of type, such as aluminium oxide (AlOx), tungsten oxide (WOx), hafnium oxide (HfOx),
Tantalum oxide (TaOx), titanium oxide (TiOx), silicon oxide (SiO2), zinc oxide (ZnOx), oxygen
Change a kind of material in nickel (NiOx) or the combination of different materials.The material composition of 22a and 22b
Being identical, the technique deposit mode used during deposition storage medium material 22 has conformality and covers
Lid feature, the thickness of 22a, 22b and 22c part is identical.Wherein 22a with 22b constitutes
First angle 24,22a Yu 22c constitutes the second angle 28.The material of the first electrode 21 is because of storage
The difference of medium and be allowed a choice.Such as, when storage medium 22 is AlOx, the first electrode
21 can use the metals such as TaN, TiN, Al, W；And when storage medium 22 is SiO2,
First electrode 21 can use the ripple metal alive such as Ag, Cu.The material of storage medium 22 can also
It it is germanium antimony tellurium alloy (GeSbyTex) phase-change material.When storage medium 22 is GST phase-change material
Time, the first electrode metal can select the materials such as TiN, W, TiAlN, TiW.Storage medium
The thickness of 22 also can select different-thickness value because of the difference of material.Particularly, resistance is become
For changing storage material, the thickness of storage medium 22 is between 10nm to 100nm.Second electricity
Pole 23 is deposited on the outside of 22a and the top of 22b and 22c.Second electrode 23 is selected from
One or several alloy of the metals such as Pt, Ag, Cu, TaN, TiN, Al, W.Second electrode 23
Thickness is without particular/special requirement, minimum more than 10nm.Second electrode be arranged above interconnect metal 26.Mutually
Even metal 26 can identical from the second electrode material can also be different.For Al interconnection architecture, mutually
Even metal 26 can be Al.For Cu interconnection architecture, interconnection metal 26 can be Cu.Mutually
Connect metal 26 is arranged above (N+1) layer metal through-hole interconnection 27.Above-mentioned all metals are all
Isolated by first medium 20.First medium 20 is layer insulation medium, such as by etc.
Ion TEOS or the reduction effectively (example Han oxyfluoride for the parasitic capacitance between wiring
Such as FSG) or low-k material composition.
By making structure as shown in Figure 1, when the first electrode 21 and the second electrode 23 are executed respectively
When being biased programming signal, the distribution of the electric field intensity in storage medium layer 22 is heterogeneous.
In angle 24 position and angle 28 position, it will there is electric field congregational rate.For resistance variations
For storage material, conductive filament can be formed in the position that electric field intensity is maximum.For phase change memory
For device, due to horn structure herein, highest current density, heats is notable, therefore may be used
With reduce phase transition storage write program voltage.
In order to verify the electric field intensity congregational rate in wedge angle position, Fig. 2～Fig. 6 is to use
This non-volatile memory device is carried out under electrostatic field environment by COMSOL multiple physical field simulation softward
Electric-field intensity distribution calculate.For this non-volatile memory device 200, the first electrode 21
For reverse tapered shape, storage medium 22 and the second electrode 23 uniform ring are around being deposited on inverted cone shape structure
Lateral surface and upper bottom surface and peripheral region.Therefore total is axisymmetry structure.Select one
Individual section carries out the simulation of electric field intensity, and the analog result in this plane is permissible in stereochemical structure
Popularization is come.
Fig. 2 A is the section rough schematic view of non-volatile memory device 200, is arranged by the first electrode
For bottom electrode, bottom electrode ground connection；Second electrode is set to upper electrode, and upper electrode applies biasing and compiles
Journey signal.Fig. 2 B is the geometry division figure in COMSOL software to the structure shown in Fig. 2 A,
The unit of its abscissa and vertical coordinate is nanometer.Wherein the thickness of storage medium 22 is set to
30nm, this is rational for the storage medium of resistance-varying type, by storage medium 22
Relative dielectric constant is set to 6.0, and this is for several widely studied resistance variations storage materials,
For AlOx, TaOx material, also it is reasonable.In Fig. 2 B, coordinate is (0,0), (200,0),
(0,548.4), it is trapezoidal for first electrode area that these four points of (400,548.4) are formed, and this is straight
The value of the on-right angle acute angle that angle is trapezoidal is 70 °.The exterior lateral area of this right-angled trapezium is storage medium layer,
Thickness is 30nm, and the outside of storage medium layer is the second electrode region, is 6 limits in fig. 2b
Shape, 6 apex coordinates of this 6 limit shape are respectively (0,578.4), (0,700), (600,700),
(600,428.4), (386.4,428.4), (440.9,578.4).First electrode area and second
The region of electrode zone sandwich is storage medium region.Angle 24 and 28 is set to 70 °,
This, for technique manufactures, is also rational.When carrying out electric field simulation and calculating, wherein go up electrode
Apply program voltage 5V, bottom electrode ground connection, be set to 0V.The setting of this voltage is for resistance
For the non-volatile memory device of change type, it is rational.
Fig. 3 shows the result of static field simulation.Wherein electric field intensity is in storage medium 22
It is unevenly distributed.The region at our storage medium 22c and 22a place is referred to as sandwich knot
Structure part, by the most lower for the position at angle 24 place horn structure part, by angle 28 place
The referred to as upper horn structure part in position.For the planar structure simplified, the face of sharp corner
Long-pending being similar to a little, electric field intensity levels off to infinity herein.Similarly for the stereochemical structure simplified
Speech, the area approximation of sharp corner position is in line, and electric field intensity also levels off to infinity herein.But it is right
For the device manufactured in reality, sharp corner has real area, and area herein is relatively
In storage medium, the area at other positions is little.As it is shown on figure 3, at sandwich structure, electric-field strength
Degree is evenly distributed.In upper wedge angle 28 and lower wedge angle 24 position, electric field intensity is increased dramatically,
Figure is expressed as gray value and becomes big, as in figure, coordinate is at upper wedge angle 28 and lower wedge angle 24 position
Shown in (400,548.4) and (386.4,428.4), these 2 colors around are than other positions
Color deep..In order to analyze at sandwich structure further and two wedge angle 24 and 28 positions
Electric field intensity change, We conducted and further analyze, such as Fig. 4, Fig. 5 and Fig. 6 institute
Show.
Fig. 4 shows the electric field intensity analog result of sandwich position.Fig. 4 A shows us
The position that ordinate value is 563.4nm intercepted in Fig. 2 B carries out electric field intensity calculating, such as Fig. 4 A
In Lycoperdon polymorphum Vitt straight line shown in.Fig. 4 B shows the electric field at the Lycoperdon polymorphum Vitt linear position selected by Fig. 4 A
Intensity distributions.Result shows, the sandwich position in storage medium layer 22, electric field intensity
Being uniformly distributed, value is about 1.7*108V/m, during to close upper electrode, electric field intensity strongly reduces.
Fig. 5 shows the electric field intensity analog result of wedge angle 28 position.Fig. 5 A shows me
Intercept the position that the ordinate value in Fig. 2 B is 548.4nm and carry out electric field intensity calculating, such as figure
Shown in Lycoperdon polymorphum Vitt straight line in 5A.Fig. 5 B shows at the Lycoperdon polymorphum Vitt linear position selected by Fig. 5 A
Electric-field intensity distribution.Result shows, in storage medium layer 22, and the distribution non-thread of electric field intensity
Property, the close bottom electrode position at sandwich structure, electric field intensity is 1.7*108V/m, keeps
Constant.When near wedge angle position, electric field intensity is increased dramatically, electrode position on close
Maximum occur, strongly reducing afterwards is 0.Electric field intensity at maximum position in the case of simplifying
For infinity, although this is inapplicable for practical situation, but it can be seen that what electric field was gradually increased
Change procedure.Then we conclude that, in upper wedge angle 28 position, non-volatile compared to this
Property memory element 200 storage medium 22 in other positions, electric field intensity becomes big, serves
The effect assembled.
Fig. 6 shows the electric field intensity analog result of lower wedge angle 24 position.Fig. 6 A shows me
Intercept the position that the ordinate value in Fig. 2 B is 386.4nm and carry out electric field intensity calculating, such as figure
Shown in Lycoperdon polymorphum Vitt straight line in 6A.Fig. 6 B shows at the Lycoperdon polymorphum Vitt linear position selected by Fig. 6 A
Electric-field intensity distribution.Result shows, in storage medium layer 22, and the distribution non-thread of electric field intensity
Property.When near wedge angle position, electric field intensity is increased dramatically, and on close, electrode position goes out
Existing maximum, strongly reducing afterwards is 0.In the case of simplifying, at maximum position, electric field intensity is
Infinitely great, although this is inapplicable for practical situation, but it can be seen that the change that is gradually increased of electric field
Change process.Then we conclude that, in lower wedge angle 24 position, non-volatile compared to this
Other positions in the storage medium of memory element 200, electric field intensity becomes big, serves gathering
Effect.
Hereinafter, referring to the drawings the manufacture method of non-volatile memory device proposed by the invention is entered
Row explanation.
Fig. 7 to Figure 12 is the major part of the non-volatile memory device 200 representing the present invention
Manufacture method sectional view, this manufacture method is compatible with standard CMOS logic manufacturing process.
First, as it is shown in fig. 7,31 is to block signal icon, the left side of 31 is storage array portion
Point, the right side of 31 is logical gate.For logical gate, metal throuth hole 30 can be with
The contacting metal that bottom transistor connects, it is also possible to be to connect n-th layer and (N+1) layer metal
The via metal of interconnection line.For storage array, 21 is the first electrode.Metal throuth hole 30
Being first medium 20 with the periphery of the first electrode 20, first medium 20 is layer insulation medium, example
As by plasma TEOS or for the effective fluorine-containing oxidation of reduction of parasitic capacitance between wiring
Thing (such as FSG) or low-k material are constituted.
It is introduced first against memory portion.The manufacture process of the first electrode 21 is first to sink
Long-pending one layer of insulating medium layer 20, etches the first electricity by the method for photoetching on insulating medium layer 20
The hole of pole 21, this etching uses dry etching.Use certain process conditions so that carve
Losing the hole is inverted cone, and the area of upper bottom surface is more than bottom surface area.Use afterwards and spatter
Penetrate or other deposition process fill the first electrode 21 metal material, after filling, use chemistry
Mechanical polishing method is processed by shot blasting, obtains structure as shown in Figure 7.For logical gate,
The preparation method of its contacting metal 30 is basic with the preparation method of the first electrode 21 of memory portion
Similar, but to the shape of contacting metal 30 without particular/special requirement.
Then, as shown in Figure 8, use a mask plates, 25 logical gate is hidden with photoresist
Gear, and only the storage array part on the left of 31 is carried out wet etching.Whole silicon chip is placed in DHF
In solution or BHF solution, etch away certain thickness dielectric 20.Etch thicknesses depends on
In the thickness of the storage medium layer 22 of non-volatile memory device, and to ensure certain thickness
The thickness of the second electrode 23.If such as requiring the minimum 20nm of thickness of the second electrode 23, and
The thickness of storage medium layer 22 is 20nm, then the thickness using wet etching to fall to ensure to be more than
40nm.By the structure that obtains after this step as shown in Figure 8, the inverted cone shape of the first electrode 21
Understand some round platform with specific thicknesses and be exposed to the outside of first medium layer 20.
Then, as it is shown in figure 9, deposit storage medium layer 22.The deposition side of storage medium layer 22
Method is different because storage medium is different, multiple for example with sputtering method, technique for atomic layer deposition etc.
Method.The non-volatile memory element of the present invention requires the deposition technique of its storage medium layer 22, must
Need ensure that the covering of storage medium layer 22 has good conformality.I.e. covering at each position
Lid thickness is uniform.
Then, as shown in Figure 10, after having deposited storage medium 22, the second electrode 23 is deposited
Metal material, the thickness of at least 20nm after the upper surface that the thickness of deposition covers the first electrode 21
Degree surplus.Use afterwards the method for chemically mechanical polishing by silicon wafer polishing, storage medium layer 22c
The second electrode 23 metal level that top at least 10nm is thick.For logical gate, remove the second electricity
Pole 23 and storage medium layer 22, use cmp method, with the use of dry etching,
Until spilling upper surface and the first medium layer 20 of the first electrode 21.Can not there is the second electrode 23 He
The residual of storage medium 22.Obtain structure as shown in Figure 10.
Then, as shown in figure 11, for the storage array part on the left of in the of 31, dry etching is first used
Definition memory element, carries out isolated etching by between different memory element.The size of memory element
It is defined the most in this step.This step needs use mask plate and carry out photoetching process.Single
Individual memory element must comprise the first electrode 21, storage medium layer 22 and the second electrode 23, institute
The size stating the first electrode that single memory element is comprised can be the complete horizontal stroke of the first electrode
Cross section, it is also possible to be the partial cross sectional of the first electrode；The storage that described memory element is comprised is situated between
Matter layer 22 can comprise the 22a of the first whole lateral surface of electrode and part 22b and whole 22c,
Can also be the 22a of the portions of lateral side comprising the first electrode and part 22b and part 22c；
The area of the second electrode 23 that described memory element comprises can cover the whole outside of the first electrode
Face, it is also possible to the lateral surface of covering part the first electrode.The shape of cross section of described memory element can
Be circle can also be square.Region etch beyond by the region of defined memory element
After falling, deposit first medium layer 20.The thickness of the first medium layer 20 of deposit is greater than following
Two size sums.First size is the degree of depth of the produced hole of previous step etching；Second
Size is the height of next layer of metal interconnecting wires 26.After deposit first medium layer 20 is complete, right
Whole silicon chip uses cmp method to be polished, and obtains structure as shown in figure 11.
The most as shown in figure 12.Carry out n-th layer metal interconnecting wires deposition and definition, and form the
(N+1) layer metal throuth hole.Illustrate as a example by copper-connection manufacturing process, in the of previous step
Carry out photoetching on one dielectric layer 20, after etching the shape of n-th layer metal interconnecting wires, use electricity
Plating method deposition Cu interconnection line 26.Deposit complete after, be processed by shot blasting.Deposit first afterwards
Dielectric layer 20, thickness should be greater than the height of (N+1) layer metal throuth hole, uses photoetching work afterwards
Skill carries out the definition etching of (N+1) layer metal throuth hole and (N+1) layer metal interconnecting wires,
After etching, use galvanoplastic depositing Cu metal, use chemical mechanical polishing method to carry out afterwards
Polishing.So far, non-volatile memory device 200 manufactures stream with the compatible of standard logic process
Journey is the most complete.Logical gate afterwards is identical with the manufacturing process of storage array part.Shape
The structure becoming Figure 12 is used as the interconnection fabrication processes of aluminum interconnection architecture.
In the non-volatile memory device of the embodiment of the present invention, storage medium layer can annular be enclosed in
Can nature between side and the upper bottom surface, and the first electrode and the second electrode of inverted cone the first electrode
Form two horn structure.When the first and second electrodes apply program voltage respectively, storage medium
In Ceng, the electric field intensity of two sharp corners of close two electrodes is compared to the electricity at sandwich structure
Field intensity is much larger.The existence of horn structure makes electric field intensity at this assemble, and conductive path is at this
Place is formed, the position that can occur with fixed resistance change, and can reduce the operation of memory element
Voltage, beneficially granular and high capacity.
Example above primarily illustrates structure and the manufacturer of the non-volatile memory device of the present invention
Method.Although only some of them embodiments of the present invention being described, but this area being common
Technical staff it is to be appreciated that the present invention can without departing from its spirit with scope in many other
Form is implemented.Therefore, the example shown and embodiment are considered schematic and non-limiting
, in the case of without departing from spirit and scope of the present invention as defined in appended claims,
The present invention may contain various amendments and replacement.
Symbol description:
200: the non-volatile memory device that the present invention proposes；
20,104: first medium layer；
21,107: the first electrode metal layers；
22a, 22b, 22c: storage medium layer；
23,105: the second electrode metal layers；
24: the first angles；
25: photoresist；
26: the 1 layers of metal wiring layer or n-th layer metal wiring layer；
27: the 1st metal throuth hole or (N+1) individual metal throuth hole of logical gate；
28: the second angles；
30: the contacting metal of logical gate or n-th via metal；
31: block signal icon；
100,10: electro-resistance element；
101: substrate；
102: adhesion layer；
103: conductive layer；
106: resistance change layer.
Claims (14)
1. a non-volatile memory device, including:
Inverted cone shape the first electrode；
Storage medium layer, it includes Part I, Part II and Part III, wherein said
A part is attached on the lateral surface of inverted cone shape the first electrode, described Part II and described inverted cone shape
The non-parallel lower end being arranged so that with described Part I of the lateral surface of the first electrode is connected and shape
Become the non-parallel setting of lateral surface of the first angle, described Part III and described inverted cone shape the first electrode
To such an extent as to be connected with the upper end of described Part I and form the second angle；
On second electrode, its first angle being formed at described storage medium layer and the second angle.
2. non-volatile memory device as claimed in claim 1, it is characterised in that described storage
Dielectric layer be selected from aluminium oxide (AlOx), tungsten oxide (WOx), hafnium oxide (HfOx), tantalum oxide (TaOx),
Titanium oxide (TiOx), silicon oxide (SiO2), zinc oxide (ZnOx), nickel oxide (NiOx), germanium
A kind of material in antimony tellurium alloy (GeSbyTex) or the combination of different materials.
3. non-volatile memory device as claimed in claim 1, it is characterised in that described non-easily
The property lost memory element is resistance random storage, and described storage medium layer is resistance-change memory medium
Layer, wherein, described resistive memory medium layer is configured at described first electrode and described two electrodes
Between offset programming signal time, at the first angle of corresponding described storage medium layer and/or the second angle
Substantially location, place forms the conductive filament for storing programming.
4. non-volatile memory device as claimed in claim 1, wherein said first electrode is selected from
By Pt, a kind of material in Ag, Cu, TaN, TiN, Al, W or wherein alloy is formed.
5. non-volatile memory device as claimed in claim 1, wherein said second electrode is selected from
By Pt, a kind of material in Ag, Cu, TaN, TiN, Al, W or wherein alloy is formed.
Non-volatile memory device the most according to claim 1, wherein, described inverted cone shape the first electricity
Pole is formed in first medium layer and shape is exposed in the bigger upper part of inverted cone shape the first electrode
Becoming pylon structure, described Part I, Part II and Part III are covered in this post by conformal
Formed in platform structure, wherein the lateral surface of the upper part of described first electrode of Part I encirclement,
Described Part II is formed at the upper surface of described first medium layer, and described Part III is formed at institute
State on the upper surface of inverted cone shape the first electrode.
Non-volatile memory device the most according to claim 6, wherein, by arranging described back taper
The cone angle size of shape the first electrode arranges described first angle and/or the angular dimension of the second angle.
8. according to the non-volatile memory device of claim 1 or 7, wherein, the angle of described angle
Degree is more than or equal to 60 ° and less than or equal to 80 °.
9. non-volatile memory device as claimed in claim 1, the thickness of wherein said storage medium layer
More than or equal to 10nm and less than or equal to 100nm.
10. non-volatile memory device as claimed in claim 1, wherein said non-volatile memories unit
Part is integrated arranging in the rear end structure of cmos circuit.
The non-volatile memory device of 11. such as claim 10, wherein said inverted cone shape the first electrode
For the metal via structure for connecting interconnection line layer, described second electrode is this interconnection line layer.
The manufacture method of 12. 1 kinds of non-volatile memory devices, it is characterised in that including:
Inverted cone shape the first electrode is formed in first medium layer；
To described first medium layer selective etching so that described inverted cone shape the first electrode bigger upper
End portion exposes formation pylon structure；
Deposit the conformal storage medium layer being covered on this pylon structure and first medium layer, thus
Make that described storage medium layer at least includes being attached on the lateral surface of inverted cone shape the first electrode first
Partly and the Part II of the non-parallel setting of lateral surface of described inverted cone shape the first electrode and the 3rd
Point, described Part I is connected with the lower end of described Part I and is formed the first angle, and described the
A part of and described Part III upper end is connected and forms the second angle；In described storage medium layer
The first angle and the second angle on form the second electrode.
13. manufacture methods as claimed in claim 12, it is characterised in that forming described second
In the step of electrode, including:
Deposit the second electrode material layer；
Described second electrode material layer patterned etch is retained and is attached to outside inverted cone shape the first electrode
Part I on side, the Part II being formed at the upper surface of described first medium layer and formation
Part III on the upper surface of described inverted cone shape the first electrode.
14. manufacture methods as claimed in claim 12, it is characterised in that described manufacture method with
The rear end structure preparation technology of cmos circuit is mutually integrated；
Wherein, described first medium layer is metal interlamination medium layer, and described inverted cone shape the first electrode is
For connecting the metal via structure of interconnection line layer, described second electrode is this interconnection line layer.
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