CN100578753C - Memory element and manufacturing method thereof - Google Patents
Memory element and manufacturing method thereof Download PDFInfo
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- CN100578753C CN100578753C CN200710087797A CN200710087797A CN100578753C CN 100578753 C CN100578753 C CN 100578753C CN 200710087797 A CN200710087797 A CN 200710087797A CN 200710087797 A CN200710087797 A CN 200710087797A CN 100578753 C CN100578753 C CN 100578753C
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- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000010410 layer Substances 0.000 claims description 152
- 238000000034 method Methods 0.000 claims description 49
- 238000010276 construction Methods 0.000 claims description 36
- 239000011229 interlayer Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910010037 TiAlN Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910008599 TiW Inorganic materials 0.000 claims description 4
- 229910004166 TaN Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The invention relates to a memory element. A cylindrical structure comprises a first electrode layer, a dielectric layer on the first electrode layer and a second electrode layer on the dielectric layer. A phase change layer coats around the cylindrical structure. A bottom electrode is electrically connected with the first electrode layer of the cylindrical structure. A top electrode is electrically connected with the second electrode layer of the cylindrical structure.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, relate in particular to a kind of memory component and manufacture method thereof.
Background technology
Ovonics unified memory has competitive characteristics such as speed, power, capacity, reliability, process integration degree and cost, is one to be fit to be used as the stand alone type or the Embedded memory application of higher density.Because the unique advantage of Ovonics unified memory technology, also make it be considered to might replace very much the highly competititve static memory SRAM of present commercialization and dynamic random access memory DRAM volatile memory and flash memory Flash non-volatile memory technologies, be expected to become following potential New Times semiconductor memory.
Phase change memory device is to utilize the difference of Ovonics unified memory material in crystalline state and amorphous resistance value, write, read or erase, for example, fashionable when writing, a short time (for example 50ns) and higher relatively electric current (for example 1mA) can be provided, make phase change layer convert amorphous state to, because the amorphous state phase change layer has higher resistance (for example 105 ohm), it is when reading, and when a voltage was provided, the electric current that obtains was less relatively.In the time will erasing, one long period (for example 100ns) and relatively low electric current (for example 0.2mA) can be provided, make phase change layer convert crystalline state to, because the crystalline state phase change layer has lower resistance (for example 103～104 ohm), it is when reading, and when a voltage is provided, the electric current that obtains is relatively large, in view of the above, can carry out the operation of phase change memory device.
Fig. 1 illustrates the Ovonics unified memory of an existing T type structure, as shown in Figure 1, the phase change memory cell of existing T type structure comprises bottom electrode 102 in regular turn, heating electrode 104, phase change layer 106 and top electrode 108, the heating electrode 104 of column contacts with phase change layer 106, the electric current of Ovonics unified memory is the contact area decision by phase change layer and electrode, the Ovonics unified memory of this existing T type structure is to use the gold-tinted photoetching process to carry out the graphical of phase change layer 106 and heating electrode 104, therefore, the contact area of this kind phase change layer that manufacturing technology forms 106 and electrode 104 is the limit decisions by the gold-tinted photoetching process, can't effectively dwindle the contact area of phase change layer 106 and electrode 104, make the size of phase change memory device further to dwindle.
Fig. 2 illustrates the Ovonics unified memory of existing another structure, as shown in Figure 2, form a horizontal heating electrode 202 on bottom electrode 204 and interlayer dielectric layer 206, afterwards, horizontal heating electrode 202 is carried out a gold-tinted lithography step, and form a phase change layer 208 exposure level heating electrodes 202, then, again phase change layer 208 is carried out the gold-tinted lithography step of other direction, with define storage units, follow-up, form a top electrode 210, electrically connect phase change layer 208.The heating electrode of this kind memory element structure is to adopt to be horizontally disposed with, so, the size of heating electrode is by the film thickness decision that forms heating electrode 202, can not be subjected to the qualification of gold-tinted photoetching process, yet, the phase-transition material of this phase change memory device technology is filling out the hole process deposits, and its reliability that contacts with heating electrode 112, uniformity are all undesirable.
Summary of the invention
In view of this, for addressing the above problem, the invention provides a kind of memory component and its manufacture method, its operating current is also enough low, uses photomask few than prior art, and cost of manufacture is relatively low.
The invention provides a kind of manufacture method of memory component, comprise the following steps.At first, provide a substrate, form one first interlayer dielectric layer in the substrate top.Then, form a bottom electrode in first interlayer dielectric layer, form one first electrode layer on first interlayer dielectric layer and bottom electrode., form a dielectric layer in first electrode layer on, form a second electrode lay on dielectric layer thereafter.Next, graphical first electrode layer, dielectric layer and the second electrode lay, to form a column construction, wherein column construction forms a phase change layer in column construction and substrate corresponding to a memory cell of memory component.Then, graphical phase change layer is separated the graphical phase change layer of memory cell and the graphical phase change layer of adjoining memory cell.Follow-up, form a top electrode, electrically connect the second electrode lay of column construction.
The invention provides a kind of memory component.One column construction comprises that one first electrode layer, is positioned at dielectric layer and on first electrode and is positioned at the second electrode lay on the dielectric layer.One phase change layer coats column construction all around.One bottom electrode electrically connects first electrode layer of column construction.One top electrode electrically connects the second electrode lay of column construction.
Description of drawings
Fig. 1 illustrates the Ovonics unified memory of an existing T type structure;
Fig. 2 illustrates the Ovonics unified memory of existing another structure;
Fig. 3 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 3 B illustrates the profile of Fig. 3 A;
Fig. 4 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 4 B illustrates the profile of Fig. 4 A;
Fig. 5 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 5 B illustrates the profile of Fig. 5 A;
Fig. 6 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 6 B illustrates the profile of Fig. 6 A;
Fig. 7 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 7 B illustrates the profile of Fig. 7 A;
Fig. 8 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 8 B illustrates the profile of Fig. 8 A;
Fig. 9 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Fig. 9 B illustrates the profile of Fig. 9 A;
Fig. 9 C illustrates the top view of a plurality of memory cell of one embodiment of the invention;
Figure 10 A illustrates the top view of the manufacture method intermediate steps of one embodiment of the invention phase change memory device;
Figure 10 B illustrates the profile of Figure 10 A;
Figure 11 illustrates the stereogram of one embodiment of the invention phase change memory device.
The main element symbol description
102～bottom electrode;
104～heating electrode;
106～phase change layer;
108～top electrode;
202～horizontal heating electrode;
204～bottom electrode;
206～interlayer dielectric layer;
208～phase change layer;
210～top electrode;
301～adjoining memory cell;
302～the first interlayer dielectric layers;
303～adjoining memory cell;
304～bottom electrode;
305～adjoining memory cell;
306～the first electrode layers;
307～graphical phase change layer;
308～dielectric layer;
309～graphical phase change layer;
310～the second electrode lay;
311～graphical phase change layer;
312～graphical photoresist layer;
314～column construction;
316～phase change layer;
318～graphical photoresist layer;
320～phase change layer;
330～the second interlayer dielectric layers;
332～top electrode.
Embodiment
Below will describe in detail as reference of the present invention, and example is accompanied by graphic explanation with embodiment.In graphic or description, similar or identical part is used identical Reference numeral.In graphic, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.The part of each element will be it should be noted that the element that does not illustrate among the figure or describe to describe explanation respectively in graphic, can have the form known to various those skilled in the art, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
Fig. 3 A～Figure 10 B discloses the manufacture method of one embodiment of the invention phase change memory device, wherein Fig. 3 A is the top view of Fig. 3 B, at first, please refer to Fig. 3 A and Fig. 3 B, one substrate (not illustrating) is provided, can comprise required element in the substrate, for example grid can be formed with dielectric layer and/or conductive plunger in the substrate, above-mentioned unit or its manufacture method is well known to those skilled in the art, at this,, above-mentioned all unit are not illustrated or describe in detail for succinctly.Then, shown in Fig. 3 A and Fig. 3 B, on dielectric layer and/or conductive plunger, (do not illustrate) and form first interlayer dielectric layer 302 and bottom electrode 304, first interlayer dielectric layer 302 can for example be formed by silica, silicon nitride, silicon oxynitride or dielectric materials, and bottom electrode 304 can be formed by low electrical conductivity materials such as aluminium, copper or tungsten.The method that forms bottom electrode 304 can be with gold-tinted photoetching etching method and form opening in first interlayer dielectric layer 302, inserts conductive layer again to form bottom electrode 304 in opening.In addition, can also an earlier graphical conductive layer to form bottom electrode 304, around bottom electrode 304, deposit first interlayer dielectric layer 302 again, afterwards, etch-back first interlayer dielectric layer 302.
Then, please refer to Fig. 4 A and Fig. 4 B, with for example physical vaporous deposition (physical vapordeposition, below can be called for short PVD) or atomic layer deposition method (Atomic layer deposition, below can be called for short ALD) form one first electrode layer 306 on the bottom electrode 304 and first interlayer dielectric layer 302, first electrode layer 306 can be formed by TiN, TiW or TiAlN, the thickness that it is noted that first electrode layer 306 can not be too thick, its thickness can be 5 dusts～500 dusts, preferably, the thickness of first electrode layer 306 is 100 dusts～300 dusts.Follow-up, with for example Low Pressure Chemical Vapor Deposition (low pressurechemical vapor deposition, below can be called for short LPCVD), aumospheric pressure cvd method (atmosphere pressure chemical vapor deposition, below can be called for short APCVD), subatmospheric chemical vapour deposition technique (sub-atmospheric chemical vapor deposition, below can be called for short SACVD), plasma chemical vapor deposition (plasma enhanced chemical vapordeposition, below can be called for short PECVD) or other deposition techniques one dielectric layer 308 on first electrode layer 306, dielectric layer 308 can be silica, silicon nitride, silicon oxynitride or other materials similar.Then, form a second electrode lay 310 on dielectric layer 308 with for example physical vaporous deposition (PVD) or atomic layer deposition method (ALD), the second electrode lay 310 can be formed by TiN, TiW, TiAl, TaN or TiAlN, in the preferred embodiment of the present invention, the thickness of the second electrode lay 310 is thick than the thickness of first electrode layer 306, for example the thickness of twice to three times at least is 100 dusts～3000 dusts on the thickness preferred general of the second electrode lay.
Then, please refer to Fig. 5 A and Fig. 5 B, form a photoresist layer (not illustrating) on the second electrode lay 310 with for example method of spin coating, then, carry out a gold-tinted lithography step, definition photoresist layer forms graphical photoresist layer 312, makes the photoresist layer form the predetermined pattern that forms.Follow-up, please refer to Fig. 6 A and Fig. 6 B, is mask with graphical photoresist layer 312, carries out an anisotropic etching process, etching the second electrode lay 310, dielectric layer 308 and first electrode layer 306 in regular turn have closed-loop around all around column construction 314 to form one.Then, remove graphical photoresist layer 312, in this preferred embodiment, this structure 314 illustrates and is cylindrical structural 314, but the invention is not restricted to this, this structure can be any closed geometry figure, for example elliptical cylinder-shape structure, square structure or the like, and this has closed-loop around all around column construction 314 memory cell corresponding to memory component of the present invention.
Next, please refer to Fig. 7 A and Fig. 7 B, with for example physical vaporous deposition (PVD) or atomic layer deposition method (ALD), form a phase change layer 316 on the top and sidewall of first interlayer dielectric layer 302 and above-mentioned column construction 314, phase change layer 316 can be Ag, In, Te, Sb or its combination, or Ge, Te, Sb or its combination form, and in the preferred embodiment of the present invention, phase change layer 316 is Ag
xIn
yTe
zSb
wOr Ge
xTe
ySb
wAlloy, in addition, the thickness of phase change layer 316 is preferably approximately greater than 500 dusts, it is noted that at this, phase change layer 316 directly contact column construction 314 around around, particularly, first electrode layer 306 that phase change layer 316 directly contacts column construction 314 is all around.
Follow-up, please refer to Fig. 8 A and Fig. 8 B, form a photoresist layer (not illustrating) on phase change layer 316 with for example method of spin coating, then, carry out a gold-tinted lithography step, definition photoresist layer is to form graphical photoresist layer 318.Then, please refer to Fig. 9 A and Fig. 9 B, is mask with graphical photoresist layer 318, etching phase change layer 316, the graphical phase change layer 320 of this memory cell 300 and the graphical phase change layer 307,309,311 of adjoining memory cell 301,303,305 are separated, shown in Fig. 9 C.
Next, please refer to Figure 10 A and Figure 10 B, with for example chemical vapour deposition technique, form one second interlayer dielectric layer 330 and cover the phase change layer 316 and first interlayer dielectric layer 302, second interlayer dielectric layer 330 can be silica, silicon nitride or silicon oxynitride, follow-up through the chemico-mechanical polishing planarization, next, graphical second interlayer dielectric layer 330 and phase change layer 316 are to form an opening (not illustrating), expose the second electrode lay 310, next, deposition one Al for example, Cu or the conductive layer of W and are inserted in the opening on second interlayer dielectric layer 330, to form top electrode 332, electrically connect the second electrode lay 310 of column construction 314.
Figure 11 is the stereogram of one embodiment of the invention phase change memory cell, as shown in the figure, among this embodiment, the memory cell main body is one to comprise the column construction 314 of first electrode layer 306, dielectric layer 308 and the second electrode lay 310, and this column construction 314 is coated by a graphical phase change layer 320, in addition, first electrode layer 306 of column construction 314 and the second electrode lay 310 are to electrically connect a bottom electrode 304 and a top electrode 332 respectively.
According to the abovementioned embodiments of the present invention, because the thickness of first electrode layer 306 of column construction 314 is thin many than the second electrode lay 310, so, its impedance is bigger, and therefore, the heat energy major part that electric current passes through to be sent distributes around first electrode layer 306.If column construction 314 is one cylindrical, the contact-making surface of its first electrode layer 306 (heating electrode) and phase change layer 320 is a horizontal ring-type (ring), and if the diameter of cylindrical structural 314 is cd, thickness is t, then the contact area of its heating electrode and phase change layer 320 is A=cd * π * t, not limited by the gold-tinted photoetching process.In addition, this technology of the present invention only uses gold-tinted photoetching process promptly to determine the contact area of heating electrode and phase change layer 320, can reduce parameter or influence that many one photoetching processes are produced, in addition, the above embodiment of the present invention is after forming phase change layer 320, phase change layer 320 is not carried out extra special process processing in heating phase change district (i.e. 316 and 320 contact zones), modify its profile, can avoid the composition of phase change layer 320 to change, again in addition, the present invention forms the method for heating electrode (first electrode layer 306), for it being deposited on the plane, can be easier to control the thickness of heating electrode.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (26)
1. the manufacture method of a memory component comprises:
Substrate is provided;
Form first interlayer dielectric layer in this substrate top;
Form bottom electrode in this first interlayer dielectric layer;
Form first electrode layer on this first interlayer dielectric layer and this bottom electrode;
Form dielectric layer on this first electrode layer;
Form the second electrode lay on this dielectric layer;
Graphical this first electrode layer, this dielectric layer and this second electrode lay, forming column construction, this column construction have around around, wherein this column construction is corresponding to the memory cell of this memory component;
Form phase change layer in this column construction and this substrate, this phase change layer directly contact this column construction around around;
Graphical this phase change layer is separated the graphical phase change layer of this memory cell and the graphical phase change layer of adjoining memory cell; And
Form top electrode, electrically connect the second electrode lay of this column construction.
2. the manufacture method of memory component as claimed in claim 1, wherein this phase change layer directly contact this column construction first electrode layer all around.
3. the manufacture method of memory component as claimed in claim 1, wherein this column construction is cylindrical.
4. the manufacture method of memory component as claimed in claim 3, wherein the contact-making surface of this first electrode layer and this phase change layer is a ring-type.
5. the manufacture method of memory component as claimed in claim 1, wherein the thickness of this phase change layer is greater than 500 dusts.
6. the manufacture method of memory component as claimed in claim 1, wherein the thickness of this first electrode layer is than the thin thickness of this second electrode lay.
7. the manufacture method of memory component as claimed in claim 1, wherein the thickness of this first electrode layer is 5 dusts～500 dusts.
8. the manufacture method of memory component as claimed in claim 7, wherein the thickness of this first electrode layer is 100 dusts～300 dusts.
9. the manufacture method of memory component as claimed in claim 1, wherein this first electrode layer is formed by TiN, TiW or TiAIN.
10. the manufacture method of memory component as claimed in claim 1, wherein this second electrode lay is formed by TiN, TiW, TiAl, TaN or TiAlN.
11. the manufacture method of memory component as claimed in claim 1, wherein this phase change layer comprises Ag, In, Te, Sb or its combination and Ge, Te, Sb or its combination.
12. the manufacture method of memory component as claimed in claim 1, wherein this dielectric layer is formed by silica, silicon nitride or silicon oxynitride.
13. the manufacture method of memory component as claimed in claim 1, wherein power on very Al, Cu or W of this bottom electrode and this forms.
14. a memory component comprises:
Column construction comprises first electrode layer, is positioned at the dielectric layer on this first electrode, and is positioned at the second electrode lay on this dielectric layer, this column construction have around around;
Phase change layer coats this column construction all around, this phase change layer directly contact this column construction around around;
Bottom electrode electrically connects first electrode layer of this column construction; And
Top electrode electrically connects the second electrode lay of this column construction.
15. memory component as claimed in claim 14, wherein this phase change layer directly contact this column construction first electrode layer all around.
16. memory component as claimed in claim 14, wherein this column construction is cylindrical.
17. memory component as claimed in claim 16, wherein the contact-making surface of this first electrode layer and this phase change layer is a ring-type.
18. memory component as claimed in claim 14, wherein the thickness of this phase change layer is greater than 500 dusts.
19. memory component as claimed in claim 14, wherein the thickness of this first electrode layer is than the thin thickness of this second electrode lay.
20. memory component as claimed in claim 14, wherein the thickness of this first electrode layer is 5 dusts～500 dusts.
21. memory component as claimed in claim 20, wherein the thickness of this second electrode lay is 100 dusts～3000 dusts.
22. memory component as claimed in claim 14, wherein this first electrode layer is formed by TiN, TiW or TiAlN.
23. memory component as claimed in claim 14, wherein this second electrode lay is formed by TiN, TiW, TiAl, TaN or TiAlN.
24. memory component as claimed in claim 14, wherein this phase change layer comprises Ag, In, Te, Sb or its combination and Ge, Te, Sb or its combination.
25. memory component as claimed in claim 14, wherein this dielectric layer is formed by silica, silicon nitride or silicon oxynitride.
26. memory component as claimed in claim 14, wherein power on very Al, Cu or W of this bottom electrode and this forms.
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| CN200710087797A CN100578753C (en) | 2007-03-19 | 2007-03-19 | Memory element and manufacturing method thereof |
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| CN200710087797A CN100578753C (en) | 2007-03-19 | 2007-03-19 | Memory element and manufacturing method thereof |
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| CN100578753C true CN100578753C (en) | 2010-01-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
| TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
| TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
| CN103427022B (en) * | 2013-08-22 | 2016-07-06 | 中国科学院上海微系统与信息技术研究所 | The preparation method comprising the phase change storage structure of sandwich type electrode |
| CN105226181A (en) * | 2015-09-01 | 2016-01-06 | 宁波时代全芯科技有限公司 | Phase-change memory and manufacture method thereof |
| CN105428525B (en) * | 2015-11-06 | 2018-03-02 | 江苏时代全芯存储科技有限公司 | Phase change memory and manufacturing method thereof |
| CN105428529B (en) * | 2015-12-16 | 2018-04-13 | 江苏时代全芯存储科技有限公司 | The manufacture method of phase-change memory |
| CN105428533B (en) * | 2015-12-24 | 2018-05-15 | 江苏时代全芯存储科技有限公司 | The manufacture method of phase-change memory |
| CN108550696B (en) * | 2016-03-08 | 2022-02-25 | 江苏时代全芯存储科技股份有限公司 | Phase change memory |
| CN108520879B (en) * | 2018-06-12 | 2020-09-29 | 湘潭大学 | High-density ferroelectric memory unit |
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