TWI824627B - Semiconductor integrated circuit component and manufacturing method thereof - Google Patents

Abstract

This case discloses a semiconductor integrated circuit element and a manufacturing method thereof. The semiconductor integrated circuit element covers the outside of the bump structure with a resistive switching layer. Because the layer will not be damaged by the etching process during its preparation, it avoids The possibility exists that strong, single conductive filaments formed by the etching process may be destroyed during electrical manipulation. In addition, the semiconductor integrated circuit component adds a thermal insulation layer (TEL) that fully covers the component, making it easier for the component to form multiple weakly conductive filaments, thereby achieving the purpose of adjusting pulses to control continuous changes in conductance, which can be better used as an analog type memory, used in CIM and other scenarios.

Description

Semiconductor integrated circuit component and manufacturing method thereof

Cross-references to related applications:

This case is based on a Chinese patent application with application number 202111388509.4 and a filing date of November 22, 2021, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this case as a reference.

This case involves the field of semiconductor components, especially a resistive random access memory (RRAM) and its manufacturing method.

The basic structure of RRAM includes a resistive switching layer and electrodes located on both sides of the resistive switching layer. Among them, the resistive variable layer is mostly made of various oxide film materials, such as transition metal oxides (TMO). Under the action of an external voltage, the resistance state of the resistive variable layer can be changed between a high resistance state and a low resistance state. Transition, and the transition between different resistance states is mainly achieved through the formation and breakage of conductive filaments.

Due to its advantages such as low power consumption, simple structure, and fast erasing and writing speed, RRAM can not only occupy a place in the field of digital memory as a new type of non-volatile memory, but can also realize an analog type with bidirectionally adjustable conductance. ) memory can realize Computing In Memory (CIM, Computing In Memory) through simple multiplication and addition operations, and has huge application potential in the field of artificial neural networks.

Different from digital RRAM, analog RRAM applies continuous electrical pulses to the components to cause continuous multi-level changes in conductance. In particular, conductance jumps are not expected during the SET and RESET processes. Therefore, when RRAM is required to generate conductive filaments, it is best to generate multiple weakly conductive filaments with a relatively uniform distribution.

However, in the mainstream RRAM implementation process, when defining the RRAM cell size, the edge portion of the RRAM resistive layer is damaged by the etching process, causing conductive filaments to be more easily distributed on the edge portion of the RRAM. If there is too much damage to the edge of the resistive layer, strong conductive filaments can easily form at the edge. In this case, the formation and disconnection of filaments can lead to jump conditions in conductance, which cannot meet the requirements of analog memory well, resulting in poor CIM performance.

In view of the above technical problems, the applicant creatively provides a semiconductor integrated circuit element and a preparation method thereof.

According to a first aspect of the embodiment of this case, a semiconductor integrated circuit element is provided. The semiconductor integrated circuit element includes: a bump structure, the bump structure is provided with a dielectric layer in the horizontal direction; a first thermal enhancement layer (Thermal Enhance Layer, TEL), located below the bump structure; a resistive switching layer, covering the top and outside of the side walls of the bump structure; a second thermal insulation layer, covering the top and outside of the side walls of the resistive switching layer, formed together with the first thermal insulation layer Full coverage of the resistive layer and bump structure.

In an implementation, the bump structure further includes: an oxygen storage layer (Oxygen Ion Reservoir, OIR), located below the dielectric layer.

In an embodiment, the semiconductor integrated circuit element further includes a first metal layer and a second metal layer, the first metal layer is connected to the first thermal insulation layer, and the second metal layer is connected to the second thermal insulation layer.

In an embodiment, the first thermal insulation layer is located inside the resistive layer. Correspondingly, the first metal layer is connected to the first thermal insulation layer, including: the first metal layer is connected to the first thermal insulation layer through a through hole (Via). Thermal insulation connection.

In an implementation, the first thermal insulation layer is located inside the resistive layer, and accordingly, the first metal layer is connected to the first thermal insulation layer, including: the first metal layer is directly connected to the first thermal insulation layer.

In an implementation manner, the material of the thermal insulation layer includes tantalum nitride (TaN).

According to a second aspect of the embodiment of the present application, a method for manufacturing a semiconductor integrated circuit element is provided. The method includes: obtaining a substrate with a first metal layer; forming a first thermal insulation layer on the first metal layer; A bump structure with a dielectric layer arranged in the horizontal direction is formed on a thermal insulation layer; a resistive switching layer is formed above the bump structure, so that the resistive switching layer covers the top and side walls of the bump structure; on the resistive switching layer A second thermal insulation layer is formed above, so that the second thermal insulation layer covers the top and outside of the side wall of the resistive switching layer; the bump structure covered with the resistive switching layer and the second thermal insulation layer is partitioned so that the partition occurs on the bump. The flat area on the periphery of a block structure.

In an embodiment, after performing isolation treatment on the bump structure covered with the resistive change layer and the second thermal insulation layer, the method further includes: insulating the bump structure covered with the resistive change layer and the second thermal insulation layer A second metal layer is manufactured on top and connected to the second thermal insulation layer.

In an implementation, forming the first thermal insulation layer on the first metal layer includes: forming a through hole on the first metal layer; and forming the first thermal insulation layer on the through hole.

In an embodiment, the material of the thermal insulation layer includes tantalum nitride (TaN). Accordingly, the process of forming the thermal insulation layer includes: physical vapor deposition process (PVD), chemical vapor deposition process (CVD), or Atomic layer deposition process (ALD).

The embodiment of this case is a semiconductor integrated circuit element and its manufacturing method. The semiconductor integrated circuit element covers the outside of the bump structure with a resistive switching layer. Because this layer will not be damaged by the etching process during its manufacturing process, The possibility of strong, single conductive filaments being damaged by the etching process during electrical operations is avoided. In addition, the semiconductor integrated circuit component adds a thermal insulation layer that fully covers the component, making it easier for the component to form multiple weak conductive filaments, thereby achieving the purpose of continuously controlling the continuous change of conductance through pulses, and thus can better serve as an analog memory body, used in CIM and other scenarios.

It should be understood that the implementation of the embodiments of this case does not need to achieve all the above beneficial effects, but specific technical solutions can achieve specific technical effects, and other implementations of the embodiments of this case can also achieve benefits not mentioned above. Effect.

In order to make the purpose, features, and advantages of this case more obvious and easy to understand, the technical solutions in the embodiments of this case will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this case. Obviously, the described embodiments These are only some of the embodiments of this case, not all of them. Based on the embodiments in this case, all other embodiments obtained by those with ordinary knowledge in the field to which the present invention belongs without any creative work fall within the scope of protection of this case.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the present application. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, a person of ordinary skill in the art to which the present invention pertains may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples unless they are inconsistent with each other.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of this case, "plurality" means two or more, unless otherwise explicitly and specifically limited.

Figure 1 shows a schematic structural cross-sectional view of an embodiment of the semiconductor integrated circuit device of the present invention. As shown in Figure 1, the semiconductor integrated circuit element includes: a bump structure, which is provided with a dielectric layer 107 in the horizontal direction; a first thermal insulation layer 105 (Thermal Enhance Layer, TEL), located on the bump structure Below; the resistive switching layer 108 covers the top and side walls of the bump structure; the second thermal insulation layer 109 covers the top and side walls of the resistive switching layer 108 and together with the first thermal insulation layer 105 forms a pair of resistive switching layers. 108 and full coverage of bump construction.

The bump structure is provided with a dielectric layer 107 in the horizontal direction; a resistive switching layer 108 covering the top and outside of the side walls of the bump structure; a second thermal insulation layer 109 covering the top and outside of the side walls of the resisting switching layer 108; a first The thermal insulation layer 105 is located below the bump structure, and together with the second thermal insulation layer 109 forms a full coverage of the resistive layer 108 and the bump structure.

In this embodiment, the bump structure includes a dielectric layer 107 and an oxygen storage layer 106 . The bump structure may be an inverted trapezoid, a cuboid, a cube, etc. Because the raised portion of the bump structure has a certain height, the resistive switching material can be deposited outside the side walls of the bump structure to obtain an upright resistive switching layer (the resistive switching layer 108 covers the portion outside the side walls of the bump structure). During the subsequent etching operation, the resistive switching layer located on the flat part of the periphery of the bump structure can be etched, while the resistive switching layer covering the top and side walls of the bump structure remains intact, so that it will not be affected by the etching. The damage caused by corrosion forms strong conductive filaments in the resistive layer.

As shown in Figure 1, the resistive layer portion on the top and outside the sidewall of the bump structure will form a corner, and usually strong conductive filaments will be formed in the corner portion. To this end, in this embodiment, a dielectric layer 107 is provided in the bump structure and positioned in a horizontal direction.

In this way, the dielectric layer 107 can form an isolation between the resistive switching layer at the corner portion and the bottom electrode, so that strong conductive filaments will not be formed in the resistive switching layer at the corner portion.

The material of the dielectric layer 107 may be silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

In addition, in this embodiment, an oxygen storage layer 106 is also provided in the bump structure. The oxygen storage layer 106 is located below the dielectric layer 107 and is used to attract or store more oxygen to make the formation of conductive filaments easier and more stable. Commonly used materials for the oxygen storage layer 106 include at least one of titanium (Ti), hafnium (Hf), and zirconium (Zr).

It should be noted that the oxygen storage layer 106 is provided to improve the effect of forming conductive filaments, but it is not necessary, and the oxygen storage layer 106 may not be provided.

As shown in Figure 1, the resistive switching layer 108 covers the top and sidewalls of the bump structure, and any suitable resistive switching material can be used, such as aluminum oxide (AlO), copper oxide (CuO), hafnium oxide (HfO), One or more resistive materials such as molybdenum oxide (MoO), nickel oxide (NiO), tantalum oxide (TaO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO) and tungsten oxide (WO) .

As shown in Figure 1, the top and side walls of the resistive layer 108 are also covered with a second thermal insulation layer 109; and a first thermal insulation layer 105 is also provided below the bump structure.

In the embodiment shown in Figure 1, the first thermal insulation layer 105 and the dielectric layer 107 in the bump structure form a top-down superimposed structure, and are located inside the resistive layer 108 and opposite to the second thermal insulation layer 109. Full coverage of resistive layer 108 and bump structure.

Since increasing the temperature can make the formation of conductive filaments easier, the full coverage of the resistive layer 108 and the bump structure can not only achieve a better thermal insulation effect, but also make the temperature distribution in the resistive layer 108 more uniform. . As a result, multiple weakly conductive filaments can be formed, and it is easy to control the continuous changes in conductance through pulses.

Among them, commonly used thermal insulation layer materials include: tantalum nitride (TaN) and/or titanium nitride (TiN), etc. Among them, tantalum nitride (TaN) has lower thermal conductivity and better thermal insulation effect.

In addition, in the embodiment shown in Figure 1, it also includes a second metal layer 111 and a first metal layer 101. The second metal layer 111 is connected to the second thermal insulation layer 109; the first metal layer 101 passes through a through hole. 104 is connected to the first thermal insulation layer 105 .

The second metal layer 111 and the first metal layer 101 can be any suitable metal material, including aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), One or more of materials such as tantalum (Ta), titanium nitride (TiN), titanium (Ti), tungsten (W) and tungsten nitride (WN).

In this way, by applying a voltage to the second metal layer 111 or the first metal layer 101, a plurality of weak conductive filaments can be formed in the erected part of the resistive layer 108, so that it can be used as an analog memory to achieve better performance. CIM performance.

Figure 2 shows a schematic structural cross-sectional view of another embodiment of the semiconductor integrated circuit element of the present invention. As shown in Figure 2, the semiconductor integrated circuit element includes: a bump structure, which is provided with a dielectric layer 207 in the horizontal direction; a first thermal insulation layer 205, located below the bump structure; a resistive layer 208 , covering the top and outside of the side walls of the bump structure; the second thermal insulation layer 209 covers the top and outside of the side walls of the resistive change layer 208, and together with the first thermal insulation layer 205, form a barrier to the resistive change layer 208 and the bump structure. Full coverage.

Similar to the embodiment shown in FIG. 1 , in the bump structure in the embodiment shown in FIG. 2 , in addition to the dielectric layer 207 , an oxygen storage layer 206 is also provided.

In addition, in the embodiment shown in Figure 2, it also includes a second metal layer 211 and a first metal layer 201. The second metal layer 211 is connected to the second thermal insulation layer 209; the first metal layer 201 is directly connected to the first metal layer 209. The thermal insulation layer 205 is connected.

However, in the embodiment shown in FIG. 2 , the first thermal insulation layer 205 is located below the resistive layer 208 and is directly connected to the first metal layer 201 instead of the through hole.

Using this structure, the first thermal insulation layer 205 can also work with the second thermal insulation layer 209 to form full coverage of the resistive layer 208 and the bump structure, and because the first thermal insulation layer 205 replaces the through hole, it is directly connected to the first thermal insulation layer 205 . The metal layer 201 is connected, which can further eliminate the step of manufacturing through holes and make the height of the entire semiconductor component lower, which can better meet the requirements of miniaturization.

In the embodiments shown in Figures 1 and 2, the resistive switching layer covers the top and side walls of the bump structure. Since the dielectric layer disposed horizontally in the bump structure covers the top of the bump structure, Electrical isolation is formed between the resistive variable layer part and the top electrode. The conductive filaments are mainly formed in the resistive variable layer part covering the side walls of the bump structure. This part of the resistive variable layer is formed by deposition and will not be affected by subsequent The etching process is damaged. Therefore, strong conductive filaments are not formed within the resistive layer.

Since the second thermal insulation layer covers the top and side walls of the resistive switching layer, the first thermal insulation layer is located below the bump structure, forming full coverage of the resistive switching layer and the bump structure. After being energized, the temperature of the resistive layer can be made higher and the temperature distribution more uniform, which makes it easier to form multiple weak conductive filaments, thereby achieving the purpose of continuously controlling the continuous change of conductance through pulses, and thus can be better used as a Analog memory is used in scenarios such as CIM.

This case also provides a method for manufacturing semiconductor integrated circuit components. As shown in Figure 3, the method includes: step S310, obtaining a substrate with a first metal layer; step S320, forming a first metal layer on the first metal layer. Thermal insulation layer; Step S330, form a bump structure with a dielectric layer in the horizontal direction on the first thermal insulation layer; Step S340, form a resistive switching layer above the bump structure, so that the resistive switching layer covers the bumps The top of the structure and the outside of the side walls; Step S350, form a second thermal insulation layer above the resistive switching layer, so that the second thermal insulation layer covers the top of the resistive switching layer and the outside of the side walls; Step S360, form the resistive switching layer and the outside of the side wall. The bump structure of the second thermal insulation layer is partitioned so that the partition occurs at a flat area on the periphery of the bump structure to ensure that the resistive layer and the second thermal insulation layer outside the side walls of the bump structure are intact.

In step S310, a substrate with a first metal layer is provided. This component mainly provides the first metal layer for energizing and applying voltage to the semiconductor integrated circuit component of the embodiment of the present case, and the semiconductor integrated circuit component of the embodiment of the present case is manufactured on it. body circuit components.

To manufacture the substrate with the first metal layer, any applicable existing preparation method can be used.

In step S320, when forming the first thermal insulation layer on the first metal layer, any suitable deposition process may be used to deposit any suitable thermal insulation layer material on the first metal layer. Among them, commonly used deposition processes include: chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

Among them, the selected deposition process usually depends on the selected thermal insulation layer material. For example, if tantalum nitride (TaN) is selected as the thermal insulation layer material, it is more suitable to use a physical deposition process or an atomic layer deposition process.

In step S330, the process of forming the bump structure usually includes: depositing each designed functional layer in the bump layer by layer, such as an oxygen storage layer and a dielectric layer; and then performing photolithography and then etching to obtain the designed bump structure. .

In step S340, the process of forming the resistive variable layer mainly includes depositing any applicable resistive variable layer material using any applicable deposition process.

In step S350, the process of forming the second thermal insulation layer mainly includes depositing any applicable thermal insulation layer material using any applicable deposition process.

In step S360, the process of performing the isolation process is usually photolithography and then etching. It is particularly important to note that when performing the isolation process, the isolation must occur at a flat place on the periphery of the bump structure to ensure the barrier outside the side walls of the bump structure. The variable layer and the second thermal insulation layer remain intact and form a partition between the storage units to avoid short circuits.

After that, a second metal layer can be fabricated on the bump structure covered with the resistive layer and the second thermal insulation layer to connect with the second thermal insulation layer. This process can also adopt any applicable existing process, so it will not be described again here.

Figure 4 shows the main process of manufacturing the semiconductor integrated circuit component shown in Figure 1, including:

Step S4010, obtain the substrate 102 with the first metal layer 101, and deposit an intermetal dielectric (IMD) material on it to form the dielectric layer 103;

The material of the first metal layer 101 may be aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), titanium ( One or more of materials such as Ti), tungsten (W) and tungsten nitride (WN).

The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

Step S4020, use an etching process to etch the dielectric layer 103 of the substrate to obtain a through hole 104, and deposit a metal material in the through hole 104 to obtain a structure as shown in Figure 5;

Among them, the metal material can be aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), titanium (Ti), One or more materials such as tungsten (W) and tungsten nitride (WN).

Step S4030, deposit the first thermal insulation layer 105, the oxygen storage layer 106 and the dielectric layer 107 to obtain the structure shown in Figure 6;

Among them, the material of the first thermal insulation layer 105 can be tantalum nitride (TaN), titanium nitride (TiN), etc.;

The material of the oxygen storage layer 106 may be at least one of titanium (Ti), hafnium (Hf) and zirconium (Zr);

The material of the dielectric layer 107 may be silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

Step S4040, perform photolithography and then etching on the first thermal insulation layer 105, the oxygen storage layer 106 and the dielectric layer 107 to obtain the structure shown in Figure 7;

Step S4050, deposit the resistive layer material 108 to obtain the structure shown in Figure 8;

The material of the resistive layer 108 may be aluminum oxide (AlO), copper oxide (CuO), hafnium oxide (HfO), molybdenum oxide (MoO), nickel oxide (NiO), tantalum oxide (TaO), titanium oxide (TiO), One or more resistive materials such as zinc oxide (ZnO), zirconium oxide (ZrO), and tungsten oxide (WO).

Step S4060, deposit the second thermal insulation layer 109 to obtain the structure shown in Figure 9;

The material of the second thermal insulation layer 109 may be low thermal conductivity materials such as tantalum nitride (TaN) and/or titanium nitride (TiN);

Step S4070, deposit the metal interlayer dielectric 110 to obtain the structure shown in Figure 10;

The material of the inter-metal dielectric 110 may be an existing commonly used dielectric material, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

Step S4080: Polish the inter-metal dielectric 110 to obtain the structure shown in Figure 11;

The grinding process can use chemical-mechanical polishing (CMP);

Step S4090: Cut off the flat portion of the first thermal insulation layer 109 located on the periphery of the bump structure through a photolithography and then etching process to obtain the structure shown in Figure 12;

Step S4100, deposit the metal interlayer dielectric 110 to obtain the structure shown in Figure 13;

The material of the inter-metal dielectric 110 may be an existing commonly used dielectric material, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

Step S4110: Polish the inter-metal dielectric 110 to obtain the structure shown in Figure 14;

The grinding process can use chemical-mechanical polishing (CMP);

Step S4120: deposit the second metal layer 111 to obtain the semiconductor integrated circuit component of the embodiment shown in Figure 1.

The material of the second metal layer 111 may be aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), One or more of materials such as titanium (Ti), tungsten (W) and tungsten nitride (WN).

Figure 15 shows the main process of manufacturing the semiconductor integrated circuit component shown in Figure 2, including:

Step S5010, obtain the substrate 202 with the first metal layer 201, and deposit the first thermal insulation layer 205 material on it to obtain the structure shown in Figure 16;

The material of the first metal layer 201 may be aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), titanium ( One or more of materials such as Ti), tungsten (W) and tungsten nitride (WN).

The material of the first thermal insulation layer 205 may be low thermal conductivity materials such as tantalum nitride (TaN) and/or titanium nitride (TiN).

Step S5020, perform photolithography and then etching on the first thermal insulation layer 205 to obtain the structure shown in Figure 17;

Step S5030, deposit the metal interlayer dielectric 202 to obtain the structure shown in Figure 18;

The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

Step S5040, deposit the oxygen storage layer 206 and the dielectric layer 207 to obtain the structure shown in Figure 19;

The material of the oxygen storage layer 206 may be at least one of titanium (Ti), hafnium (Hf) and zirconium (Zr);

The material of the dielectric layer 207 may be silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

Step S5050, perform photolithography and then etching on the oxygen storage layer 206 and the dielectric layer 207 to obtain the structure shown in Figure 20;

Step S5060, deposit the resistive layer 208 material to obtain the structure shown in Figure 21;

The material of the resistive layer 208 may be aluminum oxide (AlO), copper oxide (CuO), hafnium oxide (HfO), molybdenum oxide (MoO), nickel oxide (NiO), tantalum oxide (TaO), titanium oxide (TiO), One or more resistive materials such as zinc oxide (ZnO), zirconium oxide (ZrO), and tungsten oxide (WO).

Step S5070, deposit the second thermal insulation layer 209 to obtain the structure shown in Figure 22;

The material of the second thermal insulation layer 209 may be low thermal conductivity materials such as tantalum nitride (TaN) and/or titanium nitride (TiN);

Step S5080, deposit the metal interlayer dielectric 202 to obtain the structure shown in Figure 23;

The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

Step S5090: Polish the inter-metal medium 202 to obtain the structure shown in Figure 24;

The grinding process can use chemical-mechanical polishing (CMP);

Step S5100, through a photolithography and then etching process, isolate the portion of the second thermal insulation layer 209 located between the bump structures to obtain the structure shown in Figure 25;

Step S5110, deposit the metal interlayer dielectric 202 to obtain the structure shown in Figure 26;

The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO ₂ ), silicon nitride (SiN) and other insulating metal oxides or nitrides.

Step S5120: Polish the inter-metal dielectric 202 to obtain the structure shown in Figure 27;

The grinding process can use chemical-mechanical polishing (CMP);

Step S5130: deposit the second metal layer 211 to obtain the semiconductor integrated circuit component of the embodiment shown in Figure 2.

The material of the second metal layer 211 may be aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), One or more of materials such as titanium (Ti), tungsten (W) and tungsten nitride (WN).

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

In the several embodiments provided in this case, it should be understood that the disclosed components and methods can be implemented in other ways. The component embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined or integrated into Another device, or some features can be ignored, or not implemented. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be electrical, mechanical, or other forms. of.

The above are only specific implementations of this case, but the scope of protection of this case is not limited thereto. Anyone who is familiar with the field and has ordinary knowledge in the field to which the present invention belongs can easily think of changes or substitutions within the technical scope disclosed in this case, and they should all be covered. within the scope of protection in this case. Therefore, the scope of protection in this case should be based on the scope of protection of the patent application.

101: First metal layer 102:Substrate 103: Dielectric layer 104:Through hole 105: First thermal insulation layer 106:Oxygen storage layer 107:Media layer 108: Resistive layer 109: Second thermal insulation layer 110:Metal interlayer medium 111: Second metal layer 201: First metal layer 202:Metal interlayer medium 205:First thermal insulation layer 206:Oxygen storage layer 207:Media layer 208: Resistive layer 209: Second thermal insulation layer 211: Second metal layer S310～S360: steps S4010～S4120: steps S5010～S5130: steps

The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the case are shown in an illustrative and non-limiting manner, in which: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts. Figure 1 shows a schematic structural cross-sectional view of an embodiment of the semiconductor integrated circuit component of the present invention; Figure 2 shows a schematic structural cross-sectional view of another embodiment of the semiconductor integrated circuit component of the present invention; Figure 3 shows a schematic diagram of the manufacturing process of a semiconductor integrated circuit component according to an embodiment of the present invention; Figure 4 shows a schematic diagram of the manufacturing process of the embodiment shown in Figure 1; Figure 5 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 6 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 7 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 8 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 9 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 10 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 11 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 12 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 13 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 14 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 15 shows a schematic diagram of the manufacturing process of the embodiment shown in Figure 2; Figure 16 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 17 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 18 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 19 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 20 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 21 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 22 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 23 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 24 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 25 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 26 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 27 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2 .

101: First metal layer

102:Substrate

103: Dielectric layer

104:Through hole

105: First thermal insulation layer

106:Oxygen storage layer

107:Media layer

108: Resistive layer

109: Second thermal insulation layer

110:Metal interlayer medium

111: Second metal layer

Claims (10)

A semiconductor integrated circuit component, which includes: a bump structure, the bump structure is provided with a dielectric layer in a horizontal direction; a first thermal insulation layer located below the bump structure; a resistive layer covering the A top and the outside of one side wall of the bump structure; a second thermal insulation layer covering a top and the outside of one side wall of the resistive change layer, and together with the first thermal insulation layer, form a pair of the resistive change layer and the bump. Full coverage of the block structure; wherein, the first thermal insulation layer and the dielectric layer in the bump structure form an upper and lower superposition structure, and are located inside the resistive variable layer; the top part of the resistive variable layer covers the bump structure The top part of the resistive variable layer covers the bump structure and the outside of the side wall of the first thermal insulation layer. The bottom end of the vertical part of the resistive variable layer extends in a direction away from the bump structure to form a horizontal part. , the lower surface of the bottom end of the vertical part of the resistive layer and the lower surface of the horizontal part are flush with the lower surface of the first thermal insulation layer; the second thermal insulation layer covers the top part of the resistive layer, vertical The outer part of the part and the upper surface of the horizontal part; alternatively, the first thermal insulation layer is located below the resistive switch layer, and the dielectric layer in the bump structure is located inside the resistive switch layer; the top part of the resistive switch layer Covering the top of the bump structure, the vertical part of the resistive variable layer covers the outside of the side wall of the bump structure, and the bottom end of the vertical part of the resistive variable layer extends in a direction away from the bump structure to form a horizontal part, the The lower surface of the bottom end of the vertical part of the resistive layer and the lower surface of the horizontal part are in contact with the upper surface of the first thermal insulation layer; the second thermal insulation layer covers the top part of the resistive layer and the vertical part of the resistive layer. exterior as well as the upper surface of the horizontal section. The semiconductor integrated circuit component according to claim 1, wherein the bump structure further includes: An oxygen storage layer is located below the dielectric layer. The semiconductor integrated circuit component according to claim 1, wherein the semiconductor integrated circuit component further includes a first metal layer and a second metal layer, the first metal layer is connected to the first thermal insulation layer; The two metal layers are connected to the second thermal insulation layer. The semiconductor integrated circuit element according to claim 3, wherein when the first thermal insulation layer is located inside the resistive layer, correspondingly, the first metal layer is connected to the first thermal insulation layer, including: The first metal layer is connected to the first thermal insulation layer through a through hole. The semiconductor integrated circuit element according to claim 3, wherein when the first thermal insulation layer is located below the resistive switching layer, correspondingly, the first metal layer is connected to the first thermal insulation layer, including: The first metal layer is directly connected to the first thermal insulation layer. The semiconductor integrated circuit component according to claim 1, wherein the material of the thermal insulation layer includes tantalum nitride (TaN). A method for manufacturing semiconductor integrated circuit components, the method includes: obtaining a substrate with a first metal layer; forming a first thermal insulation layer on the first metal layer; forming a first thermal insulation layer on the first thermal insulation layer A bump structure is formed with a dielectric layer in a horizontal direction; a resistive switching layer is formed above the bump structure, so that the resistive switching layer covers a top and the outside of one side wall of the bump structure; A second thermal insulation layer is formed above the variable layer, so that the second thermal insulation layer covers a top and the outside of one side wall of the resistive variable layer; Perform isolation treatment on a bump structure covered with the resistive layer and the second thermal insulation layer, so that the isolation occurs at a flat place on the periphery of the bump structure; wherein, the first thermal insulation layer and the bump The dielectric layer in the structure forms an upper and lower superimposed structure, and is located inside the resistive switching layer; the top part of the resistive switching layer covers the top of the bump structure, and the vertical part of the resistive switching layer covers the bump structure and the bump structure. Outside the side wall of the first thermal insulation layer, the bottom end of the vertical part of the resistive variable layer extends in a direction away from the bump structure to form a horizontal part, and the lower surface of the bottom end of the vertical part of the resistive variable layer and the horizontal part The lower surface is flush with the lower surface of the first thermal insulation layer; the second thermal insulation layer covers the top part of the resistive layer, the outside of the vertical part and the upper surface of the horizontal part; or the first thermal insulation layer Located below the resistive switching layer, the dielectric layer in the bump structure is located inside the resistive switching layer; the top part of the resistive switching layer covers the top of the bump structure, and the vertical part of the resistive switching layer covers the Outside the sidewall of the bump structure, the bottom end of the vertical part of the resistive layer extends in a direction away from the bump structure to form a horizontal part, and the lower surface of the bottom end of the vertical part of the resistive layer and the lower surface of the horizontal part It is attached to the upper surface of the first thermal insulation layer; the second thermal insulation layer covers the top part of the resistive layer, the outside of the vertical part and the upper surface of the horizontal part. The method according to claim 7, wherein after the isolation process is performed on the bump structure covered with the resistive change layer and the second thermal insulation layer, the method further includes: A second metal layer is formed on the bump structure of the second thermal insulation layer and connected to the second thermal insulation layer. The method according to claim 7, wherein forming the first thermal insulation layer on the first metal layer includes: A through hole is formed on the first metal layer; and the first thermal insulation layer is formed on the through hole. The method according to claim 7, wherein the material of the first thermal insulation layer and the second thermal insulation layer includes tantalum nitride TaN, correspondingly, the process of forming the first thermal insulation layer and the second thermal insulation layer Including: physical vapor deposition process, chemical vapor deposition process, or atomic layer deposition process.

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