TWI824627B - Semiconductor integrated circuit component and manufacturing method thereof - Google Patents
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
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Abstract
本案公開了一種半導體積體電路元件及其製造方法,該半導體積體電路元件通過將阻變層覆蓋在凸塊結構的外側,因為在其製備過程中該層不會被蝕刻製程損傷,所以避免了在電操作過程中由蝕刻製程破壞形成的強壯且單一導電細絲的可能性。此外,該半導體積體電路元件增加了全面覆蓋元件的熱保溫層(TEL)使得元件更容易形成多條弱導電細絲,從而達到調節脈衝控制電導連續變化的目的,進而可更好地作為類比型記憶體,應用於CIM等場景。This case discloses a semiconductor integrated circuit element and a manufacturing method thereof. The semiconductor integrated circuit element covers the outside of the bump structure with a resistive switching layer. Because the layer will not be damaged by the etching process during its preparation, it avoids The possibility exists that strong, single conductive filaments formed by the etching process may be destroyed during electrical manipulation. In addition, the semiconductor integrated circuit component adds a thermal insulation layer (TEL) that fully covers the component, making it easier for the component to form multiple weakly conductive filaments, thereby achieving the purpose of adjusting pulses to control continuous changes in conductance, which can be better used as an analog type memory, used in CIM and other scenarios.
Description
相關申請的交叉引用:Cross-references to related applications:
本案基於申請號為202111388509.4、申請日為2021年11月22日的中國專利申請提出,並主張該中國專利申請的優先權,該中國專利申請的全部內容在此引入本案作為參考。This case is based on a Chinese patent application with application number 202111388509.4 and a filing date of November 22, 2021, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this case as a reference.
本案涉及半導體元件領域,尤其涉及一種阻變記憶體(Resistive Random Access Memory,RRAM)及其製造方法。This case involves the field of semiconductor components, especially a resistive random access memory (RRAM) and its manufacturing method.
RRAM的基本結構包括阻變層和位於阻變層兩側的電極。其中,阻變層多為各種氧化薄膜材料,例如過渡金屬氧化物(Transition Metal Oxides,TMO),在外加電壓的作用下,阻變層的電阻狀態可在高阻態和低阻態之間進行轉變,而不同阻態之間的轉變主要是通過導電細絲的形成和斷裂來實現的。The basic structure of RRAM includes a resistive switching layer and electrodes located on both sides of the resistive switching layer. Among them, the resistive variable layer is mostly made of various oxide film materials, such as transition metal oxides (TMO). Under the action of an external voltage, the resistance state of the resistive variable layer can be changed between a high resistance state and a low resistance state. Transition, and the transition between different resistance states is mainly achieved through the formation and breakage of conductive filaments.
由於低功耗、結構簡單、抹寫速度快等優勢,RRAM不僅可以作為新型非揮發性記憶體在數位型(digital)記憶體領域佔據一席之地,而且還可以實現電導雙向可調的類比型(analog)記憶體,通過簡單的乘加運算就可以實現計算儲存一體化(CIM,Computing In Memory),在人工神經網路領域有著巨大的應用潛力。Due to its advantages such as low power consumption, simple structure, and fast erasing and writing speed, RRAM can not only occupy a place in the field of digital memory as a new type of non-volatile memory, but can also realize an analog type with bidirectionally adjustable conductance. ) memory can realize Computing In Memory (CIM, Computing In Memory) through simple multiplication and addition operations, and has huge application potential in the field of artificial neural networks.
與數位型的RRAM不同,類比型的RRAM在元件上會施加連續的電脈衝使其電導呈現連續的多階變化,特別是在SET和RESET過程中不希望出現電導跳變的情況。因此,要求RRAM在生成導電細絲時,最好是生成多條分佈較為均勻的弱導電細絲。Different from digital RRAM, analog RRAM applies continuous electrical pulses to the components to cause continuous multi-level changes in conductance. In particular, conductance jumps are not expected during the SET and RESET processes. Therefore, when RRAM is required to generate conductive filaments, it is best to generate multiple weakly conductive filaments with a relatively uniform distribution.
然而,在主流的RRAM實現過程當中,在定義RRAM單元大小時, RRAM阻變層的邊緣部分被蝕刻製程損傷,導致導電細絲更容易分佈在RRAM的邊緣部分。如果阻變層邊緣部分的損傷過多,則很容易在邊緣形成強壯的導電細絲。在這種情況下,細絲的形成和斷開會導致電導的跳變情況,不能很好地滿足類比型記憶體的要求,導致CIM性能不佳。However, in the mainstream RRAM implementation process, when defining the RRAM cell size, the edge portion of the RRAM resistive layer is damaged by the etching process, causing conductive filaments to be more easily distributed on the edge portion of the RRAM. If there is too much damage to the edge of the resistive layer, strong conductive filaments can easily form at the edge. In this case, the formation and disconnection of filaments can lead to jump conditions in conductance, which cannot meet the requirements of analog memory well, resulting in poor CIM performance.
針對上述技術問題,本申請人創造性地提供了一種半導體積體電路元件及其製備方法。In view of the above technical problems, the applicant creatively provides a semiconductor integrated circuit element and a preparation method thereof.
根據本案實施例的第一方面,提供一種半導體積體電路元件,該半導體積體電路元件包括:凸塊結構,凸塊結構在水平方向設置有介質層;第一熱保溫層(Thermal Enhance Layer,TEL),位於凸塊結構的下方;阻變層,覆蓋在凸塊結構的頂部和側壁外部;第二熱保溫層,覆蓋在阻變層的頂部和側壁外部,與第一熱保溫層共同形成對阻變層和凸塊結構的全覆蓋。According to a first aspect of the embodiment of this case, a semiconductor integrated circuit element is provided. The semiconductor integrated circuit element includes: a bump structure, the bump structure is provided with a dielectric layer in the horizontal direction; a first thermal enhancement layer (Thermal Enhance Layer, TEL), located below the bump structure; a resistive switching layer, covering the top and outside of the side walls of the bump structure; a second thermal insulation layer, covering the top and outside of the side walls of the resistive switching layer, formed together with the first thermal insulation layer Full coverage of the resistive layer and bump structure.
在一可實施方式中,凸塊結構還包括:儲氧層(Oxygen Ion Reservoir,OIR),位於介質層下方。In an implementation, the bump structure further includes: an oxygen storage layer (Oxygen Ion Reservoir, OIR), located below the dielectric layer.
在一可實施方式中,該半導體積體電路元件還包括第一金屬層和第二金屬層,第一金屬層與第一熱保溫層連接;第二金屬層與第二熱保溫層連接。In an embodiment, the semiconductor integrated circuit element further includes a first metal layer and a second metal layer, the first metal layer is connected to the first thermal insulation layer, and the second metal layer is connected to the second thermal insulation layer.
在一可實施方式中,第一熱保溫層位於阻變層的內側,相應地,第一金屬層與第一熱保溫層連接,包括:第一金屬層連接通過通孔(Via)與第一熱保溫層連接。In an embodiment, the first thermal insulation layer is located inside the resistive layer. Correspondingly, the first metal layer is connected to the first thermal insulation layer, including: the first metal layer is connected to the first thermal insulation layer through a through hole (Via). Thermal insulation connection.
在一可實施方式中,第一熱保溫層位於阻變層的內側,相應地,第一金屬層與第一熱保溫層連接,包括:第一金屬層連接直接與第一保溫層連接。In an implementation, the first thermal insulation layer is located inside the resistive layer, and accordingly, the first metal layer is connected to the first thermal insulation layer, including: the first metal layer is directly connected to the first thermal insulation layer.
在一可實施方式中,熱保溫層的材料包括氮化鉭(TaN)。In an implementation manner, the material of the thermal insulation layer includes tantalum nitride (TaN).
根據本案實施例的第二方面,提供一種半導體積體電路元件的製造方法,該方法包括:獲取帶有第一金屬層的基板;在第一金屬層之上形成第一熱保溫層;在第一熱保溫層之上形成在水平方向設置有介質層的凸塊結構;在凸塊結構的上方形成阻變層,使阻變層覆蓋在凸塊結構的頂部和側壁外部;在阻變層的上方形成第二熱保溫層,使第二熱保溫層覆蓋在阻變層的頂部和側壁外部;對覆蓋有阻變層和第二熱保溫層的凸塊結構進行隔斷處理,使隔斷發生於凸塊結構外圍的平坦處。According to a second aspect of the embodiment of the present application, a method for manufacturing a semiconductor integrated circuit element is provided. The method includes: obtaining a substrate with a first metal layer; forming a first thermal insulation layer on the first metal layer; A bump structure with a dielectric layer arranged in the horizontal direction is formed on a thermal insulation layer; a resistive switching layer is formed above the bump structure, so that the resistive switching layer covers the top and side walls of the bump structure; on the resistive switching layer A second thermal insulation layer is formed above, so that the second thermal insulation layer covers the top and outside of the side wall of the resistive switching layer; the bump structure covered with the resistive switching layer and the second thermal insulation layer is partitioned so that the partition occurs on the bump. The flat area on the periphery of a block structure.
在一可實施方式中,在對覆蓋有阻變層和第二熱保溫層的凸塊結構進行隔斷處理之後,該方法還包括:在覆蓋有阻變層和第二熱保溫層的凸塊結構之上製造第二金屬層與第二熱保溫層連接。In an embodiment, after performing isolation treatment on the bump structure covered with the resistive change layer and the second thermal insulation layer, the method further includes: insulating the bump structure covered with the resistive change layer and the second thermal insulation layer A second metal layer is manufactured on top and connected to the second thermal insulation layer.
在一可實施方式中,在第一金屬層之上形成第一熱保溫層,包括:在第一金屬層之上形成通孔;在通孔之上形成第一熱保溫層。In an implementation, forming the first thermal insulation layer on the first metal layer includes: forming a through hole on the first metal layer; and forming the first thermal insulation layer on the through hole.
在一可實施方式中,熱保溫層的材料包括氮化鉭(TaN),相應地,形成熱保溫層的製程包括:物理氣相沉積製程(PVD),化學氣相沉積製程(CVD),或原子層沉積製程(ALD)。In an embodiment, the material of the thermal insulation layer includes tantalum nitride (TaN). Accordingly, the process of forming the thermal insulation layer includes: physical vapor deposition process (PVD), chemical vapor deposition process (CVD), or Atomic layer deposition process (ALD).
本案實施例一種半導體積體電路元件及其製造方法,該半導體積體電路元件通過將阻變層覆蓋在凸塊結構的外側,因為在其製程製備過程中該層不會被蝕刻製程損傷,所以避免了在電操作過程中由蝕刻製程破壞形成的強壯且單一導電細絲的可能性。此外,該半導體積體電路元件增加了全面覆蓋元件的熱保溫層使得元件更容易形成多條弱導電細絲,從而達到通過脈衝連續控制電導連續變化的目的,進而可更好地作為類比型記憶體,應用於CIM等場景。The embodiment of this case is a semiconductor integrated circuit element and its manufacturing method. The semiconductor integrated circuit element covers the outside of the bump structure with a resistive switching layer. Because this layer will not be damaged by the etching process during its manufacturing process, The possibility of strong, single conductive filaments being damaged by the etching process during electrical operations is avoided. In addition, the semiconductor integrated circuit component adds a thermal insulation layer that fully covers the component, making it easier for the component to form multiple weak conductive filaments, thereby achieving the purpose of continuously controlling the continuous change of conductance through pulses, and thus can better serve as an analog memory body, used in CIM and other scenarios.
需要理解的是,本案實施例的實施並不需要實現上面的全部有益效果,而是特定的技術方案可以實現特定的技術效果,並且本案實施例的其他實施方式還能夠實現上面未提到的有益效果。It should be understood that the implementation of the embodiments of this case does not need to achieve all the above beneficial effects, but specific technical solutions can achieve specific technical effects, and other implementations of the embodiments of this case can also achieve benefits not mentioned above. Effect.
為使本案的目的、特徵、優點能夠更加的明顯和易懂,下面將結合本案實施例中的附圖,對本案實施例中的技術方案進行清楚、完整地描述,顯然,所描述的實施例僅僅是本案一部分實施例,而非全部實施例。基於本案中的實施例,本發明所屬領域中具有通常知識者在沒有做出創造性勞動前提下所獲得的所有其他實施例,都屬於本案保護的範圍。In order to make the purpose, features, and advantages of this case more obvious and easy to understand, the technical solutions in the embodiments of this case will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this case. Obviously, the described embodiments These are only some of the embodiments of this case, not all of them. Based on the embodiments in this case, all other embodiments obtained by those with ordinary knowledge in the field to which the present invention belongs without any creative work fall within the scope of protection of this case.
在本說明書的描述中,參考術語“一個實施例”、“一些實施例”、“示例”、“具體示例”、或“一些示例”等的描述意指結合該實施例或示例描述的具體特徵、結構、材料或者特點包含於本案的至少一個實施例或示例中。而且,描述的具體特徵、結構、材料或者特點可以在任一個或多個實施例或示例中以合適的方式結合。此外,在不相互矛盾的情況下,本發明所屬領域中具有通常知識者可以將本說明書中描述的不同實施例或示例以及不同實施例或示例的特徵進行結合和組合。In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the present application. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, a person of ordinary skill in the art to which the present invention pertains may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples unless they are inconsistent with each other.
此外,術語“第一”、“第二”僅用於描述目的,而不能理解為指示或暗示相對重要性或者隱含指明所指示的技術特徵的數量。由此,限定有“第一”、“第二”的特徵可以明示或隱含地包括至少一個該特徵。在本案的描述中,“多個”的含義是兩個或兩個以上,除非另有明確具體的限定。In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of this case, "plurality" means two or more, unless otherwise explicitly and specifically limited.
第1圖示出了本案半導體積體電路元件一實施例的結構剖面示意圖。如第1圖所示,該半導體積體電路元件包括:凸塊結構,凸塊結構在水平方向設置有介質層107;第一熱保溫層105(Thermal Enhance Layer,TEL),位於凸塊結構的下方;阻變層108,覆蓋在凸塊結構的頂部和側壁外部;第二熱保溫層109,覆蓋在阻變層108的頂部和側壁外部,與第一熱保溫層105共同形成對阻變層108和凸塊結構的全覆蓋。Figure 1 shows a schematic structural cross-sectional view of an embodiment of the semiconductor integrated circuit device of the present invention. As shown in Figure 1, the semiconductor integrated circuit element includes: a bump structure, which is provided with a
該凸塊結構在水平方向設置有介質層107;阻變層108,覆蓋在凸塊結構的頂部和側壁外部;第二熱保溫層109,覆蓋在阻變層108的頂部和側壁外部;第一熱保溫層105,位於凸塊結構的下方,與第二熱保溫層109共同形成對阻變層108和凸塊結構的全覆蓋。The bump structure is provided with a
在本案實施例中,凸塊結構包括介質層107和儲氧層106。該凸塊結構可以是倒梯形體、長方體或正方體等。因為凸塊結構凸起的部分有一定高度,故而可以在凸塊結構的側壁外部沉積阻變材料得到豎立的阻變層(阻變層108覆蓋在凸塊結構側壁外部的部分)。在進行後續的刻蝕操作時,可以對處於凸塊結構外圍平坦部分的阻變層進行刻蝕,而使覆蓋在凸塊結構頂部和側壁外部的阻變層部分保持完好,從而不會因為刻蝕產生的損傷在阻變層內形成較強的導電細絲。In this embodiment, the bump structure includes a
如第1圖所示,在凸塊結構頂部和側壁外部的阻變層部分會形成一個折角,而通常在折角部分會形成較強的導電細絲。為此,本案實施例在凸塊結構中設置有介質層107,並使其處於在水平方向。As shown in Figure 1, the resistive layer portion on the top and outside the sidewall of the bump structure will form a corner, and usually strong conductive filaments will be formed in the corner portion. To this end, in this embodiment, a
如此,介質層107可以在折角部分的阻變層和底電極之間形成隔離,就不會在折角部分的阻變層內形成較強的導電細絲。In this way, the
介質層107的材料可以是二氧化矽(SiO
2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。
The material of the
此外,本案實施例在凸塊結構中,還設置有儲氧層106。儲氧層106,位於介質層107的下方,用於吸引或儲備更多的氧,以使導電細絲的形成更為容易和更加穩定。儲氧層106的常用材料包括鈦(Ti)、鉿(Hf)、鋯(Zr)的至少一種。In addition, in this embodiment, an
需要說明的是,儲氧層106的設置是為了使導電細絲形成的效果更好,但並不是必須的,也可以不設置儲氧層106。It should be noted that the
如第1圖所示,阻變層108覆蓋在凸塊結構頂部和側壁外部,可使用任何適用的阻變材料,例如,氧化鋁(AlO)、氧化銅(CuO)、氧化鉿(HfO)、氧化鉬(MoO)、氧化鎳(NiO)、氧化鉭(TaO)、氧化鈦(TiO)、氧化鋅(ZnO)、氧化鋯(ZrO)和氧化鎢(WO)等阻變材料中的一種或多種。As shown in Figure 1, the
如第1圖所示,在阻變層108的頂部和側壁外部還覆蓋有第二熱保溫層109;而在凸塊結構的下方還設置有第一熱保溫層105。As shown in Figure 1, the top and side walls of the
在第1圖所示的實施例中,第一熱保溫層105與凸塊結構中的介質層107形成上下疊加結構,一同位於阻變層108的內側,與第二熱保溫層109形成了對阻變層108和凸塊結構的全覆蓋。In the embodiment shown in Figure 1, the first
由於增溫可使導電細絲的形成更為容易,而對阻變層108和凸塊結構的全覆蓋不僅可以取得更佳的保溫效果,還可以使溫度在阻變層108的分佈更為均勻。從而可形成多條弱導電細絲,易於通過脈衝連續控制電導發生連續變化。Since increasing the temperature can make the formation of conductive filaments easier, the full coverage of the
其中,常用的熱保溫層材料包括:氮化鉭(TaN)和/或氮化鈦(TiN)等。其中,氮化鉭(TaN)的熱導率較低,熱保溫效果更佳。Among them, commonly used thermal insulation layer materials include: tantalum nitride (TaN) and/or titanium nitride (TiN), etc. Among them, tantalum nitride (TaN) has lower thermal conductivity and better thermal insulation effect.
此外,在第1圖所示的實施例中,還包括第二金屬層111和第一金屬層101,第二金屬層111與第二熱保溫層109連接;第一金屬層101,通過通孔104與第一熱保溫層105連接。In addition, in the embodiment shown in Figure 1, it also includes a
其中,第二金屬層111和第一金屬層101,可以是任何適用的金屬材料,包括鋁(Al)、金(Au)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢(W)和氮化鎢(WN)等材料中的一種或多種。The
如此,在第二金屬層111或第一金屬層101上施加電壓,即可在阻變層108豎立的部分形成多條較弱的導電細絲,從而可以作為類比型記憶體,取得更好的CIM性能。In this way, by applying a voltage to the
第2圖示出了本案半導體積體電路元件另一實施例的結構剖面示意圖。如第2圖所示,該半導體積體電路元件包括:凸塊結構,該凸塊結構在水平方向設置有介質層207;第一熱保溫層205,位於凸塊結構的下方;阻變層208,覆蓋在凸塊結構的頂部和側壁外部;第二熱保溫層209,覆蓋在阻變層208的頂部和側壁外部,與第一熱保溫層205共同形成對阻變層208和凸塊結構的全覆蓋。Figure 2 shows a schematic structural cross-sectional view of another embodiment of the semiconductor integrated circuit element of the present invention. As shown in Figure 2, the semiconductor integrated circuit element includes: a bump structure, which is provided with a
與第1圖所示的實施例類似,在第2圖所示的實施例中的凸塊結構中,除了設置有介質層207之外,還設置有儲氧層206。Similar to the embodiment shown in FIG. 1 , in the bump structure in the embodiment shown in FIG. 2 , in addition to the
此外,在第2圖所示的實施例中,也包括第二金屬層211和第一金屬層201,第二金屬層211與第二熱保溫層209連接;第一金屬層201直接與第一熱保溫層205連接。In addition, in the embodiment shown in Figure 2, it also includes a
但在第2圖所示的實施例中,第一熱保溫層205位於阻變層208的下方,替代通孔直接與第一金屬層201連接。However, in the embodiment shown in FIG. 2 , the first
採用這一結構,第一熱保溫層205同樣可以與第二熱保溫層209共同形成對阻變層208和凸塊結構的全覆蓋,且由於第一熱保溫層205替代通孔直接與第一金屬層201連接,可進一步省去製造通孔的步驟,並使整個半導體元件的高度更低,能更好地滿足微縮化需求。Using this structure, the first
在第1圖和第2圖所示的實施例中,阻變層覆蓋在凸塊結構的頂部和側壁外部,其中,由於凸塊結構中水平方向設置的介質層在覆蓋在凸塊結構頂部的阻變層部分和頂電極之間形成電隔離,導電細絲主要形成在覆蓋在凸塊結構側壁外部豎立的阻變層部分,而這部分阻變層是通過沉積形成的,不會因後續的刻蝕製程受到損壞。因此,在阻變層內不會形成較強的導電細絲。In the embodiments shown in Figures 1 and 2, the resistive switching layer covers the top and side walls of the bump structure. Since the dielectric layer disposed horizontally in the bump structure covers the top of the bump structure, Electrical isolation is formed between the resistive variable layer part and the top electrode. The conductive filaments are mainly formed in the resistive variable layer part covering the side walls of the bump structure. This part of the resistive variable layer is formed by deposition and will not be affected by subsequent The etching process is damaged. Therefore, strong conductive filaments are not formed within the resistive layer.
由於第二熱保溫層覆蓋在阻變層的頂部和側壁外部,第一熱保溫層位於凸塊結構的下方,形成對阻變層和凸塊結構的全覆蓋。在通電後,可以使阻變層的溫度更高且溫度分佈更為均勻,也就更容易形成多條弱導電細絲,從而達到通過脈衝連續控制電導連續變化的目的,進而可更好地作為類比型記憶體應用於CIM等場景。Since the second thermal insulation layer covers the top and side walls of the resistive switching layer, the first thermal insulation layer is located below the bump structure, forming full coverage of the resistive switching layer and the bump structure. After being energized, the temperature of the resistive layer can be made higher and the temperature distribution more uniform, which makes it easier to form multiple weak conductive filaments, thereby achieving the purpose of continuously controlling the continuous change of conductance through pulses, and thus can be better used as a Analog memory is used in scenarios such as CIM.
本案還提供一種半導體積體電路元件的製造方法,如第3圖所示,該方法包括:步驟S310,獲取帶有第一金屬層的基板;步驟S320,在第一金屬層之上形成第一熱保溫層;步驟S330,在第一熱保溫層之上形成在水平方向設置有介質層的凸塊結構;步驟S340,在凸塊結構的上方形成阻變層,使阻變層覆蓋在凸塊結構的頂部和側壁外部;步驟S350,在阻變層的上方形成第二熱保溫層,使第二熱保溫層覆蓋在阻變層的頂部和側壁外部;步驟S360,對覆蓋有阻變層和第二熱保溫層的凸塊結構進行隔斷處理,使隔斷發生於凸塊結構外圍的平坦處以確保凸塊結構側壁外部的阻變層和第二熱保溫層完整無損。This case also provides a method for manufacturing semiconductor integrated circuit components. As shown in Figure 3, the method includes: step S310, obtaining a substrate with a first metal layer; step S320, forming a first metal layer on the first metal layer. Thermal insulation layer; Step S330, form a bump structure with a dielectric layer in the horizontal direction on the first thermal insulation layer; Step S340, form a resistive switching layer above the bump structure, so that the resistive switching layer covers the bumps The top of the structure and the outside of the side walls; Step S350, form a second thermal insulation layer above the resistive switching layer, so that the second thermal insulation layer covers the top of the resistive switching layer and the outside of the side walls; Step S360, form the resistive switching layer and the outside of the side wall. The bump structure of the second thermal insulation layer is partitioned so that the partition occurs at a flat area on the periphery of the bump structure to ensure that the resistive layer and the second thermal insulation layer outside the side walls of the bump structure are intact.
在步驟S310中,帶有第一金屬層的基板,該元件主要為本案實施例半導體積體電路元件提供用於通電和施加電壓的第一金屬層,並在其之上製造本案實施例半導體積體電路元件。In step S310, a substrate with a first metal layer is provided. This component mainly provides the first metal layer for energizing and applying voltage to the semiconductor integrated circuit component of the embodiment of the present case, and the semiconductor integrated circuit component of the embodiment of the present case is manufactured on it. body circuit components.
製造帶有第一金屬層的基板,可採用現有任意適用的製備方法。To manufacture the substrate with the first metal layer, any applicable existing preparation method can be used.
在步驟S320中,在第一金屬層之上形成第一熱保溫層時,可採用任何適用的沉積製程在第一金屬層之上沉積任何適用的熱保溫層材料。其中,常用的沉積製程包括:化學氣相沉積製程、物理氣相沉積製程或原子層沉積製程等。In step S320, when forming the first thermal insulation layer on the first metal layer, any suitable deposition process may be used to deposit any suitable thermal insulation layer material on the first metal layer. Among them, commonly used deposition processes include: chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.
其中,所選用的沉積製程通常取決於所選用的熱保溫層材料。例如,若選擇氮化鉭(TaN)作為熱保溫層材料,則比較適合採用物理沉積製程或原子層沉積製程。Among them, the selected deposition process usually depends on the selected thermal insulation layer material. For example, if tantalum nitride (TaN) is selected as the thermal insulation layer material, it is more suitable to use a physical deposition process or an atomic layer deposition process.
在步驟S330中,形成凸塊結構的工序通常包括:逐層沉積凸塊內所設計的各功能層,例如,儲氧層和介質層;之後,進行先光刻再蝕刻得到設計的凸塊結構。In step S330, the process of forming the bump structure usually includes: depositing each designed functional layer in the bump layer by layer, such as an oxygen storage layer and a dielectric layer; and then performing photolithography and then etching to obtain the designed bump structure. .
在步驟S340中,形成阻變層的製程主要包括使用任何適用的沉積製程沉積任何適用的阻變層材料。In step S340, the process of forming the resistive variable layer mainly includes depositing any applicable resistive variable layer material using any applicable deposition process.
在步驟S350中,形成第二熱保溫層的製程主要包括使用任何適用的沉積製程沉積任何適用的熱保溫層材料。In step S350, the process of forming the second thermal insulation layer mainly includes depositing any applicable thermal insulation layer material using any applicable deposition process.
在步驟S360中,進行隔斷處理的製程通常是先光刻再蝕刻,特別需要注意的是,在進行隔斷處理時,務必使隔斷發生於凸塊結構外圍的平坦處以確保凸塊結構側壁外部的阻變層和第二熱保溫層完整無損,並在儲存單元之間形成隔斷,避免短路。In step S360, the process of performing the isolation process is usually photolithography and then etching. It is particularly important to note that when performing the isolation process, the isolation must occur at a flat place on the periphery of the bump structure to ensure the barrier outside the side walls of the bump structure. The variable layer and the second thermal insulation layer remain intact and form a partition between the storage units to avoid short circuits.
之後,還可在覆蓋有阻變層和第二熱保溫層的凸塊結構之上製造第二金屬層與第二熱保溫層連接。這一製程也可採用任何適用的現有製程,故在此不再贅述。After that, a second metal layer can be fabricated on the bump structure covered with the resistive layer and the second thermal insulation layer to connect with the second thermal insulation layer. This process can also adopt any applicable existing process, so it will not be described again here.
第4圖示出了製造第1圖所示的半導體積體電路元件的主要過程,包括:Figure 4 shows the main process of manufacturing the semiconductor integrated circuit component shown in Figure 1, including:
步驟S4010,獲取帶有第一金屬層101的基板102,並在其之上沉積金屬層間介質(Inter Metal Dielectric,IMD)材料,形成電介質層103;Step S4010, obtain the
第一金屬層101的材料可以是鋁(Al)、金(Au)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢(W)和氮化鎢(WN)等材料中的一種或多種。The material of the
金屬層間介質材料可以是現有常用的介質材料,例如,二氧化矽(SiO 2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。 The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (SiN) and other insulating metal oxides or nitrides.
步驟S4020,使用蝕刻製程對基板的電介質層103進行蝕刻得到通孔104,並在通孔104內沉積金屬材料,得到如第5圖所示的結構;Step S4020, use an etching process to etch the
其中,金屬材料可以是鋁(Al)、金(Au)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢(W)和氮化鎢(WN)等材料中的一種或多種。Among them, the metal material can be aluminum (Al), gold (Au), copper (Cu), platinum (Pt), tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), titanium (Ti), One or more materials such as tungsten (W) and tungsten nitride (WN).
步驟S4030,沉積第一熱保溫層105、儲氧層106和介質層107得到如第6圖所示的結構;Step S4030, deposit the first
其中,第一熱保溫層105的材料可以是氮化鉭(TaN)、氮化鈦(TiN)等;Among them, the material of the first
儲氧層106的材料可以是鈦(Ti)、鉿(Hf)和鋯(Zr)中的至少一種;The material of the
介質層107的材料可以是二氧化矽(SiO
2)或氮化矽(SiN)等。
The material of the
步驟S4040,對第一熱保溫層105、儲氧層106和介質層107進行先光刻再蝕刻,得到第7圖所示的結構;Step S4040, perform photolithography and then etching on the first
步驟S4050,沉積阻變層材料108,得到第8圖所示的結構;Step S4050, deposit the
阻變層108的材料可以是氧化鋁(AlO)、氧化銅(CuO)、氧化鉿(HfO)、氧化鉬(MoO)、氧化鎳(NiO)、氧化鉭(TaO)、氧化鈦(TiO)、氧化鋅(ZnO)、氧化鋯(ZrO)和氧化鎢(WO)等阻變材料中的一種或多種。The material of the
步驟S4060,沉積第二熱保溫層109,得到第9圖所示的結構;Step S4060, deposit the second
第二熱保溫層109的材料可以是氮化鉭(TaN)和/或氮化鈦(TiN)等低導熱率材料;The material of the second
步驟S4070,沉積金屬層間介質110,得到第10圖所示的結構;Step S4070, deposit the
金屬層間介質110的材料可以是現有常用的介質材料,例如,二氧化矽(SiO
2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。
The material of the
步驟S4080,對金屬層間介質110進行磨平,得到第11圖所示的結構;Step S4080: Polish the
磨平製程可以採用化學機械拋光(Chemical-Mechanical Polishing,CMP);The grinding process can use chemical-mechanical polishing (CMP);
步驟S4090,通過先光刻再蝕刻的製程,對第一熱保溫層109 位於凸塊結構外圍平坦位置的部分進行隔斷,得到第12圖所示的結構;Step S4090: Cut off the flat portion of the first
步驟S4100,沉積金屬層間介質110,得到第13圖所示的結構;Step S4100, deposit the
金屬層間介質110的材料可以是現有常用的介質材料,例如,二氧化矽(SiO
2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。
The material of the
步驟S4110,對金屬層間介質110進行磨平,得到第14圖所示的結構;Step S4110: Polish the
磨平製程可以採用化學機械拋光(Chemical-Mechanical Polishing,CMP);The grinding process can use chemical-mechanical polishing (CMP);
步驟S4120,沉積第二金屬層111,即得到第1圖所示的本案實施例半導體積體電路元件。Step S4120: deposit the
其中,第二金屬層111的材料可以是鋁(Al)、金(Au)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢(W)和氮化鎢(WN)等材料中的一種或多種。The material of the
第15圖示出了製造第2圖所示的半導體積體電路元件的主要過程,包括:Figure 15 shows the main process of manufacturing the semiconductor integrated circuit component shown in Figure 2, including:
步驟S5010,獲取帶有第一金屬層201的基板202,並在其之上沉積第一熱保溫層205材料,得到第16圖所示的結構;Step S5010, obtain the
第一金屬層201的材料可以是鋁(Al)、金(Au)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢(W)和氮化鎢(WN)等材料中的一種或多種。The material of the
第一熱保溫層205的材料可以是氮化鉭(TaN)和/或氮化鈦(TiN)等低導熱率材料。The material of the first
步驟S5020,對第一熱保溫層205進行先光刻再蝕刻,得到第17圖所示的結構;Step S5020, perform photolithography and then etching on the first
步驟S5030,沉積金屬層間介質202,得到第18圖所示的結構;Step S5030, deposit the
金屬層間介質材料可以是現有常用的介質材料,例如,二氧化矽(SiO 2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。 The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (SiN) and other insulating metal oxides or nitrides.
步驟S5040,沉積儲氧層206和介質層207得到如第19圖所示的結構;Step S5040, deposit the
儲氧層206的材料可以是鈦(Ti)、鉿(Hf)和鋯(Zr)中的至少一種;The material of the
介質層207的材料可以是二氧化矽(SiO
2)或氮化矽(SiN)等。
The material of the
步驟S5050,對儲氧層206和介質層207進行先光刻再蝕刻,得到第20圖所示的結構;Step S5050, perform photolithography and then etching on the
步驟S5060,沉積阻變層208材料,得到第21圖所示的結構;Step S5060, deposit the
阻變層208的材料可以是氧化鋁(AlO)、氧化銅(CuO)、氧化鉿(HfO)、氧化鉬(MoO)、氧化鎳(NiO)、氧化鉭(TaO)、氧化鈦(TiO) 、氧化鋅(ZnO)、氧化鋯(ZrO)和氧化鎢(WO)等阻變材料中的一種或多種。The material of the
步驟S5070,沉積第二熱保溫層209,得到第22圖所示的結構;Step S5070, deposit the second
第二熱保溫層209的材料可以是氮化鉭(TaN)和/或氮化鈦(TiN)等低導熱率材料;The material of the second
步驟S5080,沉積金屬層間介質202,得到第23圖所示的結構;Step S5080, deposit the
金屬層間介質材料可以是現有常用的介質材料,例如,二氧化矽(SiO 2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。 The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (SiN) and other insulating metal oxides or nitrides.
步驟S5090,對金屬層間介質202進行磨平,得到第24圖所示的結構;Step S5090: Polish the inter-metal medium 202 to obtain the structure shown in Figure 24;
磨平製程可以採用化學機械拋光(Chemical-Mechanical Polishing,CMP);The grinding process can use chemical-mechanical polishing (CMP);
步驟S5100,通過先光刻再蝕刻的製程,對第二熱保溫層209 位於凸塊結構之間位置的部分進行隔斷,得到第25圖所示的結構;Step S5100, through a photolithography and then etching process, isolate the portion of the second
步驟S5110,沉積金屬層間介質202,得到第26圖所示的結構;Step S5110, deposit the
金屬層間介質材料可以是現有常用的介質材料,例如,二氧化矽(SiO 2),氮化矽(SiN)等絕緣金屬氧化物或者氮化物。 The inter-metal dielectric material may be an existing commonly used dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride (SiN) and other insulating metal oxides or nitrides.
步驟S5120,對金屬層間介質202進行磨平,得到第27圖所示的結構;Step S5120: Polish the
磨平製程可以採用化學機械拋光(Chemical-Mechanical Polishing,CMP);The grinding process can use chemical-mechanical polishing (CMP);
步驟S5130,沉積第二金屬層211,即得到第2圖所示的本案實施例半導體積體電路元件。Step S5130: deposit the
其中,第二金屬層211的材料可以是鋁(Al)、金(Au)、銅(Cu)、鉑(Pt)、氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢(W)和氮化鎢(WN)等材料中的一種或多種。The material of the
需要說明的是,在本文中,術語“包括”、“包含”或者其任何其他變體意在涵蓋非排他性的包含,從而使得包括一系列要素的過程、方法、物品或者裝置不僅包括那些要素,而且還包括沒有明確列出的其他要素,或者是還包括為這種過程、方法、物品或者裝置所固有的要素。在沒有更多限制的情況下,由語句“包括一個……”限定的要素,並不排除在包括該要素的過程、方法、物品或者裝置中還存在另外的相同要素。It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.
在本案所提供的幾個實施例中,應該理解到,所揭露的元件和方法,可以通過其它的方式實現。以上所描述的元件實施例僅僅是示意性的,例如,單元的劃分,僅僅為一種邏輯功能劃分,實際實現時可以有另外的劃分方式,如:多個單元或組件可以結合,或可以整合到另一個裝置,或一些特徵可以忽略,或不執行。另外,所顯示或討論的各組成部分相互之間的耦合、或直接耦合、或通信連接可以是通過一些接口,設備或單元的間接耦合或通信連接,可以是電性的、機械的或其它形式的。In the several embodiments provided in this case, it should be understood that the disclosed components and methods can be implemented in other ways. The component embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined or integrated into Another device, or some features can be ignored, or not implemented. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be electrical, mechanical, or other forms. of.
以上,僅為本案的具體實施方式,但本案的保護範圍並不局限於此,任何熟悉本發明所屬領域中具有通常知識者在本案揭露的技術範圍內,可輕易想到變化或替換,都應涵蓋在本案的保護範圍之內。因此,本案的保護範圍應以申請專利範圍的保護範圍為准。The above are only specific implementations of this case, but the scope of protection of this case is not limited thereto. Anyone who is familiar with the field and has ordinary knowledge in the field to which the present invention belongs can easily think of changes or substitutions within the technical scope disclosed in this case, and they should all be covered. within the scope of protection in this case. Therefore, the scope of protection in this case should be based on the scope of protection of the patent application.
101:第一金屬層 102:基板 103:電介質層 104:通孔 105:第一熱保溫層 106:儲氧層 107:介質層 108:阻變層 109:第二熱保溫層 110:金屬層間介質 111:第二金屬層 201:第一金屬層 202:金屬層間介質 205:第一熱保溫層 206:儲氧層 207:介質層 208:阻變層 209:第二熱保溫層 211:第二金屬層 S310~S360:步驟 S4010~S4120:步驟 S5010~S5130:步驟 101: First metal layer 102:Substrate 103: Dielectric layer 104:Through hole 105: First thermal insulation layer 106:Oxygen storage layer 107:Media layer 108: Resistive layer 109: Second thermal insulation layer 110:Metal interlayer medium 111: Second metal layer 201: First metal layer 202:Metal interlayer medium 205:First thermal insulation layer 206:Oxygen storage layer 207:Media layer 208: Resistive layer 209: Second thermal insulation layer 211: Second metal layer S310~S360: steps S4010~S4120: steps S5010~S5130: steps
通過參考附圖閱讀下文的詳細描述,本案示例性實施方式的上述以及其他目的、特徵和優點將變得易於理解。在附圖中,以示例性而非限制性的方式示出了本案的若干實施方式,其中: 在附圖中,相同或對應的標號表示相同或對應的部分。 第1圖示出了本案半導體積體電路元件一實施例的結構剖面示意圖; 第2圖示出了本案半導體積體電路元件另一實施例的結構剖面示意圖; 第3圖示出了本案半導體積體電路元件一實施例製造過程示意圖; 第4圖示出了第1圖所示實施例的製造過程示意圖; 第5圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第6圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第7圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第8圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第9圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第10圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第11圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第12圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第13圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第14圖示出了第1圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第15圖示出了第2圖所示實施例的製造過程示意圖; 第16圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第17圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第18圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第19圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第20圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第21圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第22圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第23圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第24圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第25圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第26圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖; 第27圖示出了第2圖所示實施例的製造過程中某一階段的結構剖面示意圖。 The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the case are shown in an illustrative and non-limiting manner, in which: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts. Figure 1 shows a schematic structural cross-sectional view of an embodiment of the semiconductor integrated circuit component of the present invention; Figure 2 shows a schematic structural cross-sectional view of another embodiment of the semiconductor integrated circuit component of the present invention; Figure 3 shows a schematic diagram of the manufacturing process of a semiconductor integrated circuit component according to an embodiment of the present invention; Figure 4 shows a schematic diagram of the manufacturing process of the embodiment shown in Figure 1; Figure 5 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 6 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 7 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 8 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 9 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 10 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 11 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 12 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 13 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 14 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 1; Figure 15 shows a schematic diagram of the manufacturing process of the embodiment shown in Figure 2; Figure 16 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 17 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 18 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 19 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 20 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 21 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 22 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 23 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 24 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 25 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 26 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2; Figure 27 shows a schematic cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown in Figure 2 .
101:第一金屬層 101: First metal layer
102:基板 102:Substrate
103:電介質層 103: Dielectric layer
104:通孔 104:Through hole
105:第一熱保溫層 105: First thermal insulation layer
106:儲氧層 106:Oxygen storage layer
107:介質層 107:Media layer
108:阻變層 108: Resistive layer
109:第二熱保溫層 109: Second thermal insulation layer
110:金屬層間介質 110:Metal interlayer medium
111:第二金屬層 111: Second metal layer
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CN114220915A (en) * | 2021-11-22 | 2022-03-22 | 厦门半导体工业技术研发有限公司 | Semiconductor integrated circuit device and method for manufacturing the same |
-
2021
- 2021-11-22 CN CN202111388509.4A patent/CN114220915A/en active Pending
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2022
- 2022-07-13 WO PCT/CN2022/105494 patent/WO2023087750A1/en unknown
- 2022-07-19 TW TW111126998A patent/TWI824627B/en active
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TW201324757A (en) * | 2011-12-02 | 2013-06-16 | Macronix Int Co Ltd | Thermally confined electrode for programmable resistance memory |
CN109473546A (en) * | 2017-09-07 | 2019-03-15 | 清华大学 | Resistance-variable storing device and preparation method thereof |
CN111584711A (en) * | 2020-04-29 | 2020-08-25 | 厦门半导体工业技术研发有限公司 | RRAM device and method for forming RRAM device |
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TW202335325A (en) | 2023-09-01 |
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