CN106298937B - 一种沟槽型vdmos - Google Patents
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- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
本发明属于半导体技术领域,特别涉及一种沟槽型VDMOS器件。本发明主要在体内沟槽中有二氧化硅层包裹的多晶硅柱,多晶硅柱中存储着均匀负电荷。多晶硅柱的形状为上宽下窄,其与硅片间的二氧化硅的厚度由上至下增加。器件反向阻断时,N‑型漂移区与多晶硅柱内的负电荷之间产生横向电场,辅助耗尽漂移区。由于N‑型漂移区的电势由下至上逐渐降低,而多晶硅柱侧壁的二氧化硅的厚度由上至下增加,使漂移区的横向电场分布更均匀,从而纵向电场更接近矩形分布,提高器件的反向阻断电压。同时,由于没有采用与源电极相连的体场板结构,本发明中的栅漏电容Cds较低。
Description
技术领域
本发明属于半导体技术领域,特别涉及一种沟槽型VDMOS器件。
背景技术
功率VDMOS是多子导电器件,具有开关速度快、输入阻抗高、易驱动等优点。理想的VDMOS应具有较低的导通电阻、开关损耗和较高的阻断电压。但是导通电阻和击穿电压、导通电阻和开关损耗之间存在着牵制作用,限制了功率VDMOS的发展。为了提高器件性能,减小导通电阻,陈星弼院士提出了超结VDMOS结构。对比传统结构,超结结构获得更为优异的器件耐压与导通电阻的折中关系,在相同的器件耐压的条件下,超结结构的VDMOS的导通电阻更小。
由于超结结构VDMOS对于P/N柱的电荷平衡极为敏感,并且在实际工艺中P/N柱的最小宽度限制了元胞尺寸的减小,因此,专利号US6710,403提出了采用多晶硅充当的体内场板结构替代P/N柱来降低漂移区导通电阻,避免电荷平衡的影响,其结构图如图1所示。由于多晶硅的电位和源极相连,体场板型VDMOS反向耐压时,多晶硅电位为低电位,N型漂移区和场板之间形成横向电场,该横向电场起到辅助耗尽N型漂移区的作用,产生类似超结结构的效果,可以使器件在具有高耐压的同时可采用更高杂质浓度的漂移区。但是,体场板型VDMOS也存在一定的缺点,其漂移区内的电场分布如图2所示,可以看出,由于整个场板上的电位相同,漂移区内的电场值沿着垂直方向下降,制约了反向耐压的进一步提高。同时,由于体场板与VDMOS的源极相连,其源漏电容Cds会较高,影响了器件的动态特性。
发明内容
本发明所要解决的,就是针对体场板型VDMOS的上述问题,为了更好的改善反向耐压和导通电阻的折衷关系,在相同的导通电阻的条件下,提高器件的反向耐压,提出了一种沟槽型VDMOS。
本发明的技术方案是:一种沟槽型VDMOS,包括从下至上依次层叠设置的金属化漏极11、N+衬底1、N-漂移区2和金属化源极4;所述N-漂移区2中具有体内沟槽3、P型掺杂区5、N型重掺杂区6、P型重掺杂区7和沟槽8,所述P型掺杂区5位于两侧的体内沟槽3之间,且P型掺杂区5的侧面与体内沟槽3的侧面接触;所述N型重掺杂区6位于P型掺杂区5的上表面,N型重掺杂区6的上表面与金属化源极4的下表面接触;所述P型重掺杂区7位于体内沟槽3与N型重掺杂区6之间并分别于体内沟槽3和N型重掺杂区6接触;所述体内沟槽3的上表面与金属化源极4的下表面接触;所述沟槽8的上表面与金属化源极4的下表面接触,沟槽8的下端沿垂直方向依次贯穿N型重掺杂区6和P型重掺杂区7并延伸至N-漂移区2中,所述沟槽8中填充有第一二氧化硅层9,在第一二氧化硅层9中具有多晶硅10;其特征在于,所述体内沟槽3中填充有第二二氧化硅层12,所述第二二氧化硅层12中具有多晶硅柱13,所述多晶硅柱13的上表面不高于P型掺杂区5的下表面,所述多晶硅岛13中均匀存储有负电荷,所述多晶硅岛13与P-漂移区2之间的二氧化硅12的厚度由上至下逐渐增加。
一种沟槽型VDMOS,包括从下至上依次层叠设置的金属化漏极11、P+衬底1、P-漂移区2和金属化源极4;所述P-漂移区2中具有体内沟槽3、N型掺杂区5、P型重掺杂区6、N型重掺杂区7和沟槽8,所述N型掺杂区5位于两侧的体内沟槽3之间,且N型掺杂区5的侧面与体内沟槽3的侧面接触;所述P型重掺杂区6位于N型掺杂区5的上表面,P型重掺杂区6的上表面与金属化源极4的下表面接触;所述N型重掺杂区7位于体内沟槽3与P型重掺杂区6之间并分别于体内沟槽3和P型重掺杂区6接触;所述体内沟槽3的上表面与金属化源极4的下表面接触;所述沟槽8的上表面与金属化源极4的下表面接触,沟槽8的下端沿垂直方向依次贯穿P型重掺杂区6和N型重掺杂区7并延伸至P-漂移区2中,所述沟槽8中填充有第一二氧化硅层9,在第一二氧化硅层9中具有多晶硅10;其特征在于,所述体内沟槽3中填充有第二二氧化硅层12,所述第二二氧化硅层12中具有多晶硅柱13,所述多晶硅柱13的上表面不高于P型掺杂区5的下表面,所述多晶硅岛13中均匀存储有正电荷,所述多晶硅岛13与P-漂移区2之间的二氧化硅12的厚度由上至下逐渐增加。
进一步的,所述多晶硅10与沟槽8侧壁之间的第一二氧化硅层9的厚度为5-100nm,多晶硅10与沟槽8下表面之间的第一二氧化硅层9的厚度为200—500nm。
本发明的有益效果为,本发明所提供的一种沟槽型VDMOS器件,在体内沟槽3中有二氧化硅层包裹的多晶硅柱13,多晶硅柱13中存储着均匀负电荷。多晶硅柱13的形状为上宽下窄,其与硅片间的二氧化硅12的厚度由上至下增加。器件反向阻断时,N-型漂移区2与多晶硅柱13内的负电荷之间产生横向电场,辅助耗尽漂移区。由于N-型漂移区的电势由下至上逐渐降低,而多晶硅柱13侧壁的二氧化硅12的厚度由上至下增加,使漂移区的横向电场分布更均匀,从而纵向电场更接近矩形分布,提高器件的反向阻断电压。同时,由于没有采用与源电极相连的体场板结构,本发明中的栅漏电容Cds较低。
附图说明
图1是专利号US6710,403提供的一种具有体内场板的VDMOS结构示意图;
图2是专利号US6710,403提供的一种具有体内场板的VDMOS结构在反向偏压时的漂移区内的电场分布示意图;
图3是本发明提供的一种沟槽型VDMOS器件示意图;
图4是本发明提供的一种沟槽型VDMOS器件在反向偏压时的漂移区内的耗尽线及电场分布示意图;
图5-图11是本发明提供的一种沟槽型VDMOS器件制作的关键工艺步骤。
具体实施方式
下面结合附图和实施例,详细描述本发明的技术方案:
实施例1
如图3所示,本例的一种沟槽型VDMOS,包括从下至上依次层叠设置的金属化漏极11、N+衬底1、N-漂移区2和金属化源极4;所述N-漂移区2中具有体内沟槽3、P型掺杂区5、N型重掺杂区6、P型重掺杂区7和沟槽8,所述P型掺杂区5位于两侧的体内沟槽3之间,且P型掺杂区5的侧面与体内沟槽3的侧面接触;所述N型重掺杂区6位于P型掺杂区5的上表面,N型重掺杂区6的上表面与金属化源极4的下表面接触;所述P型重掺杂区7位于体内沟槽3与N型重掺杂区6之间并分别于体内沟槽3和N型重掺杂区6接触;所述体内沟槽3的上表面与金属化源极4的下表面接触;所述沟槽8的上表面与金属化源极4的下表面接触,沟槽8的下端沿垂直方向依次贯穿N型重掺杂区6和P型重掺杂区7并延伸至N-漂移区2中,所述沟槽8中填充有第一二氧化硅层9,在第一二氧化硅层9中具有多晶硅10;其特征在于,所述体内沟槽3中填充有第二二氧化硅层12,所述第二二氧化硅层12中具有多晶硅柱13,所述多晶硅柱13的上表面不高于P型掺杂区5的下表面,所述多晶硅岛13中均匀存储有负电荷,所述多晶硅岛13与P-漂移区2之间的二氧化硅12的厚度由上至下逐渐增加。
(1)器件的正向导通
本发明所提供的一种沟槽型VDMOS器件,其正向导通时的电极连接方式为:多晶硅栅电极10正电位,金属化漏极11接正电位,金属化源极4接零电位。当多晶硅栅电极10所加正电压等于或大于开启电压之后,多子电子在金属化漏极11正电位的作用下从N型重掺杂区6流向金属化漏极11。由于槽型栅电极4底部的栅氧化层采取厚氧工艺,所以栅漏电容Cgd得到较大的改善。同时,由于没有采用与源电极相连的体场板,相较于专利号US6710,403中采用源极体内场板技术,本发明中的源漏电容Cds降低。
(2)器件的反向阻断
器件反向耐压时,N-漂移区和槽3内的多晶硅柱13中的固定负电荷之间存在横向电场,承担反向压降。此时,VDMOS的金属化漏极接高电位,金属化源极接低电位此,因此N-漂移区2由下至上的电势逐渐降低。多晶硅柱13的厚度是由下至上增加的,因此二氧化硅层12的厚度由下至上减少,而多晶硅柱13内存储的固定负电荷的电荷密度是均匀的,因此,N-漂移区2内的与槽3之间的横向电场强度沿着垂直方向基本保持不变。图4所示为器件反向耐压时的N-漂移区垂直方向上的电场分布,可以看出,电场分布近似矩形。此时,漂移区内的耗尽线由槽3两侧向N-漂移区2体内扩展,直至N-漂移区2完全耗尽。相较于专利号US6710,403的器件反向耐压时的N-漂移区垂直方向上的电场分布,电场斜率减小,电场分布E(Y)与Y轴之间围的面积增大,反向阻断耐压提高。
本发明的一种沟槽型VDMOS器件的一种制造工艺流程如下:
1、单晶硅准备及外延生长。在N型重掺杂单晶硅衬底1上,采用气相外延VPE等方法生长一定厚度和掺杂浓度的N-漂移区2,如图5所示。
2、刻蚀槽3,接着槽3内生长二氧化硅层,形成二氧化层12,进行刻蚀,形成斜面的槽,如图6所示。
3、在二氧化硅槽内淀积一定厚度的多晶硅柱13,并注入负离子,使多晶硅柱13带固定负电荷;
4、刻蚀绝缘层,在硅片表面淀积二氧化硅,形成槽3内的二氧化硅层12的顶部,如图7所示。
5、利用光刻板刻蚀P型掺杂区5窗口,进行硼注入,形成P型掺杂区5,如图8所示。
6、光刻N型注入区窗口,进行N型磷注入,形成N型重掺杂区6,如图9所示。
7、刻蚀形成槽8,生长介质层,形成二氧化硅层9的底部及侧壁,接着淀积多晶硅10形成栅电极,如图10所示。
8、生长氧化层,利用光刻板进行离子刻蚀形成窗口,注入硼,形成P型重掺杂区7,如图11所示。
9、金属化。刻蚀掉多余的氧化层,正面金属化,金属刻蚀,背面金属化,钝化等等。
实施例2
本例的结构在实施例1的基础上,将实施例1中的所有N型材料替换为P型材料,所有的P型材料替换为N型材料,多晶硅柱13中的负电荷替换为正电荷。
制作器件时,还可用碳化硅、砷化镓或锗硅等半导体材料替代硅。
Claims (4)
1.一种沟槽型VDMOS,包括从下至上依次层叠设置的金属化漏极(11)、N+衬底(1)、N-漂移区(2)和金属化源极(4);所述N-漂移区(2)中具有体内沟槽(3)、P型掺杂区(5)、N型重掺杂区(6)、P型重掺杂区(7)和沟槽(8),所述P型掺杂区(5)位于两侧的体内沟槽(3)之间,且P型掺杂区(5)的侧面与体内沟槽(3)的侧面接触;所述N型重掺杂区(6)位于P型掺杂区(5)的上表面,N型重掺杂区(6)的上表面与金属化源极(4)的下表面接触;所述P型重掺杂区(7)位于体内沟槽(3)与N型重掺杂区(6)之间并分别与体内沟槽(3)和N型重掺杂区(6)接触;所述体内沟槽(3)的上表面与金属化源极(4)的下表面接触;所述沟槽(8)的上表面与金属化源极(4)的下表面接触,沟槽(8)的下端沿垂直方向依次贯穿N型重掺杂区(6)和P型重掺杂区(7)并延伸至N-漂移区(2)中,所述沟槽(8)中填充有第一二氧化硅层(9),在第一二氧化硅层(9)中具有多晶硅(10);其特征在于,所述体内沟槽(3)中填充有第二二氧化硅层(12),所述第二二氧化硅层(12)中具有多晶硅柱(13),所述多晶硅柱(13)的上表面不高于P型掺杂区(5)的下表面,所述多晶硅柱(13)中均匀存储有负电荷,所述多晶硅柱(13)与N-漂移区(2)之间的二氧化硅(12)的厚度由上至下逐渐增加。
2.根据权利要求1所述的一种沟槽型VDMOS,其特征在于,所述多晶硅(10)与沟槽(8)侧壁之间的第一二氧化硅层(9)的厚度为5-100nm,多晶硅(10)与沟槽(8)下表面之间的第一二氧化硅层(9)的厚度为200-500nm。
3.一种沟槽型VDMOS,包括从下至上依次层叠设置的金属化漏极(11)、P+衬底(1)、P-漂移区(2)和金属化源极(4);所述P-漂移区(2)中具有体内沟槽(3)、N型掺杂区(5)、P型重掺杂区(6)、N型重掺杂区(7)和沟槽(8),所述N型掺杂区(5)位于两侧的体内沟槽(3)之间,且N型掺杂区(5)的侧面与体内沟槽(3)的侧面接触;所述P型重掺杂区(6)位于N型掺杂区(5)的上表面,P型重掺杂区(6)的上表面与金属化源极(4)的下表面接触;所述N型重掺杂区(7)位于体内沟槽(3)与P型重掺杂区(6)之间并分别与体内沟槽(3)和P型重掺杂区(6)接触;所述体内沟槽(3)的上表面与金属化源极(4)的下表面接触;所述沟槽(8)的上表面与金属化源极(4)的下表面接触,沟槽(8)的下端沿垂直方向依次贯穿P型重掺杂区(6)和N型重掺杂区(7)并延伸至P-漂移区(2)中,所述沟槽(8)中填充有第一二氧化硅层(9),在第一二氧化硅层(9)中具有多晶硅(10);其特征在于,所述体内沟槽(3)中填充有第二二氧化硅层(12),所述第二二氧化硅层(12)中具有多晶硅柱(13),所述多晶硅柱(13)的上表面不高于N型掺杂区(5)的下表面,所述多晶硅柱(13)中均匀存储有正电荷,所述多晶硅柱(13)与P-漂移区(2)之间的二氧化硅(12)的厚度由上至下逐渐增加。
4.根据权利要求3所述的一种沟槽型VDMOS,其特征在于,所述多晶硅(10)与沟槽(8)侧壁之间的第一二氧化硅层(9)的厚度为5-100nm,多晶硅(10)与沟槽(8)下表面之间的第一二氧化硅层(9)的厚度为200-500nm。
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US20040021173A1 (en) * | 2002-07-30 | 2004-02-05 | Fairchild Semiconductor Corporation | Dual trench power mosfet |
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