CN106298878A - Double-gate MOSFET structure and preparation method thereof - Google Patents
Double-gate MOSFET structure and preparation method thereof Download PDFInfo
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- CN106298878A CN106298878A CN201610862149.XA CN201610862149A CN106298878A CN 106298878 A CN106298878 A CN 106298878A CN 201610862149 A CN201610862149 A CN 201610862149A CN 106298878 A CN106298878 A CN 106298878A
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- 239000010703 silicon Substances 0.000 claims abstract description 15
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- 238000007789 sealing Methods 0.000 claims description 22
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a double-gate MOSFET structure and a preparation method thereof, belonging to the technical field of semiconductor integration. The dual-gate MOSFET structure comprises a first gate metal layer, a III-V group semiconductor channel layer, a III-V group semiconductor source drain layer and a second gate metal layer from bottom to top, wherein the first gate metal layer and the second gate metal layer form the dual-gate structure; the III-V semiconductor channel layer and the III-V semiconductor source drain layer are made of III-V semiconductor materials. The invention adopts a double-gate structure, which can effectively improve the gate control capability of the MOSFET device and reduce the influence of short channel effect and the like. The invention adopts the through hole technology to realize the back gate structure, thereby effectively reducing the parasitic capacitance and improving the radio frequency characteristic of the device. The MOSFET structure is integrated on a silicon substrate, and can realize monolithic integration with other silicon-based CMOS integrated devices.
Description
Technical field
The present invention relates to field of semiconductor integration technology, particularly relate to a kind of double grids MOSFET structure and preparation method thereof.
Background technology
Semiconductor technology, as the core of information industry and basis, is considered weigh a national science technological progress and combine
Close the important symbol of national power.In more than 40 year of past, the integrated circuit technique based on silicon CMOS technology is followed mole fixed
Restrain and improve the operating rate of chip by the characteristic size reducing device, increase integrated level and reduce cost, integrated circuit
Characteristic size be reduced to nanoscale by micro-meter scale.But when the grid length of MOS device be reduced to 90 nm technology node with
After, traditional silicon base CMOS device is faced with increasing problem, and introducing new construction, new material have become as the rear mole epoch
One of solution.
Traditional MOSFET element structure during device gate length is ever-reduced, short channel effect, Punchthrough, doping
Fluctuations etc. become the factor affecting MOSFET element in succession.Academia generally believes with industrial circle: use mobility channel material
It will be the important development direction of CMOS integrated technology that material substitutes traditional silicon material, and wherein Group III-V semiconductor channel material has most
Large-scale application may be realized in the recent period.MOSFET element structure is also converted to FinFET structure from traditional planar structure,
The lattice parameter of III-V group semi-conductor material can change by changing material component, has the biggest at heterogeneous integrated aspect
Advantage, may be used for prepare ultra-thin body MOSFET element, double-gate structure then be conducive to improve grid-control ability, carry out double grid
The research of MOSFET element seems particularly necessary.And the backgate of traditional double-gate structure MOSFET due to the connecing of raceway groove and source and drain
Touch Area comparison big, thus parasitic capacitance is bigger, limits double-gated devices radio-frequency performance, and use through hole technology will carry on the back
Grid reduce with the contact area of raceway groove and source and drain.Silicon base CMOS technology remains the main flow of semiconductor integration technology, how will
Group III-V semiconductor channel mosfet single-chip integration is to being also problem demanding prompt solution on silicon substrate.How by these new constructions
Organically combine with new material, be to obtain the problem that high performance MOSFET device need to be considered when.For rear mole of epoch
The development of CMOS technology has important function.
Summary of the invention
(1) to solve the technical problem that
Present invention aim at using high mobility compound semiconductor materials as channel material, in order to improve MOSFET device
The mobility of part raceway groove, use double-gated devices structure improve grid-control ability use simultaneously through hole technology to realize back gate contact,
Reduce parasitic gate electric capacity, and use bonding techniques by Group III-V semiconductor trench MOSFET device single-chip integration to silicon also
It is the trend of CMOS integrated technology development, the single-chip integration of mole epoch multifunction chip after being conducive to, in conjunction with above demand, this
Invention is by a kind of for disclosure double grids MOSFET structure and preparation method thereof.
(2) technical scheme
For reaching above-mentioned purpose, the present invention provides a kind of double grids MOSFET structure:
Described double grids MOSFET structure by monocrystalline substrate, sealing coat, bonding metal layer, first grid metal level, remove parasitism
Dielectric layer, first grid dielectric layer, the first Interface Control layer, Group III-V semiconductor channel layer, second contact surface key-course, second gate
Dielectric layer, the 3rd gate dielectric layer, second gate metal level, Group III-V semiconductor source-drain layer, source and drain metal level form, wherein, described
First grid metal level and second gate metal level constitute double-gate structure；Described Group III-V semiconductor channel layer and Group III-V semiconductor
Source-drain layer uses III-V group semi-conductor material.
The component relationship of described double grids MOSFET structure Each part: described sealing coat is stacked in described monocrystalline substrate
On；Described bonding metal layer is stacked on described sealing coat: described first grid metal level is stacked in described bonding metal layer
On, and described first grid metal level core is protruding, whole one-tenth convex；Described parasitic agent layer is gone to be stacked in described first
Grid metal level both sides, and its upper surface and described first grid metal level upper surface level, described first grid metal level bossing
Side and the described side removing parasitic agent layer connect；Described first grid dielectric layer is stacked in described first grid metal level and institute
State on parasitic agent layer；Described first Interface Control layer is stacked on described first grid dielectric layer；Described iii-v half
Conductor channel layer is stacked on described first Interface Control layer；Described second contact surface key-course is stacked in described iii-v half
On conductor channel layer；Described Group III-V semiconductor source-drain layer is stacked in the both sides on described second contact surface key-course；Described
Second gate dielectric layer is stacked on described second contact surface key-course and described Group III-V semiconductor source-drain layer, and by described
The side of Group III-V semiconductor source-drain layer covers；During described second gate metal level is stacked on described second gate dielectric layer
Between, described second gate metal level be shaped as convex-down；Described source and drain metal level is stacked in described Group III-V semiconductor source-drain layer
On；Described 3rd gate dielectric layer is stacked in the both sides on described Group III-V semiconductor source-drain layer；Described source and drain metal level side
Limit side with described 3rd gate dielectric layer and described second gate dielectric layer respectively connects；Described second gate metal level and described source
Do not connect between leakage metal level and keep certain distance.
Described sealing coat is silica-based, aluminum base, zirconio, hafnio, gadolinio, gallio, lanthanio, tantalio, beryllio, titanio, yttrio oxygen
One in compound or its many oxide lamination or its mutual doped oxide layer, the thickness of described sealing coat is in 1 nanometer-300
Between nanometer；
Described bonding metal layer be a kind of or its multiple material in gold, copper, indium, titanium, platinum, chromium, germanium, nickel be combined into folded
Layer, the thickness of described bonding metal layer be 3 angstroms between 300 nanometers；
Described first grid metal level is multiple folded in titanium nitride, tantalum nitride, tungsten, gold, copper, indium, titanium, platinum, chromium, germanium, nickel
Layer composition, and the lower surface lamination of described first grid metal level is the one in gold, copper, indium, titanium, platinum, chromium, germanium, nickel or they are many
Planting the lamination that combination of materials becomes, the lower surface lamination thinnest part thickness of described first grid metal level is 1 nanometer-200 nanometer；
Described go parasitic agent layer be silica-based, aluminum base, zirconio, hafnio, gadolinio, gallio, lanthanio, tantalio, beryllio, titanio,
One in yttrium-based oxide or its many oxide lamination or its mutual doped oxide layer, described in remove the thickness of parasitic agent layer
Between 1 nanometer-200 nanometer；
Described first grid dielectric layer is the oxide of high-k, and these oxides include aluminum base, zirconio, hafnio, gadolinium
Base, gallio, lanthanio, tantalio oxide, the doped chemical in described first grid dielectric layer can be aluminum, zirconium, hafnium, gadolinium, gallium, lanthanum,
Tantalum, nitrogen, phosphorus, the thickness of described first grid dielectric layer is between 3 angstrom of-50 nanometer；
Described first Interface Control layer and described second contact surface key-course are phosphorus-containing compound semiconductor material layer, described
The thickness of one Interface Control layer and described second contact surface key-course is between 3 angstrom of-5 nanometer, in order to reduce source and drain dead resistance, and institute
State the first Interface Control layer and described second contact surface key-course can carry out N-type (during nMOSFET) or p-type (during pMOSFET) weight
Doping.
Described Group III-V semiconductor channel layer is Group III-V compound semiconductor material layer, described Group III-V semiconductor
The thickness of channel layer is between 3 angstrom of-30 nanometer；
Described second gate dielectric layer is the most identical with material with the thickness of described 3rd gate dielectric layer, for the oxygen of high-k
Compound, these oxides include aluminum base, zirconio, hafnio, gadolinio, gallio, lanthanio, tantalio oxide；
Doped chemical in described second gate dielectric layer and described 3rd gate dielectric layer can be aluminum, zirconium, hafnium, gadolinium, gallium,
Lanthanum, tantalum, nitrogen, phosphorus, the thickness of described second gate dielectric layer and described 3rd gate dielectric layer is between 3 angstrom of-10 nanometer；
Described second gate metal level be the one in titanium nitride, tantalum nitride, tungsten, gold, copper, indium, titanium, platinum, chromium, germanium, nickel or
Multiple composition；
Described Group III-V semiconductor source-drain layer is heavily doped N-type (during nMOSFET) or p-type (during pMOSFET) III-V
Race's semiconductor layer, the thickness of described Group III-V semiconductor source-drain layer is between 1 nanometer to 100 nanometers；
Described source and drain metal level be nickel, gold, silicon, palladium, germanium, tungsten, aluminum, titanium, copper, platinum, zinc, one layer of cadmium metal material layer or
Multiple-layer metallization forms.
Additionally, the present invention also provides for the preparation method of a kind of aforementioned double grids MOSFET structure, described method includes walking as follows
Rapid:
Step 1: generate described sealing coat in described monocrystalline substrate, deposits described bond wire on described sealing coat
Layer, thus form the first bonding pad；
Step 2: deposit the material layer of described first grid dielectric layer in Group III-V semiconductor epitaxial substrate, and described
Remove the material layer of parasitic agent layer on the material layer of first grid dielectric layer described in deposition, described in removal part, remove parasitic agent layer
Material layer, removes parasitic agent layer described in formation；At the described material layer going to deposit described first grid metal level on parasitic agent layer,
And carry out planarization process by the way of chemically mechanical polishing, form described first grid metal level, thus form the second bonding
Sheet；
Step 3: described bonding metal layer is relative with described first grid metal level, uses the mode of bonding by described first
Bonding pad and described second bonding pad are bonded together, and remove the portion of material layer of described Group III-V semiconductor epitaxial substrate
Until the material layer of described Group III-V semiconductor source-drain layer stops；
Step 4: remove the material layer of part described Group III-V semiconductor source-drain layer, form described Group III-V semiconductor source
Drop ply, and deposit described second gate dielectric layer and the material layer of the 3rd gate dielectric layer；
Step 5: form described second gate gold on the material layer of described second gate dielectric layer and described 3rd gate dielectric layer
Belong to layer；
Step 6: remove part described second gate dielectric layer and the material layer of described 3rd gate dielectric layer, form described second
Gate dielectric layer and described 3rd gate dielectric layer, and on described Group III-V semiconductor source-drain layer, form described source and drain metal level；
In described step 1, the deposition process of described sealing coat includes that ald, Plasma Enhanced Chemical Vapor are heavy
One or more in long-pending, magnetron sputtering, molecular beam epitaxy or metal organic chemical vapor deposition, dry oxidation, wet oxidation
Deposition process, the deposition process of described bonding metal layer include in magnetron sputtering, electron beam evaporation one or both combine；
In described step 2, described Group III-V semiconductor epitaxial substrate sequentially consists of Group III-V semiconductor, described
The material layer of Group III-V semiconductor source-drain layer, described second contact surface key-course, Group III-V semiconductor channel layer, the first interface control
Preparative layer；Described first grid dielectric layer uses the method deposition of ald, described in go the deposition of material layer of parasitic agent layer
Method includes ald, plasma reinforced chemical vapour deposition, magnetron sputtering, molecular beam epitaxy or Organometallic Chemistry gas
One or more deposition process in deposition, dry oxidation, wet oxidation mutually；The material layer processization of described first grid metal level
When learning mechanical polishing, go described in the thickness ratio of described first grid metal level big 1 nanometer of thickness of parasitic agent layer to 200 nanometers it
Between；
In described step 3, the bonding pattern used is metal-metal bonding；After being bonded, use dry etching or
The mode of wet etching removes described Group III-V semiconductor in described Group III-V semiconductor epitaxial substrate；
In described step 4, use the mode of photoetching, dry etching or wet etching to remove the described iii-v of part and partly lead
The material layer of body source drop ply, spills the upper surface of described second contact surface key-course；Described second gate dielectric layer and described 3rd grid
The material of dielectric layer is identical, uses the method for ald to deposit；
In described step 5, the mode of sputtering, evaporation or ald is used to deposit the material of described second gate metal level
Layer, uses the mode of photoetching, stripping, dry etching or wet etching to remove the material layer of unnecessary described second gate metal level,
Form described second gate metal level；
In described step 6, the mode of photoetching, dry etching or wet etching is used to remove part described second gate dielectric layer
Upper surface with the material layer of described 3rd gate dielectric layer spills described Group III-V semiconductor source-drain layer, forms described second gate
Dielectric layer and described 3rd gate dielectric layer；The mode using sputtering, evaporation or ald deposits described source and drain metal level
Material layer, uses the mode of photoetching, stripping, dry etching or wet etching to remove the material of unnecessary described source and drain metal level
Layer, forms described source and drain metal level.
(3) beneficial effect
Described double grids MOSFET structure is compared conventional planar MOSFET structure and is had the advantage that 1. to use have high electronics
The III-V group semi-conductor material of mobility/high hole mobility is as channel material, and channel carrier mobility is high；2. use
Double-gate structure can be effectively improved the grid-control ability of MOSFET element, reduces the impact of short-channel effect etc.；3. through hole is used
Technology realizes back grid structure can effectively reduce parasitic capacitance, improves the radiofrequency characteristics of device；The most described MOSFET structure collection
Become on a silicon substrate, single-chip integration can be realized with other silicon base CMOS integrated devices.Double grids MOSFET provided by the present invention
Structure has important using value in terms of rear mole of epoch CMOS integrated technology and high-performance Group III-V semiconductor device.
Accompanying drawing explanation
Fig. 1 is the structural representation of double grids MOSFET structure provided by the present invention；
Fig. 2 is described first key formed after monocrystalline substrate deposits the most described sealing coat and described bonding metal layer
Close the structural representation of sheet；
Fig. 3 is the structural representation of described Group III-V semiconductor epitaxial substrate；
Fig. 4 is the structural representation after removing parasitic agent layer described in formation in described Group III-V semiconductor epitaxial substrate；
Fig. 5, for through chemically mechanical polishing, forms the structural representation after described first grid metal level, namely the second bonding
The structural representation of sheet；
Fig. 6 is the structural representation of the bonding pad after described second bonding pad bonding back-off is bonded in the first bonding pad；
Fig. 7 is to remove the portion of material layer of described Group III-V semiconductor epitaxial substrate on described bonding pad until described
Structural representation after the material layer stopping of Group III-V semiconductor source-drain layer；
Fig. 8 is the structural representation after forming described Group III-V semiconductor source-drain layer；
Fig. 9 is the structural representation after the material layer depositing described second gate dielectric layer and the 3rd gate dielectric layer；
Figure 10 is the structural representation after forming described second gate metal level.
Wherein
1 be monocrystalline substrate, 2 be sealing coat, 3 for bonding metal layer, 4a be first grid metal level, 5 for removing parasitic agent
Layer, 6 be first grid dielectric layer, 7a the first Interface Control layer, 8 be Group III-V semiconductor channel layer, 7b second contact surface key-course,
10b be second gate dielectric layer, 10a be the 3rd gate dielectric layer, 4b be second gate metal level, 9 be Group III-V semiconductor source-drain layer,
11 for source and drain metal level, 7c be Group III-V semiconductor, 9a be the material layer of described Group III-V semiconductor source-drain layer, 10 is second
Gate dielectric layer and the material layer of described 3rd gate dielectric layer.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in further detail.
The present embodiment specifically describes a kind of double grids MOSFET structure provided by the present invention and preparation method thereof.
As it is shown in figure 1, double grids MOSFET structure provided by the present invention, described double grids MOSFET structure includes that monocrystal silicon serves as a contrast
The end 1, sealing coat 2, bonding metal layer 3, first grid metal level 4a, go parasitic agent layer 5, first grid dielectric layer the 6, first interface control
Preparative layer 7a, Group III-V semiconductor channel layer 8, second contact surface key-course 7b, second gate dielectric layer 10b, the 3rd gate dielectric layer 10a,
Second gate metal level 4b, Group III-V semiconductor source-drain layer 9, source and drain metal level 11；
Described sealing coat 2 is stacked on described monocrystalline substrate 1；Described bonding metal layer 3 is stacked in described sealing coat 2
On: described first grid metal level 4a is stacked on described bonding metal layer 3, and institute's first grid metal level 4a core is convex
Rise, whole one-tenth convex；Described go parasitic agent layer 5 to be stacked in described first grid metal level 4a both sides, and its upper surface is with described
First grid metal level 4a upper surface level, the side of described first grid metal level 4a bossing and described remove parasitic agent layer 5
Side connect；Described first grid dielectric layer 6 is stacked in bonding metal layer 3 and described goes on parasitic agent layer 5；Described first
Interface Control layer 7a is stacked on described first grid dielectric layer 6；Described Group III-V semiconductor channel layer 8 is stacked in described
On one Interface Control layer 7a；Described second contact surface key-course 7b is stacked on described Group III-V semiconductor channel layer 8；Institute
State Group III-V semiconductor source-drain layer 9 and be stacked in the both sides on described second contact surface key-course 7b；Described second gate dielectric layer
10b is stacked on described second contact surface key-course 7b and described Group III-V semiconductor source-drain layer 9, and by described iii-v
The side of semiconductor source drop ply 9 covers；During described second gate metal level 4b is stacked on described second gate dielectric layer 10b
Between, described second gate metal level 4b is shaped as convex-down；Described source and drain metal level 11 is stacked in described Group III-V semiconductor source
On drop ply 9；Described 3rd gate dielectric layer 10a is stacked in the both sides on described Group III-V semiconductor source-drain layer 9；Described source
Leak metal level 11 side side respectively with described 3rd gate dielectric layer 10a and described second gate dielectric layer 10b to connect；Described
Do not connect between two grid metal level 4b and described source and drain metal level 11 and keep certain distance.
Described sealing coat 2 is silicon dioxide, and the thickness of described sealing coat 2 is 150 nanometers；
Described bonding metal layer 3 is titanium and gold lamination from bottom to up, and in described bonding metal layer 3, the thickness of titanium is 10 to receive
Rice, the thickness of gold is 30 nanometers；
Described first grid metal level 4a is gold and titanium nitride lamination from bottom to up, the thickness of gold in described first grid metal level
Thinnest part is 30 nanometers, and in described first grid metal level 4a, the thickness of titanium nitride is 20 nanometers.
Described go parasitic agent layer 5 for silicon dioxide, described in remove the thickness of parasitic agent layer 5 be 50 nanometers.
Described first grid dielectric layer 6 is aluminium sesquioxide, and the thickness of described first grid dielectric layer 6 is 5 nanometers；
Described first Interface Control layer 7a and described second contact surface key-course 7b is indium phosphide, described first Interface Control layer
The thickness of 7a is 2.5 nanometers, and the thickness of described second contact surface key-course 7b is 2 nanometers, described first Interface Control layer 7a and institute
Stating second contact surface key-course 7b is N-type heavy doping, and doped chemical is all silicon, and doping content is all 5*1018 every cubic centimetre.
Described Group III-V semiconductor channel layer 8 is ingaas layer, indium gallium arsenic in described Group III-V semiconductor channel layer 8
Atomic ratio indium: gallium: arsenic=0.7: 0.3: 1, the thickness of described Group III-V semiconductor channel layer 8 is 8 nanometers；
Described second gate dielectric layer 10b is the most identical with material with the thickness of described 3rd gate dielectric layer 10a, described second gate
Dielectric layer 10b and described 3rd gate dielectric layer 10a is aluminium sesquioxide, and described second gate dielectric layer 10b and described 3rd grid are situated between
The thickness of matter layer 10a is 5 nanometers；
Described second gate metal level 4b is titanium nitride, and the thickness of described second gate metal level 4b is 100 nanometers；
The ingaas layer that described Group III-V semiconductor source-drain layer 9 adulterates for silicon, in described Group III-V semiconductor source-drain layer 9
The atomic ratio of indium gallium arsenic be indium: gallium: arsenic=0.53: 0.47: 1, the thickness of described Group III-V semiconductor source-drain layer 9 is 30
Nanometer；
Described source and drain metal level 11 is tungsten, and the thickness of described source and drain metal level 11 is 100 nanometers.
Additionally, the present invention also provides for the preparation method of a kind of aforementioned double grids MOSFET structure, described method includes walking as follows
Rapid:
Step 1: as in figure 2 it is shown, generate described sealing coat 2 in described monocrystalline substrate 1, heavy on described sealing coat 2
Long-pending described bonding metal layer 3, thus form the first bonding pad；
Step 2: as shown in Figure 3 and Figure 4, deposits described first grid dielectric layer 6 in Group III-V semiconductor epitaxial substrate
Material layer, and on the material layer of described first grid dielectric layer 6, described in deposition, remove the material layer of parasitic agent layer 5, remove part
The described material layer removing parasitic agent layer 5, removes parasitic agent layer 5 described in formation；As it is shown in figure 5, remove parasitic agent layer described
The material layer of upper deposition described first grid metal level 4a, and carry out planarization process by the way of chemically mechanical polishing, formed
Described first grid metal level 4a, thus form the second bonding pad；
Step 3: as shown in Figure 6, described bonding metal layer 3 is relative with described first grid metal level 4a, use bonding
Described first bonding pad and described second bonding pad are bonded together by mode.Partly lead as it is shown in fig. 7, remove described iii-v
The portion of material layer of body epitaxial substrate is until the material layer 9a of described Group III-V semiconductor source-drain layer 9 stops；
Step 4: as shown in Figure 8, removes the material layer 9a of part described Group III-V semiconductor source-drain layer 9, is formed described
Group III-V semiconductor source-drain layer 9；As it is shown in figure 9, deposit described second gate dielectric layer 10b and the material of the 3rd gate dielectric layer 10a
Layer 10；
Step 5: as shown in Figure 10, at described second gate dielectric layer 10b and the material layer 10 of described 3rd gate dielectric layer 10a
Upper formation described second gate metal level 4b；
Step 6: remove part described second gate dielectric layer 10b and the material layer 10 of described 3rd gate dielectric layer 10a, is formed
Described second gate dielectric layer 10b and described 3rd gate dielectric layer 10a, and on described Group III-V semiconductor source-drain layer 9, form institute
State source and drain metal level 11, form double grids MOSFET structure as shown in Figure 1.
In described step 1, the deposition process of described sealing coat 2 is plasma reinforced chemical vapour deposition；
In described step 2, described Group III-V semiconductor epitaxial substrate sequentially consists of Group III-V semiconductor 7c, institute
State the material layer 9a of Group III-V semiconductor source-drain layer 9, described second contact surface key-course 7b, Group III-V semiconductor channel layer 8,
One Interface Control layer 7a；Described first grid dielectric layer 6 uses the method for ald to deposit, described in remove parasitic agent layer 5
The deposition process of material layer is plasma reinforced chemical vapour deposition；The material layer of described first grid metal level 4a is through chemistry machine
During tool polishing, described in the thickness ratio of described first grid metal level 4a, go thickness 20 nanometer of parasitic agent layer；
In described step 3, the bonding pattern used is metal-metal bonding；After being bonded, use wet etching
Mode removes described Group III-V semiconductor 7c in described Group III-V semiconductor epitaxial substrate；
In described step 4, photoetching, the mode of wet etching is used to remove part described Group III-V semiconductor source-drain layer 9
Material layer 9a, spills the upper surface of described second contact surface key-course 7b；Described second gate dielectric layer 10b and described 3rd gate medium
The material of layer 10a is identical, uses the method for ald to deposit；
In described step 5, use the mode of ald to deposit the material layer of described second gate metal level 4b, use light
Carve, the mode of dry etching removes the material layer of unnecessary described second gate metal level 4b, forms described second gate metal level 4b；
In described step 6, photoetching, the mode of dry etching is used to remove part described second gate dielectric layer 10b and described
The material layer 10 of the 3rd gate dielectric layer 10a spills the upper surface of described Group III-V semiconductor source-drain layer 9, forms described second gate
Dielectric layer 10b and described 3rd gate dielectric layer 10a；The mode using sputtering deposits the material layer of described source and drain metal level 11, adopts
Remove the material layer of unnecessary described source and drain metal level by the mode of photoetching, dry etching, form described source and drain metal level 11.
Particular embodiments described above, has been carried out the purpose of the present invention, technical scheme and beneficial effect the most in detail
Describe in detail bright it should be understood that the foregoing is only the specific embodiment of the present invention, be not limited to the present invention, all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, should be included in the protection of the present invention
Within the scope of.
Claims (18)
1. a double grids MOSFET structure, includes first grid metal level, Group III-V semiconductor channel layer, iii-v from bottom to top
Semiconductor source drop ply, second gate metal level, it is characterised in that
Described first grid metal level and second gate metal level constitute double-gate structure；
Described Group III-V semiconductor channel layer and Group III-V semiconductor source-drain layer use III-V group semi-conductor material.
MOSFET structure the most according to claim 1, it is characterised in that described MOSFET structure also includes that monocrystal silicon serves as a contrast
The end, based on monocrystalline substrate, it is followed successively by sealing coat, bonding metal layer, first grid metal level from bottom to top, removes parasitic agent
Layer, first grid dielectric layer, the first Interface Control layer, Group III-V semiconductor channel layer, second contact surface key-course, second gate metal
Layer, Group III-V semiconductor source-drain layer, second gate dielectric layer, the 3rd gate dielectric layer, source and drain metal level.
MOSFET structure the most according to claim 1 and 2, it is characterised in that described first grid metal level is stacked in institute
State on bonding metal layer, and described first grid metal level core is protruding, whole one-tenth convex；Described go parasitic agent stacking
Put in described first grid metal level both sides, and its upper surface and described first grid metal level upper surface level, described first grid gold
The side and the described side removing parasitic agent layer that belong to layer bossing connect.
MOSFET structure the most according to claim 1 and 2, it is characterised in that described second gate metal level is stacked in institute
State the centre on second gate dielectric layer, described second gate metal level be shaped as convex-down, and described second gate metal level and
Do not connect between described source and drain metal level and keep certain distance.
MOSFET structure the most according to claim 1 and 2, it is characterised in that described Group III-V semiconductor channel layer is stacked
On described first Interface Control layer；Described second contact surface key-course is stacked on described Group III-V semiconductor channel layer.
MOSFET structure the most according to claim 1 and 2, it is characterised in that described Group III-V semiconductor source-drain layer is stacked
Both sides on described second contact surface key-course；Described second gate dielectric layer is stacked in described second contact surface key-course and described
On Group III-V semiconductor source-drain layer, and the side of described Group III-V semiconductor source-drain layer is covered；Described source and drain metal
Layer is stacked on described Group III-V semiconductor source-drain layer；Described 3rd gate dielectric layer is stacked in described Group III-V semiconductor source
Both sides on drop ply.
MOSFET structure the most according to claim 2, it is characterised in that described sealing coat is silica-based, aluminum base, zirconio, hafnium
One in base, gadolinio, gallio, lanthanio, tantalio, beryllio, titanio, yttrium-based oxide or its many oxide lamination or its mix mutually
Miscellaneous oxide skin(coating), the thickness of described sealing coat is between 1 nanometer-300 nanometer.
MOSFET structure the most according to claim 2, it is characterised in that described bonding metal layer be gold, copper, indium, titanium,
The lamination that a kind of or its multiple material in platinum, chromium, germanium, nickel is combined into, the thickness of described bonding metal layer is 3 angstroms and receives to 300
Between meter.
MOSFET structure the most according to claim 2, it is characterised in that described first grid metal level is titanium nitride, nitridation
Multiple lamination composition in tantalum, tungsten, gold, copper, indium, titanium, platinum, chromium, germanium, nickel, and the lower surface lamination of described first grid metal level
The lamination being combined into for a kind of or its multiple material in gold, copper, indium, titanium, platinum, chromium, germanium, nickel, described first grid metal level
Lower surface lamination thinnest part thickness is 1 nanometer-200 nanometer.
MOSFET structure the most according to claim 2, it is characterised in that described in go parasitic agent layer be silica-based, aluminum base,
One in zirconio, hafnio, gadolinio, gallio, lanthanio, tantalio, beryllio, titanio, yttrium-based oxide or its many oxide lamination
Or its mutual doped oxide layer, described in go the thickness of parasitic agent layer between 1 nanometer-200 nanometer.
The preparation method of 11. 1 kinds of double grids MOSFET structures, including:
Step 1: layer deposited isolating on substrate, deposits bonding metal layer on described sealing coat, forms the first bonding pad；
Step 2: deposit described first grid dielectric layer, remove parasitic agent layer, first grid metal level, form the second bonding pad；
Step 3: deposition Group III-V semiconductor channel layer and Group III-V semiconductor source-drain layer, and deposit described second gate dielectric layer
With the 3rd gate dielectric layer；
Step 4: deposit second gate metal level on the basis of step 3, and on Group III-V semiconductor source-drain layer described in formation of deposits
Source and drain metal level；
It is characterized in that,
Described structure is all integrated on silicon substrate；
Described double-gate structure uses through hole technology to realize.
The preparation method of 12. MOSFET structure according to claim 11, it is characterised in that described first grid metal level
By the way of chemically mechanical polishing, carry out planarization process, and remove parasitism described in the thickness ratio of the most described first grid metal level
Big 1 nanometer of thickness of dielectric layer is between 200 nanometers.
The preparation method of 13. MOSFET structure according to claim 11, it is characterised in that the first described bonding pad and
The second described bonding pad uses the mode of metal-metal bonding to be bonded together.
The preparation method of 14. MOSFET structure according to claim 11, it is characterised in that described deposition process includes
Ald, plasma reinforced chemical vapour deposition, magnetron sputtering, molecular beam epitaxy or metal organic chemical vapor deposition,
One or more deposition process in dry oxidation, wet oxidation, electron beam evaporation.
The preparation method of 15. MOSFET structure according to claim 11, it is characterised in that described Group III-V semiconductor
The material layer of source-drain layer uses the mode of photoetching, dry etching or wet etching to remove, and exposes described second contact surface key-course
Upper surface.
The preparation method of 16. MOSFET structure according to claim 11, it is characterised in that described second gate metal level is many
Remaining material layer uses the mode of photoetching, stripping, dry etching or wet etching to remove, and forms described second gate metal level.
The preparation method of 17. MOSFET structure according to claim 11, it is characterised in that use photoetching, dry etching
Or the mode of wet etching removes the excess stock layer of part described second gate dielectric layer and described 3rd gate dielectric layer and exposes institute
State the upper surface of Group III-V semiconductor source-drain layer, form described second gate dielectric layer and described 3rd gate dielectric layer, and described
The material of two gate dielectric layers and the 3rd gate dielectric layer is identical.
The preparation method of 18. MOSFET structure according to claim 11, it is characterised in that described source and drain metal level is many
Remaining material layer uses the mode of photoetching, stripping, dry etching or wet etching to remove, and forms described source and drain metal level.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833923A (en) * | 2017-10-30 | 2018-03-23 | 桂林电子科技大学 | A kind of silicon substrate InGaAs channel dual-bar MOSFET elements and preparation method thereof |
| CN112563332A (en) * | 2020-12-16 | 2021-03-26 | 南京工程学院 | Ge-based double-gate type InGaAs nMOSFET device and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610640A (en) * | 2011-11-29 | 2012-07-25 | 中国科学院微电子研究所 | High-drive-current III-V metal oxide semiconductor device |
| US20150151640A1 (en) * | 2011-10-18 | 2015-06-04 | Audi Ag | Vehicle with an electric drive |
| CN104900654A (en) * | 2015-04-14 | 2015-09-09 | 深圳市华星光电技术有限公司 | Preparation method and structure of double-grid oxide semiconductor TFT substrate |
| CN105702721A (en) * | 2016-04-20 | 2016-06-22 | 杭州电子科技大学 | Novel asymmetric double-gate tunnelling field effect transistor |
| CN105870182A (en) * | 2016-04-20 | 2016-08-17 | 杭州电子科技大学 | Sandwich-structure double gate vertical tunneling field effect transistor |
-
2016
- 2016-09-28 CN CN201610862149.XA patent/CN106298878B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150151640A1 (en) * | 2011-10-18 | 2015-06-04 | Audi Ag | Vehicle with an electric drive |
| CN102610640A (en) * | 2011-11-29 | 2012-07-25 | 中国科学院微电子研究所 | High-drive-current III-V metal oxide semiconductor device |
| CN104900654A (en) * | 2015-04-14 | 2015-09-09 | 深圳市华星光电技术有限公司 | Preparation method and structure of double-grid oxide semiconductor TFT substrate |
| CN105702721A (en) * | 2016-04-20 | 2016-06-22 | 杭州电子科技大学 | Novel asymmetric double-gate tunnelling field effect transistor |
| CN105870182A (en) * | 2016-04-20 | 2016-08-17 | 杭州电子科技大学 | Sandwich-structure double gate vertical tunneling field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833923A (en) * | 2017-10-30 | 2018-03-23 | 桂林电子科技大学 | A kind of silicon substrate InGaAs channel dual-bar MOSFET elements and preparation method thereof |
| CN112563332A (en) * | 2020-12-16 | 2021-03-26 | 南京工程学院 | Ge-based double-gate type InGaAs nMOSFET device and preparation method thereof |
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