CN106252456B - 一种高灵敏度光敏三极管及其制造方法 - Google Patents
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Abstract
本发明公开一种高灵敏度光敏三极管，包括基区、发射区、发射极金属区、高阻区、钝化区，所述基区由多个独立基区组成，所述独立基区构成元胞状结构，所述发射区位于独立基区内，所述发射极金属区独立位于所述发射区内，相连的所述发射极金属区形成光敏三极管的发射极E，所述高阻区位于相互独立基区之间，所述钝化区位于独立基区之间的高阻区上。本发明中高阻区处于耗尽状态时能够能承受更高的耐压，使得击穿电压能够达到70V以上而不受光敏三极管电流放大倍数和工艺的限制；同时光敏三极管的基区由多个独立的基区构成，且受光区位于基区和高阻区表面，具有更高的光吸收效率，对微弱的光能够产生响应，具有光灵敏度高的特点。
Description
技术领域
本发明属于半导体技术领域，具体涉及到一种高灵敏度光敏三极管及其制造方法。
背景技术
光敏三极管是一种常用的光电半导体器件，与普通三极管结构类似，它同样由发射区、基区和集电区构成，不同之处在于普通三极管通过基极电流控制集电极电流，而光敏三极管通过光信号来控制集电极电流。光敏三极管有一个对光敏感的区域作为受光区，一般用集电结作为受光区，工作时光敏三极管集电结处于反偏状态，特定波长的光照射到半导体基体的表面，一部分被反射，另一部分未被反射，未被反射的光子渡越光敏三极管的基区到集电结，在集电结空间电荷区产生电子-空穴对，受电场的作用光生电子被集电区收集，光生空穴则在基区积累，空穴的积累使发射结势垒降低，发射区电子注入基区，并渡越基区被集电区收集从而产生集电极电流。
光敏三极管广泛用于光强检测、光电耦合电路中，能对特定波长、特定强度的光做出响应，将光信号转化为电信号，实现光电控制和光电隔离。普通的光敏三极管为了提高灵敏度通常发射区结深较深而基区宽度较小以确保光敏三极管具有较高的放大倍数，但这种结构工艺控制十分困难，容易发生基区穿通，同时器件的击穿电压不容易做高，一般只能达到50V以内。
发明内容
本发明提供的一种高灵敏度光敏三极管及其制造方法，目的在于增大击穿电压的数值，同时提高光敏三极管对微弱光的灵敏度。
本发明的目的可以通过以下技术方案实现：
一种高灵敏度光敏三极管，包括基区、发射区、发射极金属区、高阻区、钝化区，所述基区由多个独立基区组成，所述独立基区构成元胞状结构，所述发射区位于独立基区内，所述发射极金属区独立位于所述发射区内，相连的所述发射极金属区形成光敏三极管的发射极E，所述高阻区位于相互独立基区之间，所述钝化区位于独立基区之间的高阻区上。
进一步地，多个所述独立基区以及所述独立基区之间的所述高阻区构成了三极管的受光区。
进一步地，当高灵敏度光敏三极管工作时在集电极C上加相对于发射极E为正的电压，所述元胞结构的基区之间的高阻区处于耗尽状态，耗尽层内的高电场有利于光生载流子的产生和分离，且阻断状态时具有70V以上的击穿电压。
一种高灵敏度光敏三极管的制造方法，包括如下步骤：
S1、选择硅片，在衬底掺磷，在外延层掺磷；
S2、对基区进行光刻，再对基区进行硼离子注入掺杂，离子注入后对基区再分布推结；
S3、对发射区进行光刻，向发射区进行磷离子注入掺杂，离子注入后对发射区再分布推结；
S4、蚀刻出接触孔，对互连金属层进行淀积，在硅片双面进行铝PVD淀积，淀积后正面的厚度为5-6um，背面的厚度为2-3um；
S5、对金属层光刻，刻蚀出区域3，再进行金属层真空合金，最后在硅片背面进行Ti-Ni-Ag复合三层金属的PVD沉积；
S6、硅片初测、切割、装架、烧结、封装测试。
进一步地，所述基区光刻及扩散掺杂后应确保各独立基区之间的间距d为5-10μm。
本发明的有益效果：本发明中高阻区处于耗尽状态时能够能承受更高的耐压，使得击穿电压能够达到70V以上而不受光敏三极管电流放大倍数和工艺的限制；同时光敏三极管的基区由多个独立的基区构成，且受光区位于基区和高阻区表面，具有更高的光吸收效率，对微弱的光能够产生响应，具有光灵敏度高的特点。
附图说明
为了便于本领域技术人员理解，下面结合附图对本发明作进一步的说明。
图1为本发明一种高灵敏度光敏三极管结构示意图；
图2为本发明一种高灵敏度光敏三极管纵向结构示意图。
具体实施方式
一种高灵敏度光敏三极管，如图1、2所示，包含基区1、发射区2、发射极金属区3、高阻区、钝化区，基区1由多个独立基区组成，独立基区构成元胞状结构，发射区2位于独立基区内，发射极金属区3独立位于发射区2内，相连的发射极金属区3形成光敏三极管的发射极E，高阻区位于相互独立基区之间，钝化区位于独立基区之间的高阻区上。
高灵敏光敏三极管采用高阻n型外延片制作，多个独立基区以及独立基区之间的高阻区构成了三极管的受光区，相互独立基区之间保持一优化的间距d，其优化值为5-10μm，硅片的背面形成金属层成为光敏三极管的集电极C。
当光敏三极管工作时在集电极C上加相对于发射极E为正的电压，由于独立基区之间的间距为5-10μm，元胞结构的基区之间的高阻区处于耗尽状态，耗尽层内的高电场有利于光生载流子的产生和分离，且阻断状态时具有70V以上的击穿电压，同时高阻区位于半导体基体的表面能更好地吸收光，吸收效率较高，因此入射到器件表面的光子不用渡越基区，能大部分被反偏集电结空间电荷区吸收并产生光生电子-空穴对，具有较高的量子效率，在集电结空间电场的作用下电子被集电区收集，空穴在基区积累使发射结势垒降低，发射区向基区注入电子，注入基区的电子渡越基区后被集电区收集形成集电极电流，从而完成光电转换。
高灵敏度光敏三极管的制造包括硅片制备、氧化、基区光刻、基区掺杂、发射区光刻、发射区掺杂、接触孔光刻、金属淀积、刻蚀、合金工艺步骤制备而成。
其具体制造方法如下：
S1、选择缺陷较少的n型掺杂<100>晶向外延片，硅片厚为260μm，在衬底掺磷，使其电阻率为0.002-0.1Ω·cm；在硅片的外延层掺磷，使其电阻率为2-20Ω·cm，厚度为5-30μm；
S2、硅片表面经过氧化覆盖有氧化层，先对元胞型基区进行光刻，再对基区进行硼离子注入掺杂，注入的能量为100-150keV，注入硼的剂量为1e14-2e15cm-2，离子注入后对基区再分布推结，推结时的温度为1230℃-1250℃，时间为60-300min，基区光刻及扩散掺杂后应确保各独立基区之间的间距d控制在较优化的水平，d的典型数值为5-10μm；
S3、对发射区进行光刻，向发射区进行磷离子注入掺杂，注入的能量为80-120keV，注入磷的剂量为5e14-5e15cm-2，离子注入后对发射区再分布推结，推结时的温度为1210℃-1230℃，时间60-120min；发射区扩散后应确保基区宽度在0.5-1.5μm之间；
S4、在发射区蚀刻出接触孔，对互连金属层进行淀积，在硅片双面进行铝PVD淀积，淀积后正面的厚度为5-6um，背面的厚度为2-3um；
S5、对金属层光刻，刻蚀出区域3，再进行金属层真空合金，最后在硅片背面进行Ti-Ni-Ag复合三层金属的PVD沉积；
S6、硅片初测、切割、装架、烧结、封装测试。
以上内容仅仅是对本发明的构思所作的举例和说明，所属本技术领域的技术人员对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代，只要不偏离发明的构思或者超越本权利要求书所定义的范围，均应属于本发明的保护范围。
Claims (2)
1.一种高灵敏度光敏三极管，其特征在于：包括基区(1)、发射区(2)、发射极金属区(3)、高阻区、钝化区，所述基区(1)由多个独立基区组成，所述独立基区构成元胞状结构，所述发射区(2)位于独立基区内，所述发射极金属区(3)独立位于所述发射区(2)内，相连的所述发射极金属区(3)形成光敏三极管的发射极E，所述高阻区位于相互独立基区之间，所述钝化区位于独立基区之间的高阻区上；
多个所述独立基区以及所述独立基区之间的所述高阻区构成了三极管的受光区；
当高灵敏度光敏三极管工作时在集电极C上加相对于发射极E为正的电压，所述元胞结构的基区之间的高阻区处于耗尽状态，耗尽层内的高电场有利于光生载流子的产生和分离，且阻断状态时具有70V以上的击穿电压；
一种高灵敏度光敏三极管的制造方法，包括如下步骤：
S1、选择硅片，在衬底掺磷，在外延层掺磷；
S2、对基区进行光刻，再对基区进行硼离子注入掺杂，注入的能量为100-150keV，注入硼的剂量为1e14-2e15cm-2，离子注入后对基区再分布推结，所述基区光刻及扩散掺杂后应确保各独立基区之间的间距d为5-10μm；
S3、对发射区进行光刻，向发射区进行磷离子注入掺杂，注入的能量为80-120keV，注入磷的剂量为5e14-5e15cm-2，离子注入后对发射区再分布推结；
S4、蚀刻出接触孔，对互连金属层进行淀积，在硅片双面进行铝PVD淀积，淀积后正面的厚度为5-6um，背面的厚度为2-3um；
S5、对金属层光刻，刻蚀出区域(3)，再进行金属层真空合金，最后在硅片背面进行Ti-Ni-Ag复合三层金属的PVD沉积；
S6、硅片初测、切割、装架、烧结、封装测试。
2.一种高灵敏度光敏三极管的制造方法，其特征在于，包括如下步骤：
S1、选择硅片，在衬底掺磷，在外延层掺磷；
S2、对基区进行光刻，再对基区进行硼离子注入掺杂，离子注入后对基区再分布推结，所述基区光刻及扩散掺杂后应确保各独立基区之间的间距d为5-10μm；
S3、对发射区进行光刻，向发射区进行磷离子注入掺杂，离子注入后对发射区再分布推结；
S4、蚀刻出接触孔，对互连金属层进行淀积，在硅片双面进行铝PVD淀积，淀积后正面的厚度为5-6um，背面的厚度为2-3um；
S5、对金属层光刻，刻蚀出区域(3)，再进行金属层真空合金，最后在硅片背面进行Ti-Ni-Ag复合三层金属的PVD沉积；
S6、硅片初测、切割、装架、烧结、封装测试。
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