CN106252317A - 具有集成电路模块和减小的键合接线应力的集成电路（ic）卡以及形成方法 - Google Patents

具有集成电路模块和减小的键合接线应力的集成电路（ic）卡以及形成方法 Download PDF

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CN106252317A
CN106252317A CN201511021524.XA CN201511021524A CN106252317A CN 106252317 A CN106252317 A CN 106252317A CN 201511021524 A CN201511021524 A CN 201511021524A CN 106252317 A CN106252317 A CN 106252317A
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support layer
dielectric support
cte
card
mold compound
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CN106252317B (zh
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张学仁
K-Y·吴
R·杜卡
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STMicroelectronics International NV
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STMicroelectronics SA
STMicroelectronics Malta Ltd
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    • H01L2924/181—Encapsulation

Abstract

一种用于IC卡的集成电路(IC)模块包括处于并排关系的多个IC卡触点。电介质支撑层位于接触层上方并且具有多个开口和第一热膨胀系数(CTE)。IC裸片位于该电介质支撑层上方并且包括多个键合焊盘。键合接线从对应的键合焊盘延伸穿过该电介质支撑层中的相邻开口到达相应的触点。对应的填料本体位于每个开口之内并且具有第二CTE。模具化合物本体位于该电介质支撑层、这些填料本体上方并且包围该IC裸片。该模具化合物本体具有第三CTE。第一CTE与接近于第三CTE相比更接近于第二CTE。

Description

具有集成电路模块和减小的键合接线应力的集成电路（IC）卡以及形成方法
技术领域
本发明涉及集成电路(IC)卡领域，并且更具体地涉及一种用于IC卡并且在触点具有填料热匹配以便减小键合接线应力的集成电路(IC)模块。
背景技术
IC卡是通常大约正常信用卡大小并且具有嵌入式集成电路(IC)裸片的袖珍卡。该卡通常由软塑料制成。IC模块固持住IC裸片并且IC模块固定在IC卡的表面上。IC裸片包括存储器和微处理器并且当IC卡被插入读卡器中时具有连接到读卡器的多个电触点。键合接线与IC裸片上对应的键合焊盘相连接。用于IC卡的IC模块在其表面上通常包括八个金属焊盘或触点并且每个焊盘或触点按照国际标准设计，包括例如VCC(电源电压)、RST(用来使IC卡的微处理器复位)、CLK(时钟信号)、GND(接地)、VPP(编程或写电压)、以及I/O(串行输入/输出线)。IC卡具有随机存取存储器(RAM)和只读存储器(ROM)电路，使用串行接口并且从外部源(例如，读卡器)接收功率。RAM用作计算和输入/输出通信的临时存储设备，而ROM包括程序存储器和芯片操作系统(COS)的指令，通常是“掩模”。
当IC卡被插入到读卡器中时，金属焊盘或触点与读卡器接触并且与读卡器中的金属销相连接，从而允许卡和读卡器进行通信。当IC卡插入到读卡器中时，它们被复位，从而引起IC卡以发送“复位应答”(ATR)消息来进行响应，该消息通知读卡器控制事务的通信和处理。
IC裸片通常位于电介质支撑层上方并且包括多个开口。键合接线从IC裸片上的对应的键合焊盘延伸穿过电介质支撑层中的相邻开口到达相应的触点。键合接线通过键合焊盘上的“球式”键合和通过“针脚式”键合(又被称为楔形键合)穿过电介质支撑层中的相邻开口连接至相应的触点。针脚式键合通常是使用超声接线键合工艺将细键合接线焊接至电镀引线框柱或“指状物”上。针脚式键合可以包括接线到下面的键合表面的压缩或超声键合区域。
模具化合物本体通常位于电介质支撑层上方并且包围IC裸片。模具化合物本体通常由具有与电介质支撑层的CTE相比较更低的热膨胀系数(CTE)的材料形成，如环氧化物填充物，在一个示例中，该电介质支撑层由又被称为带(tape)的E-玻璃材料形成。两个基本上不同的CTE引起的热失配会在电介质支撑层上方的模具化合物与形成在接触层处的触点之间产生高应力和在IC裸片上产生额外应力，这些高应力引起脱层和产生的键合接线到触点的针脚式键合牵拉和故障。
发明内容
一种用于IC卡的集成电路(IC)模块包括接触层，该接触层具有处于并排关系的多个IC卡触点。电介质支撑层位于该接触层上方并且具有在该电介质支撑层中的多个开口。该电介质支撑层具有第一热膨胀系数(CTE)。IC裸片位于该电介质支撑层上方并且包括在该IC裸片的上表面上的多个键合焊盘。包括多条键合接线，并且每条键合接线从对应的键合焊盘延伸穿过该电介质支撑层中的相邻开口到达相应的触点。对应的填料本体在该电介质支撑层中的每个开口之内。每个填料本体具有第二CTE。模具化合物本体位于该电介质支撑层、这些填料本体上方并且包围该IC裸片。该模具化合物本体具有第三CTE。第一CTE与接近于第三CTE相比更接近于第二CTE。
第一CTE可以在60至200PPM/℃的范围内。第二CTE可以 在70至200PPM/℃的范围内。第三CTE可以在3至50PPM/℃的范围内。
在实施例中，每个填料本体可以将对应的开口填充至与该电介质支撑层的相邻部分齐平的水平。该电介质支撑层可以具有从该模具化合物本体的相邻部分横向地向外延伸的多个周边部分。该电介质支撑层可以包括E-玻璃。该接触层可以包括铜，并且该模具化合物可以包括环氧化物。第一粘合层可以位于该接触层与该电介质支撑层之间，并且第二粘合层可以位于该电介质支撑层与该IC裸片之间。
又另一个方面针对一种用于制作IC卡的集成电路(IC)模块的方法。该方法可以包括：形成接触层，该接触层具有处于并排关系的多个IC卡触点，并且在该接触层上方形成电介质支撑层，该电介质支撑层具有在其中的多个开口，该电介质支撑层具有第一热膨胀系数(CTE)。该方法可以包括对IC裸片进行定位，该IC裸片位于该电介质支撑层上方并且包括在该IC裸片的上表面上的多个键合焊盘。该方法可以进一步包括将多条键合接线耦接至这些IC卡触点，每条键合接线从对应的键合焊盘延伸穿过该电介质支撑层中的相邻开口到达相应的触点。该方法还可以包括形成对应的填料本体，该对应的填料本体在该电介质支撑层中的每个开口之内，每个填料本体具有第二CTE。该方法还可以包括形成模具化合物本体，该模具化合物本体位于该电介质支撑层、这些填料本体上方并且包围该IC裸片。该模具化合物本体具有第三CTE。第一CTE可以与接近于第三CTE相比更接近于第二CTE。
附图说明
图1是IC卡的透视图，示出了现有技术IC卡本体承载的集成电路(IC)模块。
图2是IC模块的平面图，示出了现有技术中以并排关系安排的IC卡触点的配置。
图3是现有技术IC卡的一部分的截面图，该部分没有填料并且示出了从IC裸片上的键合焊盘延伸穿过电介质支撑层中的相邻开口并且连接至IC卡触点上的键合接线。
图4是与图3相似的截面图，但根据本发明示出了电介质支撑层中的每个开口之内的填料本体，该填料本体与电介质支撑层的热膨胀系数更匹配以减少IC卡触点处的应力。
图5是现有技术中IC模块的一部分的局部透视图，该部分没有填料并且示出了接触层和电介质支撑层和形成接线键合窝(pot)的开口，这些键合接线延伸到这些接线键合窝中以连接至对应的IC卡触点。
图6是现有技术中当模具化合物本体延伸穿过开口到达接触层时场应力结果的第一模拟，并且示出了模具化合物本体和接触层处的高剥离应力。
图7是根据本发明依据非限制性示例当对应的填料本体在电介质支撑层中的每个开口之内延伸时场应力结果的第二模拟，并且示出了减小的剥离应力。
具体实施方式
现在将参照附图在下文中更为全面地描述本发明，在附图中示出了本发明的优选实施例。然而，本发明可以用许多不同的形式体现，并且不应当被解释为受到在此所列出的实施例的限制。相反，提供这些实施例以便本披露将是彻底和完整的，并且将向本领域技术人员充分地传达本发明的范围。贯穿全文相同的数字指代相同的元件。
图1中示出了IC卡(或芯片卡)10并且该卡包括如以下更详细解释的IC卡本体12和由该IC卡本体承载并且具有形成在接触层18处的多个IC卡触点16的集成电路(IC)14。在本示例中，IC卡10是大约常规信用卡大小的袖珍卡并且包括作为IC模块14的一部分的嵌入式集成电路裸片。IC卡本体12通常由软塑料材料制成，如 聚氯乙烯、基于聚对苯二甲酸乙二醇酯的聚酯、丙烯腈-丁二烯-苯乙烯(ABS)或聚碳酸酯。IC卡本体12还可以由不同的卡层形成，这些卡层用高应力印刷和层压，接着是冲裁或裸片切割并且然后嵌入IC裸片。
图2中示出了IC模块14的接触层18，其中以并排关系形成了多个IC卡触点16。图2中所示的IC卡触点16还与被称为IC卡引脚并且按照国际标准设计的八个金属焊盘相对应。例如，作为触点C1的VCC用于电源电压。触点C2与用于使IC卡的微处理器复位和使卡通信复位的复位信号的RST触点相对应。触点C3是与从其中导出数据通信定时的时钟信号相对应的CLK触点。触点C5与作为参考电压的接地(GND)相对应。触点C6是与写电压相对应的VPP。
例如，ISO/IEC 7816-3标准指定编程电压和到程序持久存储器(如EEPROM)的更高电压的输入。可替代地，ISO/IEC 7816-3:2006标准指定用于或者标准用途或者专有用途的SPU作为输入端和/或输出端。触点C7与作为串行输入/输出线并且通常是半双工输出端的I/O相对应。其余的触点C4和C8是作为AUX1和AUX2的辅助触点并且可以用于USB接口和其他辅助用途。
如图1和图2中所示的IC卡通常包括随机存取存储器(RAM)和只读存储器(ROM)并且采用串行接口。在大多数示例中，它们从外部源(例如，读卡器)接收功率。RAM用作计算和输入/输出通信的临时存储设备，而ROM包括程序存储器和芯片操作系统(COS)的指令，大多数情况下作为“掩模”。某些IC卡可以具有8-位对称密钥(基于文件)EEPROM以及使用数学协处理器加密的8、16和32-位公开密钥。IC卡操作系统或芯片操作系统可以包括固定文件结构或具有不同的加密能力(如对称密钥或非对称密钥(公开密钥))的动态应用系统。某些卡具有高达八千字节的RAM和346千字节的ROM和256千字节的可编程ROM以及16-位微处理器。这些值可以取决于卡设计而变化。
通常，如图2中所示的形成这多个IC卡触点16的接触层18具有大约一平方厘米(0.16平方英寸)的接触面积作为形成在铜接触层上方的八个镀金接触焊盘。如图1中所示的IC卡10的矩形尺寸通常与常规信用卡的那些矩形尺寸相似。例如，ISO/IEO 7810标准的ID-1将IC卡限定在大于85.60×53.98毫米(3.370英寸×2.125英寸)。IC卡10的另一个普遍尺寸是ID-000，其标称为大约25×15毫米(0.984英寸×0.591英寸)并且常用于SIM卡中。通常，IC卡大约0.76毫米(0.030英寸)厚。这些值当然可以取决于IC卡设计要求而变化。通常，存在防篡改安全系统(如安全密码处理器)和安全文件系统。
当IC卡10被插入到读卡器中时，金属焊盘(即，IC卡触点16)与读卡器接触并且与读卡器中的金属销相连接，从而允许卡和读卡器进行通信。当IC卡10插入到读卡器中时，该卡被复位，从而引起IC卡以发送“复位应答”(ATR)消息来进行响应，该消息通知读卡器控制事务的通信和处理。
图3是与图1和图2中所示的IC卡类似的常规IC卡10的局部截面图，并且示出了IC卡本体12和该本体所承载的IC模块14。IC模块14包括前述形成处于并排关系的多个IC卡触点16的接触层18。接触层18通常由铜形成，但可以使用其他导电材料。经常，薄金箔层附接至铜上以形成每个IC卡触点16的外表面。
电介质支撑层20位于接触层18上方并且包括如展示的多个开口22。这些开口22经常被本领域的技术人员称为接线键合窝。图5中示出了作为开口22的接线键合窝的示例，该图在本示例中展示了六个开口用于六个触点C1-C3和C5-C7，而没有示出如图2中所示的辅助触点C4和C8。在电介质支撑层20下方展示了接触层18，并且IC裸片24定位在该电介质支撑层上方。在本示例中，电介质支撑层20由E-玻璃形成，在许多示例中，该玻璃是碱性氧化物小于1％至2％w/w的硼硅酸铝玻璃。该玻璃因为其初始电气应用而被认为是“E”型玻璃并且基本上是无碱的，尽管其可能在某种程度上易 受到氯离子侵蚀。E-玻璃不熔化，但变软。因为通常与IC模块14一起使用的E-玻璃类型，其具有低至大约60PPM/℃到高达大约200PPM/℃的热膨胀系数(CTE)。
第一粘合层26(如环氧化物粘合剂，作为非限制性示例)位于接触层18与电介质支撑层20之间以将接触层18粘附于该电介质支撑层上。电介质支撑层20还被称为“带”，因为其经常作为薄片应用，与带类似。IC裸片24位于电介质支撑层20上方，并且第二粘合层28(如环氧化物层)位于电介质支撑层20与IC裸片24之间并且将该IC裸片粘附于该电介质支撑层上。如所展示的，IC裸片24在上表面32上包括多个键合焊盘30。展示了该多条键合接线34，并且每条键合接线从对应的键合焊盘30延伸穿过电介质支撑层20中的相邻开口22到达相应的触点16。通常，键合接线34通过到键合焊盘30上的“球式”键合36和通过“针脚式”键合38(又被称为楔形键合)穿过电介质支撑层20中的相邻开口22连接至相应的IC卡触点16。针脚式键合38通常是使用超声接线键合工艺将细键合接线焊接至电镀引线框柱或“指状物”上并且可以包括接线到下面的键合表面的压缩或超声键合区域。
球式键合工艺通常包括由金、铜或钯制成的并且直径通常从15-50um的键合接线。实际直径将取决于接线长度、器件功率和接线环路高度以及特定于IC卡设计的其他因素。接线键合工艺对位于IC裸片24的上表面上的键合焊盘30使用球式键合工艺并且需要首先在键合接线的一端形成球并且然后将所形成的那个球焊接到键合焊盘30上。键合接线34横跨IC裸片24的顶部结环并且进入电介质支撑层20中的相邻开口22中。针脚式键合工艺将键合接线34键合至相应的IC卡触点16上。针脚式键合38通常具有与键合接线的直径相关的特殊针脚宽度，并且在一个示例中，典型的最小要求键合面积测量针对15um接线直径大约是90×90um，并且针对50um接线直径大约是300×300um，并且针对25um接线直径大约是150×150um。
如图3中所示，模具化合物本体50位于电介质支撑层20上方并且包围IC裸片24并且形成IC模块14。通常，模具化合物本体50由环氧化物形成并且可以包括非熔化无机材料的填充物和加速固化反应的催化剂。最终的模具材料还可以包括颜料或着色剂并且包括阻燃剂、助粘剂、离子阱和应力减轻剂。环氧化物模具化合物本体中许多包括熔融石英。这些不同组成部分(包括填充物)被选择为减少模具化合物的热膨胀系数(CTE)并且最小化或减小内部应力。增加填充物填载(如熔融石英)通常减小CTE，因为熔融石英的CTE是环氧化物的大约10％。因为增加填充物含量可能降低模具化合物材料的流动和模量，环氧化物可以包括多种配方来通过降低聚合物熔化粘性来保持流动和模量。环氧化物和填充物含量可以基于所期望的芯片设计、封装设计、模具工艺、测试要求和配方来选择。模具化合物本体中的形成IC裸片的封料的某些模具化合物本体基于甲酚醛环氧化物与酚醛环氧化物的反应。环氧化物将使许多高张力合成表面变湿并且形成到金属氧化物的强力、稳定键合。这种类型的模具化合物本体50不仅良好地粘附于IC裸片24上，而且还良好地粘附于由E-玻璃形成的电介质支撑层20上和由铜形成的接触层18上。模具化合物主体50可以具有通常低于大约50PPM/℃的热膨胀系数，并且因此范围可以从大约3或5PPM/℃到高达大约50PPM/℃。电介质支撑层20通常具有比模具化合物主体50大得多的热膨胀系数，并且模具化合物本体与IC卡触点16之间在电介质支撑层处在开口22中可能发生脱层。因为模具复合物本体50与电介质支撑层20之间在如图3中的竖直箭头A所示的Z方向上存在热失配，所以针脚式键合可能削弱。
如所展示的，电介质支撑层20具有从模具化合物本体50的相邻部分横向地向外延伸的多个周边部分52。这些部分52帮助将IC模块14定位和支撑在例如图5中所示形成在IC卡本体12中的IC卡模块接纳区域54中。为了帮助相对于IC卡本体12保持IC模块14，热熔性粘合剂56可以被定位在从模具化合物本体50的相邻部 分横向地向外延伸的周边部分52与IC卡本体12之间。可以使用其他材料，但已经发现热熔性粘合剂是有利的。
为了减轻模具化合物本体与形成在接触层处的IC卡触点之间的应力，根据非限制性实施例，对应的填料本体位于电介质支撑层中的每个开口中以帮助减轻如图4中所展示的这些应力。填料本体将对应的开口填充至与电介质支撑层的相邻部分齐平的水平。为了描述目的，赋予图4中所展示的IC卡多个100系列的参考数字，其中那些常见元件具有与图3中引用的较低数字系列相同的100系列。
图4中所展示的，根据填料的非限制性示例，IC卡110包括IC卡本体112和由其承载的IC模块114，并且该IC模块包括多个触点116和接触层118以及具有多个开口122的电介质支撑层120，这些开口形成被称为接线键合窝的事物。IC裸片124位于电介质支撑层120上方并且在其上表面上132上包括多个IC键合焊盘130，其中键合接线134从对应的键合焊盘延伸穿过电介质支撑层120中的相邻开口122到达相应的IC卡触点116。对应的填料本体在160进行了展示，位于电介质支撑层120中的每个开口122内。每个填料本体160具有大约70到大约200的第二CTE。此CTE与电介质支撑层120(具有大约60至200PPM/℃的CTE)的第一CTE类似或者与接近于模具化合物150的第三CTE相比更接近于该第一CTE，如以上解释的，该第三CTE通常要低得多(例如，3到50PPM/℃)。模具化合物150位于电介质支撑层120和填料本体160上方并且包围IC裸片124，并且此模具化合物150具有第三CTE。第一CTE与接近于第三CTE相比更接近于第二CTE。在从模具化合物本体150的相邻部分横向地向外延伸的周边部分152与IC卡本体122之间还包括第一粘合层126和第二粘合层128以及热熔性粘合剂156。
位于电介质支撑层120中的每个开口122内的对应的填料本体160可以由具有不同填充物的粘合剂形成，以产生更接近于该电介质支撑层的热膨胀系数并且可以具有类似范围的热膨胀系数。例如，该热膨胀系数范围可以从大约70到大约200。结果是，触点116处 的应力更低，同时还减小裸片应力，因为键合接线134可以不受牵拉，从而允许IC模块114的和还有相对于IC卡110的更大的稳定性。
图5是图3的一部分的透视图，示出了接触层18和电介质支撑层20并且展示了电介质支撑层中的形成接线键合窝并且形成图3的示例中的模具化合物本体50与接触层18之间的接口的多个开口22，其中每个开口之内没有填料而仅有模具化合物本体。
图6和图7展示了现有技术的模拟结果，其中图6中的结果与当模具化合物本体50包封IC裸片24并且延伸进入形成接线键合窝的电介质支撑层开口22中时相对应。这些结果示出了接触层18中的IC卡触点16的周边边缘上的高剥离应力16.5MPa。图7示出了根据本发明当填料本体160在图4中的每个开口122内延伸时的模拟结果，并且示出了在开口中使用填料代替模具化合物本体时仅4.6MPa的减小应力。为了说明目的，不同应力被标记为从最低-4.153 A直至最高16.475MPa I并且示出了应力区域。
另一方面涉及一种可以包括IC卡本体和由其承载的IC卡集成电路(IC)模块的IC卡。又另一个方面针对一种用于制作IC卡的集成电路(IC)模块的方法。该方法可以包括：形成接触层，该接触层具有处于并排关系的多个IC卡触点，并且在该接触层上方形成电介质支撑层，该电介质支撑层具有在其中的多个开口，该电介质支撑层具有第一热膨胀系数(CTE)。该方法可以包括对IC裸片进行定位，该IC裸片位于该电介质支撑层上方并且包括在该IC裸的上表面上的多个键合焊盘。该方法可以进一步包括将多条键合接线耦接至这些IC卡触点，每条键合接线从对应的键合焊盘延伸穿过该电介质支撑层中的相邻开口到达相应的触点。该方法还可以包括在该电介质支撑层中的每个开口之内形成对应的填料本体，每个填料本体具有第二CTE。该方法还可以包括形成位于该电介质支撑层、这些填料本体上方并且包围该IC的模具化合物本体。该模具化合物本体具有第三CTE。第一CTE可以与接近于第三CTE相比更接近于 第二CTE。
本发明的许多修改和其他实施例对于受益于前面的描述和附图中呈现的教导的本领域技术人员来说将是显而易见的。因此，应当理解本发明不限于所披露的具体实施例，并且那些修改及实施例旨在被包括于所附权利要求书的范围内。

Claims (24)

1.一种用于IC卡的集成电路(IC)模块，所述模块包括：
接触层，所述接触层包括处于并排关系的多个IC卡触点；
电介质支撑层，所述电介质支撑层位于所述接触层上方并且具有在所述电介质支撑层中的多个开口，所述电介质支撑层具有第一热膨胀系数(CTE)；
IC裸片，所述IC裸片位于所述电介质支撑层上方并且包括在所述IC裸片的上表面上的多个键合焊盘；
多条键合接线，每条键合接线从对应的键合焊盘延伸穿过所述电介质支撑层中的相邻开口到达相应的触点；
对应的填料本体，所述对应的填料本体在所述电介质支撑层中的每个开口之内，每个填料本体具有第二CTE；以及
模具化合物本体，所述模具化合物本体位于所述电介质支撑层、所述填料本体上方并且包围所述IC裸片，所述模具化合物本体具有第三CTE；
所述第一CTE与接近于所述第三CTE相比更接近于所述第二CTE。
2.根据权利要求1所述的IC模块，其中，所述第一CTE在60至200PPM/℃的范围内。
3.根据权利要求1所述的IC模块，其中，所述第二CTE在70至200PPM/℃的范围内。
4.根据权利要求1所述的IC模块，其中，所述第三CTE在3至50PPM/℃的范围内。
5.根据权利要求1所述的IC模块，其中，每个填料本体将对应的开口填充至与所述电介质支撑层的相邻部分齐平的水平。
6.根据权利要求1所述的IC模块，其中，所述电介质支撑层具有从所述模具化合物本体的相邻部分横向地向外延伸的多个周边部分。
7.根据权利要求1所述的IC模块，其中，所述电介质支撑层包括E-玻璃。
8.根据权利要求1所述的IC模块，其中，所述接触层包括铜。
9.根据权利要求1所述的IC模块，其中，所述模具化合物包括环氧化物。
10.根据权利要求1所述的IC模块，进一步包括位于所述接触层与所述电介质支撑层之间的第一粘合层。
11.根据权利要求1所述的IC模块，进一步包括位于所述电介质支撑层与所述IC裸片之间的第二粘合层。
12.一种集成电路(IC)卡，包括：
IC卡本体和由所述IC卡本体承载的集成电路(IC)模块；
所述IC模块包括
接触层，所述接触层包括处于并排关系的多个IC卡触点，
电介质支撑层，所述电介质支撑层位于所述接触层上方并且具有在所述电介质支撑层中的多个开口，所述电介质支撑层具有第一热膨胀系数(CTE)，
IC裸片，所述IC裸片位于所述电介质支撑层上方并且包括在所述IC裸片的上表面上的多个键合焊盘，
多条键合接线，每条键合接线从对应的键合焊盘延伸穿过所述电介质支撑层中的相邻开口到达相应的触点，
对应的填料本体，所述对应的填料本体在所述电介质支撑层中的每个开口之内，每个填料本体具有第二CTE，以及
模具化合物本体，所述模具化合物本体位于所述电介质支撑层、所述填料本体上方并且包围所述IC裸片，所述模具化合物本体具有第三CTE，
所述第一CTE与接近于所述第三CTE相比更接近于所述第二CTE。
13.根据权利要求12所述的IC卡，其中，所述第一CTE在60至200PPM/℃的范围内。
14.根据权利要求12所述的IC卡，其中，所述第二CTE在70至200PPM/℃的范围内。
15.根据权利要求12所述的IC卡，其中，所述第三CTE在3至50PPM/℃的范围内。
16.根据权利要求12所述的IC卡，其中，每个填料本体将对应的开口填充至与所述电介质支撑层的相邻部分齐平的水平。
17.根据权利要求12所述的IC卡，其中，所述电介质支撑层具有从所述模具化合物本体的相邻部分横向地向外延伸的多个周边部分。
18.根据权利要求12所述的IC卡，其中，所述电介质支撑层包括E-玻璃，所述接触层包括铜并且所述模具化合物包括环氧化物。
19.一种用于制作IC卡的集成电路(IC)模块的方法，所述方法包括：
形成接触层，所述接触层包括处于并排关系的多个IC卡触点，
形成电介质支撑层，所述电介质支撑层位于所述接触层上方并且具有在所述电介质支撑层中的多个开口，所述电介质支撑层具有第一热膨胀系数(CTE)；
对IC裸片进行定位，所述IC裸片位于所述电介质支撑层上方并且包括在所述IC裸片的上表面上的多个键合焊盘；
将多条键合接线耦接至所述IC卡触点，每条键合接线从对应的键合焊盘延伸穿过所述电介质支撑层中的相邻开口到达相应的触点；
形成对应的填料本体，所述对应的填料本体在所述电介质支撑层中的每个开口之内，每个填料本体具有第二CTE；以及
形成模具化合物本体，所述模具化合物本体位于所述电介质支撑层、所述填料本体上方并且包围所述IC裸片，所述模具化合物本体具有第三CTE；
所述第一CTE与接近于所述第三CTE相比更接近于所述第二CTE。
20.根据权利要求19所述的方法，其中，所述第一CTE在60至200PPM/℃的范围内。
21.根据权利要求19所述的方法，其中，所述第二CTE在70至200PPM/℃的范围内。
22.根据权利要求19所述的方法，其中，所述第三CTE在3至50PPM/℃的范围内。
23.根据权利要求19所述的方法，其中，每个填料本体被形成用于将对应的开口填充至与所述电介质支撑层的相邻部分齐平的水平。
24.根据权利要求19所述的方法，其中，所述电介质支撑层被形成为具有从所述模具化合物本体的相邻部分横向地向外延伸的多个周边部分。
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Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
US9449912B1 (en) * 2015-06-11 2016-09-20 Stmicroelectronics Pte Ltd Integrated circuit (IC) card having an IC module and reduced bond wire stress and method of forming
US20170287838A1 (en) * 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
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US11088087B2 (en) * 2018-07-25 2021-08-10 Stmicroelectronics, Inc. Micro module with a support structure
USD930000S1 (en) * 2018-10-12 2021-09-07 Huawei Technologies Co., Ltd. Memory card
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222510A1 (en) * 2003-03-24 2004-11-11 Akiyoshi Aoyagi Semiconductor device, semiconductor pack age, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device
CN201548983U (zh) * 2009-11-13 2010-08-11 中电智能卡有限责任公司 一种新型接触式智能卡模块
CN205750831U (zh) * 2015-06-11 2016-11-30 意法半导体(马耳他)有限公司 用于集成电路卡的集成电路模块和集成电路卡

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729433A (en) 1996-01-30 1998-03-17 Micromodule Systems, Inc. Multiple chip module assembly for top of mother board
FR2761497B1 (fr) 1997-03-27 1999-06-18 Gemplus Card Int Procede de fabrication d'une carte a puce ou analogue
JP2002026198A (ja) * 2000-07-04 2002-01-25 Nec Corp 半導体装置及びその製造方法
WO2004105133A1 (en) 2003-05-26 2004-12-02 Axalto Sa Wire bonding on in-line connection pads
US20110278638A1 (en) * 2008-03-25 2011-11-17 Lin Charles W C Semiconductor chip assembly with post/dielectric/post heat spreader
US7808100B2 (en) * 2008-04-21 2010-10-05 Infineon Technologies Ag Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element
JP2013122957A (ja) * 2011-12-09 2013-06-20 Dexerials Corp 接続方法、接続構造体、絶縁性接着部材、及び、接着部材付電子部品及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222510A1 (en) * 2003-03-24 2004-11-11 Akiyoshi Aoyagi Semiconductor device, semiconductor pack age, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device
CN201548983U (zh) * 2009-11-13 2010-08-11 中电智能卡有限责任公司 一种新型接触式智能卡模块
CN205750831U (zh) * 2015-06-11 2016-11-30 意法半导体(马耳他)有限公司 用于集成电路卡的集成电路模块和集成电路卡

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US9449912B1 (en) 2016-09-20
CN205750831U (zh) 2016-11-30

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