CN106227286A - A kind of non-bandgap non-resistance CMOS a reference source - Google Patents

Abstract

The invention belongs to Analogical Circuit Technique field, be specifically related to a kind of non-bandgap non-resistance CMOS a reference source.The a reference source of the present invention is without extra start-up circuit, after power supply electrifying, reference voltage is set up voluntarily, it is not necessary to the CMOS a reference source of diode or BJT and resistance, and this reference source framework can reject the impact on output reference voltage precision of the nonlinear temperature items such as mobility simultaneously.

Description

A kind of non-bandgap non-resistance CMOS a reference source

Technical field

The invention belongs to Analogical Circuit Technique field, be specifically related to a kind of non-bandgap non-resistance CMOS a reference source.

Background technology

Voltage-reference is the very important ingredient of Analogous Integrated Electronic Circuits or composite signal integrated circuits field.Its Effect is to provide a reference voltage not changed with temperature and supply voltage.

Voltage reference circuit ripe now generally uses the band-gap reference framework being made up of audion and resistance.For band A lot of corrective measures of gap a reference source framework have been suggested.Band gap reference framework circuit can provide one non- The most stable and high-precision reference source.But popularization and the further raising of chip integration, the band gap base along with low-power consumption application The problems such as the large area of quasi-source circuit self and high power consumption are difficult to adapt therewith.For these problems, CMOS reference source circuit It is suggested.One core concept of CMOS a reference source is the current collection with the metal-oxide-semiconductor simulation audion working in subthreshold region Relation between electrode current and base emitter voltage, obtains a positive temperature voltage.But most CMOS a reference source is carried out Effect have ignored the impact on reference voltage precision of the temperature coefficient of the nonlinear temperature items such as mobility when simulating.

Summary of the invention

To be solved by this invention, it is simply that for the problems referred to above, a kind of diode or BJT and resistance of need not is proposed CMOS a reference source, this reference source framework can reject the nonlinear temperature items such as the mobility shadow to output reference voltage precision simultaneously Ring.

The technical scheme is that a kind of non-bandgap non-resistance CMOS a reference source, including the first PMOS MP1, second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the first NMOS tube MN1, the second NMOS tube MN2, Three NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and current source；One termination of current source Power supply, the drain electrode of another termination the 6th NMOS tube MN6；The grid of the 6th NMOS tube MN6 and drain interconnection, its source ground；The The drain electrode of three NMOS tube MN3 connects the drain electrode of the 5th PMOS MP5, and the grid of the 3rd NMOS tube MN3 connects the leakage of the 6th NMOS tube MN6 Pole, the source ground of the 3rd NMOS tube MN3；The source electrode of the 4th PMOS MP4 connects voltage, and its grid connects the 5th PMOS MP5 Drain electrode；The source electrode of the 5th PMOS MP5 connects the drain electrode of the 4th PMOS MP4, and the grid of the 5th PMOS MP5 connects the 6th PMOS The drain electrode of MP；The source electrode of the 6th PMOS MP connects the drain electrode of the 5th PMOS MP5, and the grid of the 6th PMOS MP and six grades are mutually Even；The drain electrode of the second NMOS tube MN2 connects the drain electrode of the 6th PMOS MP, the leakage connecing the 6th NMOS tube MN6 of the second NMOS tube MN2 Pole, the source ground of the second NMOS tube MN2；The source electrode of the 3rd PMOS MP connects power supply, and the grid of the 3rd PMOS MP connects the 4th The drain electrode of PMOS MP4；The drain electrode of the first NMOS tube MN1 connects the source electrode of the 3rd PMOS MP, and the source electrode of the first NMOS tube MN1 connects Ground；The source electrode of the second PMOS MP2 connects power supply, and the grid of the second PMOS MP2 connects the drain electrode of the 4th PMOS MP4；First The source electrode of PMOS MP1 connects the drain electrode of the second PMOS MP2, the grid of the first PMOS MP1 and grounded drain；7th PMOS The source electrode of MP7 connects power supply, its grid and drain interconnection；The drain electrode of the 4th NMOS tube MN4 connects the drain electrode of the 7th PMOS MP7, the The grid of four NMOS tube MN4 connects the drain electrode of the 3rd PMOS MP3, the source ground of the 4th NMOS tube MN4；8th PMOS MP8 Source ground, its grid connects the drain electrode of the 7th PMOS MP7；The source electrode of the 9th PMOS MP9 connects the leakage of the 8th PMOS MP8 Pole, the grid of the 9th PMOS MP9 connects the drain electrode of the second PMOS MP2, the grounded drain of the 9th PMOS MP9；Tenth PMOS The source electrode of pipe MP10 connects the drain electrode of the 8th PMOS MP8, the grid of the tenth PMOS MP10 and drain interconnection；5th NMOS tube The drain electrode of MN5 connects the drain electrode of the tenth PMOS MP10, and the grid of the 5th NMOS tube MN5 connects the drain electrode of the 3rd PMOS MP3, and the 5th The source ground of NMOS tube MN5；The outfan in source on the basis of the drain electrode of the tenth PMOS MP10.

Beneficial effects of the present invention is, it is not necessary to extra start-up circuit, and after power supply electrifying, reference voltage is set up voluntarily, no Needing the CMOS a reference source of diode or BJT and resistance, can to reject the non-thread such as mobility warm in nature for this reference source framework simultaneously The degree item impact on output reference voltage precision.

Accompanying drawing explanation

Fig. 1 is the theory diagram of the non-bandgap non-resistance CMOS a reference source of the present invention；

Fig. 2 is the physical circuit figure of the non-bandgap non-resistance CMOS a reference source of the present invention.

Detailed description of the invention

Below in conjunction with the accompanying drawings, technical scheme is described in detail:

The operation principle of the present invention is as it is shown in figure 1, utilize circuit to produce electric current IB and voltage VB, and wherein electric current IB is proportional to V_TH, and voltage VB is proportional to VTH.

I_B∝μT²

V_B∝V_TH

Electric current IB and voltage VB is combined by recycling circuit shown in Fig. 1, final generation reference voltage V REF.In figure MPQ1 and MPQ2 is operated in saturation region, then have

$V_{SGQ1}=\left|V_{THP}\right|+\sqrt{\frac{2I_{DQ1}}{{\mathrm{\μ}}_p{C}_{ox}{S}_{Q1}}}$

$V_{SGQ2}=\left|V_{THP}\right|+\sqrt{\frac{2I_{DQ2}}{{\mathrm{\μ}}_p{C}_{ox}{S}_{Q2}}}$

Wherein SQ1 and SQ2 is respectively the ratio of wide length of MPQ1 and MPQ2, and two voltages are subtracted each other and can be obtained

V_PTAT=V_SGQ1-V_SGQ2

Because electric current IDQ1 and IDQ2 meets relation, I_DQ1∝μ_pT², I_DQ2∝μ_pT²；So there is V_PTAT∝T。

The voltage of output point REF can be written as

V_REF=V_B+V_PTAT

Wherein V_B∝V_TH, the temperature coefficient of VTH is negative, and VPTAT temperature coefficient is just.Positive temperature voltage and subzero temperature are rationally set The proportionality coefficient of the voltage output voltage VREF that can begin is temperature independent.

Fig. 2 is the physical circuit figure of the present invention, and this circuit comprises 3 parts, and VTH extracts circuit, μ T²Current generating circuit And supercircuit.

PMOS MP4, MP5 and MP6, NMOS tube MN2 and MN3, constitute VTHP and extract the core of circuit.Wherein, The size of MP4, MP5 and MP6 is than for 3:1:1.The size ratio of MN2 and MN3 is 2:1.MP5 is operated in outside linear zone, MP4, MP6, MN3 and MN2 is operated in saturation region.The source-drain voltage VDSP4 of MP4 can be obtained under these conditions

V_DSP4=V_THP

VTHP is the threshold voltage of PMOS.Drain-source (VDS) voltage of MP2 pipe sampling MP4 pipe, now V_SGP2=V_THP。 The grid of MP1 pipe and drain electrode short circuit form diode type of attachment, and size is identical with MP1 pipe.The gate source voltage of MP1 and MP2 (Vgs) equal, all it is operated in sub-threshold region.So, the voltage of A point

V_A=V_THP

The drain-source voltage (VDS) of same MP3 pipe sampling MP4 pipe, and it is operated in sub-threshold region, the leakage of MP3 pipe can be write out Electrode current

$I_{DP3}={\mathrm{\μ}}_p{C}_{ox}{S}_{P3}{V}_T^2{e}^{\frac{V_{SGP3}-V_{THP}}{V_T}}$

SP3 is the ratio of the wide length of MP3 pipe, wherein V_SGP3=V_THP, abbreviation after current is equal to

$I_{DP3}={\mathrm{\μ}}_p{C}_{ox}{S}_{P3}{V}_T^2$

Understand electric current

This electric current is mirrored to electric current supercircuit by current mirror MN1, MN4 and MN5, produces final reference voltage. The size of MN1, MN4 and MN5 is than for 1:1:1.The size of MP7 and MP8 is than for 1:m.The electric current flowing through MP9 and MP10 is

$I_{DP10}={\mathrm{\μ}}_p{C}_{ox}{S}_{P3}{V}_T^2$

$I_{DP9}=(m-1){\mathrm{\μ}}_p{C}_{ox}{S}_{P3}{V}_T^2$

MP9 and MP10 is operated in saturation region simultaneously, then the gate source voltage (VGS) of MP9 and MP10 is equal to

$V_{SGP9}=\left|V_{THP}\right|+V_T\sqrt{\frac{(m-1)S_{P3}}{S_{P9}}}$

$V_{SGP10}=\left|V_{THP}\right|+V_T\sqrt{\frac{S_{P3}}{S_{P10}}}$

Wherein SP9 and SP10 is respectively the breadth length ratio of MP9 and MP10, is subtracted each other by the gate source voltage of MP9 pipe and MP10 pipe, Arrive

$V_{PTAT}=\[\sqrt{\frac{(m-1)S_{P3}}{S_{P9}}}-\sqrt{\frac{S_{P3}}{S_{P9}}}\]\·V_T$

Wherein, VT is thermal voltage, andUnderstand V_T∝T.It will be seen that the mobility in formula is disappeared completely, VPTAT is the single order just temperature voltage of standard.VPTAT with VA voltage is added and obtains reference voltage

$V_{PEF}=V_{THP}+\[\sqrt{\frac{(m-1)S_{P3}}{S_{P9}}}-\sqrt{\frac{S_{P3}}{S_{P9}}}\]\·V_T$

By image ratio m and the spaciousness ratio of metal-oxide-semiconductor of regulation current mirror, output voltage VREF can be made temperature independent.

The present invention utilizes threshold V T HP offset operation in the metal-oxide-semiconductor of subthreshold region, obtains electric current I_D∝μT².Profit again It is operated in the metal-oxide-semiconductor of amplification region state with this current offset, obtains a single order PTAT voltage unrelated with mobility [mu].Finally By the subzero temperature amount of this voltage compensation threshold V T HP, finally give reference voltage V REF.This invention is without extra startup electricity Road, after power supply electrifying, reference voltage is set up voluntarily.

Claims (1)

1. a non-bandgap non-resistance CMOS a reference source, including the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, Nine PMOS MP9, the tenth PMOS MP10, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS Pipe MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and current source；One termination power of current source, another terminates the 6th NMOS The drain electrode of pipe MN6；The grid of the 6th NMOS tube MN6 and drain interconnection, its source ground；The drain electrode of the 3rd NMOS tube MN3 connects The drain electrode of five PMOS MP5, the grid of the 3rd NMOS tube MN3 connects the drain electrode of the 6th NMOS tube MN6, the source of the 3rd NMOS tube MN3 Pole ground connection；The source electrode of the 4th PMOS MP4 connects voltage, and its grid connects the drain electrode of the 5th PMOS MP5；5th PMOS MP5 Source electrode connects the drain electrode of the 4th PMOS MP4, and the grid of the 5th PMOS MP5 connects the drain electrode of the 6th PMOS MP；6th PMOS The source electrode of MP connects the drain electrode of the 5th PMOS MP5, the grid of the 6th PMOS MP and six grades of interconnection；The leakage of the second NMOS tube MN2 Pole connects the drain electrode of the 6th PMOS MP, the drain electrode connecing the 6th NMOS tube MN6 of the second NMOS tube MN2, the source of the second NMOS tube MN2 Pole ground connection；The source electrode of the 3rd PMOS MP connects power supply, and the grid of the 3rd PMOS MP connects the drain electrode of the 4th PMOS MP4；First The drain electrode of NMOS tube MN1 connects the source electrode of the 3rd PMOS MP, the source ground of the first NMOS tube MN1；The source of the second PMOS MP2 Pole connects power supply, and the grid of the second PMOS MP2 connects the drain electrode of the 4th PMOS MP4；The source electrode of the first PMOS MP1 connects second The drain electrode of PMOS MP2, the grid of the first PMOS MP1 and grounded drain；The source electrode of the 7th PMOS MP7 connects power supply, its grid Pole and drain interconnection；The drain electrode of the 4th NMOS tube MN4 connects the drain electrode of the 7th PMOS MP7, and the grid of the 4th NMOS tube MN4 connects The drain electrode of three PMOS MP3, the source ground of the 4th NMOS tube MN4；The source ground of the 8th PMOS MP8, its grid connects The drain electrode of seven PMOS MP7；The source electrode of the 9th PMOS MP9 connects the drain electrode of the 8th PMOS MP8, the grid of the 9th PMOS MP9 Pole connects the drain electrode of the second PMOS MP2, the grounded drain of the 9th PMOS MP9；The source electrode of the tenth PMOS MP10 connects the 8th The drain electrode of PMOS MP8, the grid of the tenth PMOS MP10 and drain interconnection；The drain electrode of the 5th NMOS tube MN5 meets the tenth PMOS The drain electrode of pipe MP10, the grid of the 5th NMOS tube MN5 connects the drain electrode of the 3rd PMOS MP3, and the source electrode of the 5th NMOS tube MN5 connects Ground；The outfan in source on the basis of the drain electrode of the tenth PMOS MP10.