CN104076856A - Ultra-low-power-consumption non-resistance non-bandgap reference source - Google Patents

Abstract

The invention relates to the field of integrated circuit design, in particular to an ultra-low-power-consumption non-resistance non-bandgap reference source which comprises a current source generation circuit, a threshold voltage extraction circuit, a right-temperature voltage generation circuit and a voltage superposition circuit. The bias voltage of the current source generation circuit is connected with an input end of the threshold voltage extraction circuit, an input end of the right-temperature voltage generation circuit and an input end of the voltage superposition circuit, the output end of the threshold voltage extraction circuit is connected with the other input end of the right-temperature voltage generation circuit and the other input end of the voltage superposition circuit, and the output end of the right-temperature voltage generation circuit and the output end of the voltage superposition circuit output reference voltage. The reference source has the advantage of being capable of generating a reference output voltage which is unchanged along with temperature and input voltage.

Description

A kind of super low-power consumption non-resistance non-bandgap reference source

Technical field

The invention belongs to integrated circuit (IC) design field, be specifically related to a kind of super low-power consumption non-resistance non-bandgap reference source.

Background technology

Reference source is an indispensable module in Analogous Integrated Electronic Circuits chip, in numerous application, playing the part of important role, for generation of not with the voltage reference of supply voltage and temperature variation, for other circuit modules provide a reference voltage, its characteristic affects the performance of whole system to a great extent.

Traditional benchmark source need to be realized by resistance conventionally, but in Standard Digital CMOS, often there is no model or the model unreliable of resistance.In addition,, even if there is resistance in digital technology, because silicide is often used to reduce the square resistance of polysilicon and diffusion layer, make the resistance in reference source need very large area.This has not only increased cost, and has worsened the interference of substrate noise coupling to reference source work.In addition, along with the development of CMOS technique and extensively popularizing of portable electric appts, low pressure and low-power consumption become more and more important, band gap reference is because the large electric current of needs causes power consumption larger, and in design process, need to produce PTAT (Proportional To Absolute Temperature) voltage with diode or BJT pipe, yet these two kinds of devices all need large chip area.

Summary of the invention

Object of the present invention, it is exactly the problem existing for above-mentioned traditional circuit, a kind of super low-power consumption non-resistance non-bandgap reference source is proposed, based on threshold voltage, and utilize threshold voltage and thermal voltage to be stacked Calais with certain proportion coefficient to obtain zero warm benchmark, adopt voltage negative feedback technique to improve the PSRR of circuit simultaneously.

Technical scheme of the present invention is that a kind of super low-power consumption non-resistance non-bandgap reference source, is characterized in that, comprises electric current source generating circuit, V_th generation circuit and positive temperature voltage generation circuit and voltage overlaying circuit; Wherein, the bias voltage that electric current source generating circuit produces is connected respectively to input end of V_th generation circuit and an input end of positive temperature voltage generation circuit and voltage overlaying circuit; The output terminal of V_th generation circuit is connected to another input end of positive temperature voltage generation circuit and voltage overlaying circuit; The output terminal output reference voltage of positive temperature voltage generation circuit and voltage overlaying circuit;

Described electric current source generating circuit comprises PMOS pipe MPS1, MPS2, MP1, MP2, MP3, NMOS pipe MN1, MN2, MN3, MN4, MNC1, NPN pipe Q1, Q2, Q3, and capacitor C S1; Wherein, the source electrode of MPS2 connects power supply, and its drain electrode is by capacitor C S1 ground connection, and its grid is connected the output terminal output offset voltage as electric current source generating circuit with the grid of the grid leak utmost point, the drain electrode of MN1, the grid of MP2 and the MP3 of MP1; The source electrode of MPS1 connects power supply, and its grid connects the tie point of MPS2 and CS1, and its drain electrode connects the grid of MN1; The source electrode of MP1 connects power supply; The source electrode of MN1 connects the collector of Q1; The base stage of Q1 and collector interconnection, its grounded emitter; The source ground of MNC1, its grid connects the drain electrode of MPS1 and the tie point of MN1 grid, its grounded drain; The source electrode of MP2 connects power supply, and its drain electrode connects the drain electrode of MN2; The drain electrode of MN2 and gate interconnection, its grid connects the grid of MN3, and its source electrode connects the drain electrode of MN4; The grid of MN4 connects the grid of MN2 and the tie point of MN3 grid, and its source electrode connects the collector of Q2; The base stage of Q2 and collector interconnection, its grounded emitter; The source electrode of MP3 connects power supply, and its drain electrode connects the drain electrode of MN3; The tie point of MP3 drain electrode and MN3 drain electrode connects the tie point of MN1 grid and MNC1 grid; The source electrode of MN3 connects the collector of Q3; The base stage of Q3 and collector interconnection, its grounded emitter;

Described V_th generation circuit comprises PMOS pipe MP4, MP5, NMOS pipe MN5, MN6, MN7; Wherein, the source electrode of MP4 and the source electrode of MP5 connect power supply, the source ground of MN7 pipe; The grid of MP4 and the grid of MP5 connect the output terminal of electric current source generating circuit; The drain electrode of MN5 and gate interconnection, its grid connects the drain electrode of MP4 and the grid of MN6, and its source electrode is connected with the drain electrode of MN6, the grid of the drain electrode of MP5, MN7; The source electrode of MN6 is connected the output terminal as V_th generation circuit with the drain electrode of MN7;

Described positive temperature voltage generation circuit and voltage overlaying circuit comprise PMOS pipe MP6, MP7, MP8, MP9, and NMOS manages MN8, MN9; Wherein, the source electrode of MP6 and the source electrode of MP7 connect power supply; The grounded drain of the source electrode of MN8, the source electrode of MN9 and MP8; The grid of MP6 and the grid of MP7 connect the output terminal of electric current source generating circuit; The drain electrode of MN8 and gate interconnection, its drain electrode connects the drain electrode of MP6, and its grid connects the grid of MN9; The drain electrode of MP7 connects the tie point of the source electrode of MP8 and the source electrode of MP9; The grid of MP8 connects the output terminal of V_th generation circuit; The drain electrode of MP9 and gate interconnection, the drain electrode that its drain electrode meets MN9 is connected as the output terminal output reference voltage of positive temperature voltage generation circuit and voltage overlaying circuit.

Beneficial effect of the present invention is that super low-power consumption non-resistance non-bandgap reference source of the present invention, utilizes the threshold voltage V with negative temperature coefficient _tHwith the thermal voltage V with positive temperature coefficient (PTC) _tsuperimposed with certain proportion coefficient, thus produce one with temperature and the constant benchmark output voltage of input voltage, adopt voltage negative feedback technique to improve the PSRR of circuit simultaneously.

Accompanying drawing explanation

Fig. 1 is the super low-power consumption non-resistance non-bandgap reference source configuration diagram that the present invention proposes;

Fig. 2 is that current source of the present invention produces circuit diagram;

Fig. 3 is V_th generation circuit diagram of the present invention;

Fig. 4 is positive temperature voltage generation circuit of the present invention and voltage overlaying circuit schematic diagram.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described

Super low-power consumption non-resistance non-bandgap reference source configuration diagram of the present invention as shown in Figure 1, comprises electric current source generating circuit, V_th generation circuit, positive temperature (PTAT) voltage generation circuit and voltage overlaying circuit.The bias voltage V that electric current source generating circuit produces _bbe connected respectively to input end of V_th generation circuit and an input end of positive temperature voltage generation circuit and voltage overlaying circuit; The output terminal V of V_th generation circuit _tHNbe connected to another input end of positive temperature voltage generation circuit and voltage overlaying circuit; The output terminal output reference voltage V of PTAT voltage generation circuit and voltage overlaying circuit _rEF.

As shown in Figure 2, it is managed by 5 PMOS above-mentioned electric current source generating circuit: MPS1, MPS2, MP1, MP2, MP3, and 5 NMOS pipes: MN1, MN2, MN3, MN4, MNC1,3 NPN pipes: Q1, Q2, Q3, and capacitor C S1 forms.Concrete annexation is: the source electrode of MPS2, MPS1, MP1, MP2, MP3 meets supply voltage VDD; The source electrode of the negative end of CS1, the emitter of Q1, MNC1 and drain electrode, the emitter of Q2, the equal earthing potential VSS of the emitter of Q3; The drain electrode of MP1 and grid short circuit, and with the grid of MPS2, the grid end of the grid of MP2, MP3 and the drain electrode of MN1 be connected as the output voltage V of this circuit _b; The drain electrode of MPS2 is connected with the forward end of the grid of MPS1, CS1; The drain electrode of MPS1 is connected with the grid of the grid of MN1, MNC1, the drain electrode of MP3; The drain electrode of MN2 and grid short circuit, and be connected with the drain electrode of MP2, the grid of the grid of MN3, MN4, source electrode is connected with the drain electrode of MN4; The collector of Q1 and base stage short circuit, be connected to the source electrode of MN1; The collector of Q2 and base stage short circuit, be connected to the source electrode of MN4; The collector of Q3 and base stage short circuit, be connected to the source electrode of MN3.

As shown in Figure 3, it is managed by 2 PMOS above-mentioned V_th generation circuit: MP4, MP5,3 NMOS pipes: MN5, MN6, MN7 form.Concrete annexation is: the source electrode of MP4 and the source electrode of MP5 are connected to supply voltage VDD, and the source electrode of MN7 pipe is connected to earth potential VSS; The grid of MP4 is connected external bias voltage signal V with the grid of MP5 _b; The drain electrode of MN5 and grid short circuit, and be connected with the drain electrode of MP4, the grid of MN6, source electrode is connected with the drain electrode of MN6, the grid of the drain electrode of MP5, MN7; The source electrode of MN6 is connected the output voltage V as this circuit with the drain electrode of MN7 _tHN.

As shown in Figure 4, it is by 4 PMOS pipes MP6, MP7, MP8, MP9 for above-mentioned PTAT voltage generation circuit and voltage overlaying circuit, and 2 NMOS pipes MN8, MN9 form.Concrete annexation is: the source electrode of MP6 and the source electrode of MP7 are connected to supply voltage VDD, and the drain electrode of the source electrode of MN8, the source electrode of MN9 and MP8 is connected to earth potential VSS; The grid of MP6 and the grid of MP7 all with external bias voltage V _bbe connected; The drain electrode of MN8 and grid short circuit, and be connected with the drain electrode of MP6, the grid of MN9; The drain electrode of MP7 is connected with the source electrode of the source electrode of MP8, MP9; The grid of MP8 is connected to external threshold voltage signal V _tHN; The drain electrode of MP9 and grid short circuit, and be connected as the output V of reference source with the drain electrode of MN9 _rEF.

In electric current source generating circuit, PMOS pipe MPS1, MPS2 and capacitor C S1 form start-up circuit.The principle of work of start-up circuit is: during chip power, the positive terminal voltage of capacitor C S1 is 0, thereby makes MPS1 conducting, starts the charging to mos capacitance MNC1, and the grid terminal voltage of MN1 slowly rises.When rising to, the gate voltage of MN1 equals the threshold voltage of NMOS pipe and the BE junction voltage sum of triode Q1 (is V _{g_MN1}=V _{tH_NMOS}+ V _{bE_Q1}) time, MN1 conducting, simultaneously also conducting of MP1.The electric current that flows through MN1 and MP1 is gone out by current mirror mirror image, and the current offset of whole reference circuit is set up.Now, MPS2 has electric current to flow through and CS1 is charged, and makes MPS1 enter cut-off region, thereby started until its positive terminal voltage is elevated to, and start-up circuit cuts out, and does not affect the normal work of other circuit modules and also current sinking not.

The utilization of electric current source generating circuit is operated in the NMOS pipe MN4 of linear zone as resistance, converts poor (for PTAT voltage) of BE junction voltage with the triode of the same type of different emitter area to electric current, and this electric current has positive temperature coefficient (PTC).In this circuit, MN4 and MNC1 are operated in linear zone, and all the other metal-oxide-semiconductors are all operated in saturation region.MP2, MP3, MN2, MN3, MN4, Q2 and Q3 form the core circuit of current source, and MP1, MN1 and Q1 are negative feedback parts, are used for steady current, improve the PSRR of circuit, and mos capacitance MNC1 is for stablizing feedback control loop.Write out respectively linear zone and saturation region current formula is as follows:

$I_{N2}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{OX}}{S}_{N2}[2(V_{\mathrm{GS}2}-V_{\mathrm{TH}})V_{\mathrm{DS}2}-V_{\mathrm{DS}2}^2]---\left(1\right)$

$I_{N4}=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{OX}}{S}_{N4}{(V_{\mathrm{GS}4}-V_{\mathrm{TH}})}^2---\left(2\right)$

Wherein, I _nirepresent NMOS pipe M _nidrain current, μ _nelectron mobility, C _oXgate oxide current potential area capacitance, S _nirepresent NMOS pipe M _nibreadth length ratio.

According to the annexation in Fig. 2, the gate source voltage that can obtain MN4 pipe equals the drain-source voltage sum of gate source voltage and the MN4 pipe of MN2 pipe:

V _GS4＝V _GS2+V _DS4 (3)

Because it is identical flowing through the electric current of Q2 and Q3, can obtain again

V _DS4＝V _BE3-V _BE2＝V _Tln N (4)

Wherein, N is Q2 and the ratio of the emitter area of Q3.The electric current that can derive on MN4 according to formula (1), (2), (3), (4) is

$I_{N4}=\frac{{\mathrm{\μ}}_n{C}_{\mathrm{OX}}{S}_{N4}^2}{{2S}_{N2}}{\left(V_T\ln N\right)}^2{(1+\sqrt{1+(S_{N2}/S_{N4})})}^2---\left(5\right)$

In NMOS pipe threshold voltage subtraction circuit, the work of MN6 pipe is in linear zone, and remaining tubing is operated in saturation region.Each parameter can arrange as follows: I _mP5=2I _mP4, 3S _n5=3S _n6=S _n7, S wherein _n5, S _n6, S _n7represent respectively the breadth length ratio of NMOS pipe MN5, MN6, MN7.The drain voltage of MN7 pipe is the threshold voltage V of NMOS pipe _tHN,

V _{D_MN7}＝V _THN (6)

Positive temperature voltage generation circuit and voltage overlaying circuit are realized the generation of positive temperature voltage and the stack of positive subzero temperature voltage simultaneously, as shown in Figure 4.Have

V _THN+V _{SG_MP8}＝V _REF+V _{SG_MP9} (7)

Order

K _i＝μ _pC _OXS _Pi (8)

μ wherein _prepresent hole mobility.

$V_{\mathrm{SG}\_\mathrm{MP}8}=\sqrt{\frac{{2I}_{\mathrm{MP}8}}{K_8}}+V_{\mathrm{THP}}---\left(9\right)$

$V_{\mathrm{SG}\_\mathrm{MP}9}=\sqrt{\frac{{2I}_{\mathrm{MP}9}}{K_9}}+V_{\mathrm{THP}}---\left(10\right)$

So have

$\begin{array}{c}{V}_{\mathrm{REF}}=V_{\mathrm{THN}}+V_{\mathrm{SG}\_\mathrm{MP}8}-V_{\mathrm{SG}\_\mathrm{MP}9}\\ =V_{\mathrm{THN}}+\sqrt{\frac{{2I}_{\mathrm{MP}8}}{K_8}}-\sqrt{\frac{{2I}_{\mathrm{MP}9}}{K_9}}\end{array}---\left(11\right)$

By (5) formula substitution (11), obtain

V _REF＝V _THN+BV _T(12)

Wherein

$B=(\sqrt{\frac{{\mathrm{\μ}}_n}{2{\mathrm{\μ}}_p{S}_{N2}{S}_{P8}}}-\sqrt{\frac{{\mathrm{\μ}}_n}{2{\mathrm{\μ}}_p{S}_{N2}{S}_{P9}}})(1+\sqrt{1+(S_{N2}/S_{N4})})S_{N4}\ln N---\left(13\right)$

Can see reference voltage V _rEFv in formula _tfor the voltage of linear positive temperature coefficient (PTC), V _tHNvoltage for linear negative temperature coefficient; Ignore μ _nand μ _pthe difference of temperature coefficient, B is temperature independent amount.Therefore by regulating breadth length ratio and the Q2 of MN2, MN4, MP8, MP9 can finally make with the ratio of the emitter area of Q3 therefore obtain the benchmark output voltage irrelevant with temperature variation.

Claims (1)

1. a super low-power consumption non-resistance non-bandgap reference source, is characterized in that, comprises electric current source generating circuit, V_th generation circuit and positive temperature voltage generation circuit and voltage overlaying circuit; Wherein, the bias voltage that electric current source generating circuit produces is connected respectively to input end of V_th generation circuit and an input end of positive temperature voltage generation circuit and voltage overlaying circuit; The output terminal of V_th generation circuit is connected to another input end of positive temperature voltage generation circuit and voltage overlaying circuit; The output terminal output reference voltage of positive temperature voltage generation circuit and voltage overlaying circuit;

Described electric current source generating circuit comprises PMOS pipe MPS1, MPS2, MP1, MP2, MP3, NMOS pipe MN1, MN2, MN3, MN4, MNC1, NPN pipe Q1, Q2, Q3, and capacitor C S1; Wherein, the source electrode of MPS2 connects power supply, and its drain electrode is by capacitor C S1 ground connection, and its grid is connected the output terminal output offset voltage as electric current source generating circuit with the grid of the grid leak utmost point, the drain electrode of MN1, the grid of MP2 and the MP3 of MP1; The source electrode of MPS1 connects power supply, and its grid connects the tie point of MPS2 and CS1, and its drain electrode connects the grid of MN1; The source electrode of MP1 connects power supply; The source electrode of MN1 connects the collector of Q1; The base stage of Q1 and collector interconnection, its grounded emitter; The source ground of MNC1, its grid connects the drain electrode of MPS1 and the tie point of MN1 grid, its grounded drain; The source electrode of MP2 connects power supply, and its drain electrode connects the drain electrode of MN2; The drain electrode of MN2 and gate interconnection, its grid connects the grid of MN3, and its source electrode connects the drain electrode of MN4; The grid of MN4 connects the grid of MN2 and the tie point of MN3 grid, and its source electrode connects the collector of Q2; The base stage of Q2 and collector interconnection, its grounded emitter; The source electrode of MP3 connects power supply, and its drain electrode connects the drain electrode of MN3; The tie point of MP3 drain electrode and MN3 drain electrode connects the tie point of MN1 grid and MNC1 grid; The source electrode of MN3 connects the collector of Q3; The base stage of Q3 and collector interconnection, its grounded emitter;

Described V_th generation circuit comprises PMOS pipe MP4, MP5, NMOS pipe MN5, MN6, MN7; Wherein, the source electrode of MP4 and the source electrode of MP5 connect power supply, the source ground of MN7 pipe; The grid of MP4 and the grid of MP5 connect the output terminal of electric current source generating circuit; The drain electrode of MN5 and gate interconnection, its grid connects the drain electrode of MP4 and the grid of MN6, and its source electrode is connected with the drain electrode of MN6, the grid of the drain electrode of MP5, MN7; The source electrode of MN6 is connected the output terminal as V_th generation circuit with the drain electrode of MN7;

Described positive temperature voltage generation circuit and voltage overlaying circuit comprise PMOS pipe MP6, MP7, MP8, MP9, and NMOS manages MN8, MN9; Wherein, the source electrode of MP6 and the source electrode of MP7 connect power supply; The grounded drain of the source electrode of MN8, the source electrode of MN9 and MP8; The grid of MP6 and the grid of MP7 connect the output terminal of electric current source generating circuit; The drain electrode of MN8 and gate interconnection, its drain electrode connects the drain electrode of MP6, and its grid connects the grid of MN9; The drain electrode of MP7 connects the tie point of the source electrode of MP8 and the source electrode of MP9; The grid of MP8 connects the output terminal of V_th generation circuit; The drain electrode of MP9 and gate interconnection, the drain electrode that its drain electrode meets MN9 is connected as the output terminal output reference voltage of positive temperature voltage generation circuit and voltage overlaying circuit.