CN106206709A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN106206709A CN106206709A CN201510297332.5A CN201510297332A CN106206709A CN 106206709 A CN106206709 A CN 106206709A CN 201510297332 A CN201510297332 A CN 201510297332A CN 106206709 A CN106206709 A CN 106206709A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- layer
- semiconductor layer
- semiconductor device
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- 229910052738 indium Inorganic materials 0.000 claims abstract description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 23
- 229910002601 GaN Inorganic materials 0.000 description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 7
- 229910002704 AlGaN Inorganic materials 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 150000002472 indium compounds Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
根据一个实施方式，半导体装置包括：第1半导体层，设置在基板上；第2半导体层，设置在所述第1半导体层上，包含掺杂有碳的氮化物半导体；第3半导体层，设置在所述第2半导体层上，包含掺杂有铟的氮化物半导体；以及第4半导体层，设置在所述第3半导体层上，包含带隙比所述第3半导体层大的氮化物半导体。第3半导体层的铟浓度大于1×1018cm－3且小于1×1019cm－3。
Description
相关申请的交叉引用
本申请基于2015年01月21日提出的在先日本专利申请第2015－009596号并要求享受其优先权利益，并且在此通过引用包含其内容的全部。
技术领域
在此说明的实施方式整体上涉及使用化合物半导体的半导体装置。
背景技术
开关电源、变换器等电路中使用开关元件、二极管等功率半导体元件，对于该功率半导体元件而言，要求高耐压以及低导通电阻。耐压与导通电阻之间存在由元件材料决定的权衡(trade off)关系，但通过将氮化物半导体或碳化硅(SiC)等宽带隙半导体作为元件材料来使用，与硅相比能够改善由材料决定的权衡关系，能够实现高耐压化以及低导通电阻化。
使用了GaN或AlGaN等氮化物半导体的元件具有优异的材料特性，因此能够实现高性能的功率半导体元件。特别在具有AlGaN/GaN的异质构造的HEMT(High Electron Mobility Transistor)中，由于在AlGaN层与GaN层的界面产生由极化带来的高浓度的二维电子气，因此能够实现低导通电阻。
发明内容
实施方式提供能够进一步提高迁移率、并且进一步减少电流崩塌的半导体装置。
根据一个实施方式，半导体装置具备：第1半导体层，设置在基板上；第2半导体层，设置在所述第1半导体层上，包含掺杂有碳的氮化物半导体；第3半导体层，设置在所述第2半导体层上，包含掺杂有铟的氮化物半导体；以及第4半导体层，设置在所述第3半导体层上，包含带隙比所述第3半导体层大的氮化物半导体。所述第3半导体层的铟浓度大于1×1018cm－3且小于1×1019cm－3。
根据上述结构的半导体装置，能够提供能够进一步提高迁移率、并且进一步减少电流崩塌的半导体装置。
附图说明
图1是实施方式的半导体装置的截面图。
具体实施方式
以下，参照附图对实施方式进行说明。其中，附图是示意性的或者是概念性的，各附图的尺寸以及比率等不一定必须与现实的结构相同。以下所示的一些实施方式例示了用于将本发明的技术思想具体化的装置以及方法，本发明的技术思想并不是通过构成部件的形状、构造、配置等来确定。另外，以下的说明中，对于具有相同功能以及结构的要素附加相同的附图标记，并仅在必要时进行重复说明。
图1是实施方式的半导体装置1的截面图。半导体装置1是使用作为化合物的氮化物半导体的氮化物半导体装置。此外，半导体装置1是场效应晶体管(FET)，具体而言是高电子迁移率晶体管(HEMT：HighElectron Mobility Transistor)。
基板10由例如以(111)面为主面的硅(Si)基板构成。作为基板10，可以使用碳化硅(SiC)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、砷化镓(GaAs)或蓝宝石(Al2O3)等。此外，作为基板10，也可以使用包含绝缘层的基板。例如，作为基板10，可以使用SOI(SiliconOn Insulator)基板。
缓冲层(第1半导体层)11设置在基板10上。缓冲层11具有对因形成在缓冲层11上的氮化物半导体层的晶格常数与基板10的晶格常数不同而产生的畸变进行缓和、并且对形成在缓冲层11上的氮化物半导体层的结晶性进行控制的功能。缓冲层11例如由AlXGa1－XN(0≤X≤1)构成。
缓冲层11也可以将组分比不同的多个AlXGa1－XN层叠而构成。在将缓冲层11以层叠构造构成的情况下，对层叠构造的组分比进行调整，以使该层叠构造所包含的多个层的晶格常数从夹着缓冲层11的上下层之中的下层的晶格常数向上层的晶格常数变化。本实施方式中，如图1所示，缓冲层11例如由AlGaN层11A和非掺杂GaN层11B的层叠构造构成。非掺杂是指有意地不掺杂杂质，例如，在制造过程等中进入的程度的杂质量是非掺杂的范畴。GaN层11B的厚度例如为1μm左右。
高电阻层(第2半导体层)12设置在缓冲层11上。高电阻层12具有提高半导体装置1的耐压的功能。即，通过设置高电阻层12，与高电阻层12的电阻相应的电压被施加到高电阻层12，因此能够与该电压量相应地提高耐压。高电阻层12的电阻被设定为比缓冲层11的电阻大。高电阻层12由掺杂有碳(C)的AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。本实施方式中，高电阻层12例如由掺杂有碳(C)的GaN(C－GaN)构成。高电阻层12的厚度例如为2μm左右。高电阻层12的电阻根据对半导体装置1而言优选的耐压而被适当设定。
沟道层(第3半导体层)13设置在高电阻层12上。沟道层13是形成晶体管的沟道(电流路径)的层。沟道层13由结晶性良好的(高品质的)氮化物半导体构成。关于沟道层13的具体结构，留待后述。
阻挡层(第4半导体层)14设置在沟道层13上。阻挡层14由AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。阻挡层14由带隙比沟道层13的带隙大的氮化物半导体构成。本实施方式中，阻挡层14例如由非掺杂AlGaN构成。作为阻挡层14的AlGaN层中的Al的组分比例如为0.2左右。阻挡层14的厚度例如为30nm左右。
另外，构成半导体装置1的多个半导体层例如通过使用了MOCVD(Metal Organic Chemical Vapor Deposition)法的外延生长而被依次形成。即，构成半导体装置1的多个半导体层由外延层构成。
在阻挡层14上相互离开地设有源极电极15以及漏极电极16。进而，在阻挡层14上且在源极电极15以及漏极电极16之间，与源极电极15以及漏极电极16离开地设有栅极电极17。
栅极电极17与阻挡层14进行肖特基接合。即，栅极电极17构成为包含与阻挡层14肖特基接合的材料。图1所示的半导体装置1为肖特基势垒型HEMT。作为栅极电极17，例如使用Au/Ni的层叠构造。“/”的左侧表示上层，右侧表示下层。另外，半导体装置1不限定于肖特基势垒型HEMT，也可以是在阻挡层14与栅极电极17之间存在栅极绝缘膜的MIS(Metal Insulator Semiconductor)型HEMT。
源极电极15与阻挡层14进行欧姆接触。同样，漏极电极16与阻挡层14进行欧姆接触。即，源极电极15以及漏极电极16分别构成为包含与阻挡层14进行欧姆接触的材料。作为源极电极15以及漏极电极16，例如使用Al/Ti的层叠构造。
在沟道层13与阻挡层14的异质结构造中，阻挡层14的晶格常数比沟道层13的晶格常数小，因此阻挡层14发生畸变。通过由该畸变带来的压电效应，在阻挡层14内产生压电极化，在沟道层13与阻挡层14的界面附近产生二维电子气(2DEG：two-dimensional electron gas)。该二维电子气成为源极电极15以及漏极电极16间的沟道。并且，通过栅极电极17与阻挡层14的接合而产生的肖特基势垒，能够实现漏极电流的控制。此外，由于二维电子气具有高的电子迁移率，因此半导体装置1能够实现非常快的开关动作。
如上述那样构成半导体装置1。半导体装置1例如为常通型。在半导体装置1导通时，例如栅极电极17被施加0V，源极电极15被施加0V，漏极电极16被施加高电压(例如200V)。此时，在漏极电极16以及源极电极15之间，经由在沟道层13形成的沟道而流过漏极电流。
在半导体装置1截止时，例如栅极电极17被施加负电压(例如－15V)，源极电极15被施加0V，漏极电极16被施加200V。此时，在栅极电极17的下方延伸的耗尽层的厚度得到控制，漏极电流被切断。
(沟道层13的结构)
接着，对沟道层13的具体结构进行说明。沟道层13由GaN(氮化镓)构成。沟道层13的厚度例如为1μm左右。进而，作为沟道层13的GaN层中掺杂有铟(In)。在掺杂有铟(In)的GaN层(In－GaN层)中，其铟浓度被设定为大于1×1018cm－3且小于1×1019cm－3。通过将铟浓度设定为上述条件，能够抑制沟道层13的结晶性恶化。
在MOCVD法中，使GaN材料外延生长时，作为Ga原料而使三甲基镓(TMGa)的碳分子进入结晶，从而结晶内的杂质浓度增大，带隙中的阱密度变高。另外，生长速度越快，TMGa的流量越增加，由碳杂质带来结晶性的恶化越显著。另一方面，在使GaN生长时，通过掺杂铟(In)来降低结晶内的碳浓度，由此提高结晶的表面平坦性。
本实施方式中，为了减少结晶内的碳杂质，在沟道层13中掺杂铟(In)。由此，能够减小沟道层13的碳浓度。具体而言，沟道层13的碳浓度被设定为1×1018cm－3以下。
如以上详细叙述的那样，根据本实施方式，通过在沟道层13中掺杂铟(In)，能够减小沟道层13的碳浓度。由此，能够抑制沟道层13的结晶性恶化。结果，能够进一步提高半导体装置1的迁移率。
此外，由于沟道层13的杂质浓度(即，碳浓度)减小，因此能够减少带隙中的阱。由此，能够进一步减少电流崩塌现象(动作时漏极电流降低的现象)，此外，能够提高沟道层13的耐压。由此，能够提高半导体装置1的动作特性。
本申请说明书中，“层叠”除了相互相接而重叠的情况以外，还包括在中间插入其他层而重叠的情况。此外，“设置在…上”，除了直接相接而设置的情况以外，还包括在中间插入其他层而设置的情况。
说明了本发明的一些实施方式，但这些实施方式是作为例来提示的，并没有要限定发明的范围。这些新的实施方式能够以其他多种形态实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含于发明的范围及主旨，并且包含于权利要求书所记载的发明及其等效范围。
Claims (5)
1.一种半导体装置，其特征在于，具备：
第1半导体层，设置在基板上；
第2半导体层，设置在所述第1半导体层上，包含掺杂有碳的氮化物半导体；
第3半导体层，设置在所述第2半导体层上，包含掺杂有铟的氮化物半导体；以及
第4半导体层，设置在所述第3半导体层上，包含带隙比所述第3半导体层大的氮化物半导体，
所述第3半导体层的铟浓度大于1×1018cm－3且小于1×1019cm－3。
2.如权利要求1所述的半导体装置，其特征在于，
所述第3半导体层的碳浓度为1×1018cm－3以下。
3.如权利要求1或2所述的半导体装置，其特征在于，
所述第3半导体层包含由GaN构成的氮化物半导体。
4.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层包含由AlXInYGa1－(X+Y)N构成的氮化物半导体，其中，0≤X＜1，0≤Y＜1，0≤X+Y＜1。
5.如权利要求3所述的半导体装置，其特征在于，
所述第2半导体层包含由AlXInYGa1－(X+Y)N构成的氮化物半导体，其中，0≤X＜1，0≤Y＜1，0≤X+Y＜1。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015009596A JP2016134565A (ja) | 2015-01-21 | 2015-01-21 | 半導体装置 |
| JP2015-009596 | 2015-01-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106206709A true CN106206709A (zh) | 2016-12-07 |
Family
ID=56408451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510297332.5A Withdrawn CN106206709A (zh) | 2015-01-21 | 2015-06-03 | 半导体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20160211358A1 (zh) |
| JP (1) | JP2016134565A (zh) |
| CN (1) | CN106206709A (zh) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014220407A (ja) * | 2013-05-09 | 2014-11-20 | ローム株式会社 | 窒化物半導体素子 |
| US10256332B1 (en) * | 2017-10-27 | 2019-04-09 | Vanguard International Semiconductor Corporation | High hole mobility transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003179082A (ja) * | 2002-11-07 | 2003-06-27 | Furukawa Electric Co Ltd:The | 高電子移動度トランジスタ |
| US20110241088A1 (en) * | 2009-03-31 | 2011-10-06 | Furukawa Electric Co., Ltd. | Field effect transistor, method of manufacturing field effect transistor, and method of forming groove |
| JP2013038157A (ja) * | 2011-08-05 | 2013-02-21 | Covalent Materials Corp | 化合物半導体基板 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3251046B2 (ja) * | 1992-03-03 | 2002-01-28 | シャープ株式会社 | 化合物半導体の成長方法、化合物半導体発光素子及びその製造方法 |
-
2015
- 2015-01-21 JP JP2015009596A patent/JP2016134565A/ja active Pending
- 2015-06-03 CN CN201510297332.5A patent/CN106206709A/zh not_active Withdrawn
- 2015-08-20 US US14/831,488 patent/US20160211358A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003179082A (ja) * | 2002-11-07 | 2003-06-27 | Furukawa Electric Co Ltd:The | 高電子移動度トランジスタ |
| US20110241088A1 (en) * | 2009-03-31 | 2011-10-06 | Furukawa Electric Co., Ltd. | Field effect transistor, method of manufacturing field effect transistor, and method of forming groove |
| JP2013038157A (ja) * | 2011-08-05 | 2013-02-21 | Covalent Materials Corp | 化合物半導体基板 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20160211358A1 (en) | 2016-07-21 |
| JP2016134565A (ja) | 2016-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11322599B2 (en) | Enhancement mode III-nitride devices having an Al1-xSixO gate insulator | |
| CN107068746B (zh) | Iii族氮化物双向器件 | |
| US10229992B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN102237402B (zh) | 氮化物半导体元件 | |
| US9490324B2 (en) | N-polar III-nitride transistors | |
| JP6049674B2 (ja) | デュアルゲート型ｉｉｉ−ｖ族複合トランジスタ | |
| CN101689570B (zh) | 采用耗尽模式GaN基FET的串叠电路 | |
| JP5793120B2 (ja) | 集積されたダイオードを有するｓｏｉ基板を備える複合半導体装置 | |
| JP5468768B2 (ja) | 電界効果トランジスタ及びその製造方法 | |
| JP6511645B2 (ja) | 窒化物半導体デバイス | |
| JP5383652B2 (ja) | 電界効果トランジスタ及びその製造方法 | |
| US8330187B2 (en) | GaN-based field effect transistor | |
| CN111883588A (zh) | 用于hemt器件的侧壁钝化 | |
| US20120187452A1 (en) | Semiconductor element | |
| US20130221371A1 (en) | Semiconductor device | |
| CN104037212A (zh) | 氮化物半导体元件及其制造方法 | |
| CN105957889A (zh) | 半导体装置 | |
| WO2014050740A1 (ja) | スイッチング素子 | |
| JP2010206125A (ja) | 窒化ガリウム系高電子移動度トランジスタ | |
| CN106206708A (zh) | 半导体装置 | |
| JP2013229458A (ja) | ヘテロ接合電界効果型トランジスタおよびその製造方法 | |
| JP2008053436A (ja) | 半導体素子 | |
| US20150021665A1 (en) | Transistor having back-barrier layer and method of making the same | |
| CN106206709A (zh) | 半导体装置 | |
| JP2010245240A (ja) | ヘテロ接合型電界効果半導体装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20161207 |
|
| WW01 | Invention patent application withdrawn after publication |