CN106100745B - A kind of optical module - Google Patents
A kind of optical module Download PDFInfo
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- CN106100745B CN106100745B CN201610487721.9A CN201610487721A CN106100745B CN 106100745 B CN106100745 B CN 106100745B CN 201610487721 A CN201610487721 A CN 201610487721A CN 106100745 B CN106100745 B CN 106100745B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/27—Arrangements for networking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q11/0067—Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
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Abstract
The embodiment of the present invention be about a kind of optical module, including the first edge triggered flip flop, the second edge triggered flip flop, logic gates and pulse latch cicuit, wherein：First edge triggered flip flop is configured as generating the first signal under clock signal effect to the trigger signal of reception；Second edge triggered flip flop is configured as generating second signal under clock signal effect to the first signal；Logic gates is configured as the first signal and the second signal and carries out logical operation generation pulse signal, and exports the pulse signal when trigger signal generates rising edge or failing edge, to pulse latch cicuit；Pulse latch cicuit is configured as doing latch processing to pulse signal, and interrupt signal is exported to microcontroller under the control of clear interrupt signal.This implementation thereby reduces optical module production cost by configuring foregoing circuit structure in optical module, it can be achieved that trigger signal Edge check.
Description
Technical field
The present invention relates to technical field of photo communication more particularly to a kind of optical modules.
Background technology
Since optical fiber has the characteristics that efficiency of transmission is high, anti-electromagnetic interference capability is strong, it is more and more in modern communications
Using optical fiber into row information transmit.It is active according to whether accessing in the access net that optical communication network is connected to user terminal
Device can be divided into AON (Active Optical Network, active optical network) and PON (Passive Optical
Network, passive optical network), wherein since PON has the characteristics that easy maintenance, is easily installed and is easy to expand, so
To extensive use.
One PON is usually by the OLT (Optical Line Terminal, optical line terminal) positioned at console for centralized control, position
In the ONU (Optical Network Unit, optical network unit) of user terminal and positioned at ODN (Optical between the two
Distribution Network, Optical Distribution Network) it constitutes.In data transmission procedure, each ONU uses TDMA (Time
Division Multiple Access, time division multiple acess) for pattern to OLT transmission uplink signals, uplink signal is operated in burst mould
It is the train of pulse that length and time interval are all different under formula.Due to this discontinuity feature of uplink signal, so, it is
Allow the reception uplink signals of OLT promptly and accurately, is usually internally provided with a trigger signal (Trigger) in OLT, passes through inspection
The trigger signal is surveyed to determine whether there is ONU to send out uplink signal.Specifically, by the way that microcontroller is arranged in OLT optical modules, and
And trigger signal edge sense circuit is set in microcontroller, when the trigger signal edge sense circuit detects that trigger signal is produced
When raw failing edge (or rising edge), then OLT optical modules think will have ONU to send out uplink signal, will carry out luminous power sampling
Prepare.
In conclusion the optical module of trigger signal can be detected for design, customization is needed to have the function of signal edge detection
Microcontroller, but the microcontroller price with signal edge detection function is costly, and then leads to that increased production cost.
Invention content
A kind of optical module is provided in the embodiment of the present invention, to reduce the production cost of optical module.
In order to achieve the above object, the embodiment of the invention discloses following technical solutions：
It provides a kind of optical module according to embodiments of the present invention, including the first edge triggered flip flop, the second edge triggered flip flop, patrols
Gate circuit and pulse latch cicuit are collected, wherein：
The first input end for receiving trigger signal, for receiving clock signal are equipped in first edge triggered flip flop
Two input terminals and output end for exporting the first signal, the first signal are that trigger signal is raw under the action of clock signal
At；
The first input end for receiving the first signal, for receiving clock signal are equipped in second edge triggered flip flop
Two input terminals and output end for exporting second signal, second signal are that the first signal is raw under the action of clock signal
At, the first input end of the second edge triggered flip flop is connect with the output end of the first edge triggered flip flop；
The first input end for receiving the first signal and second for receiving second signal is equipped in logic gates
Input terminal and output end for output pulse signal, pulse signal be the first signal and the second signal by logical operation,
Trigger signal generates rising edge or when failing edge generates, the first input end of logic gates and the first edge triggered flip flop
Output end connection, the second input terminal are connect with the output end of the second edge triggered flip flop；
The first input end for return pulse signal, for receiving clear interrupt signal are equipped in pulse latch cicuit
Two input terminals and output end for exporting interrupt signal, interrupt signal are to do to maintain high level or low electricity to pulse signal
After level state processing, generated under the control of clear interrupt signal, the first input end and logic gates of pulse latch cicuit
Output end connection.
By above technical scheme as it can be seen that in optical module provided in an embodiment of the present invention, first, the first edge triggered flip flop is utilized
Trigger signal in OLT is generated into the first signal under clock signal, while the first signal being existed using the second edge triggered flip flop
Second signal is generated under clock signal；Since the first signal that the second edge triggered flip flop receives is the defeated of the first edge triggered flip flop
Go out signal, and the second edge triggered flip flop and the first edge triggered flip flop use the same clock signal, so, the second trigger phase
Certain Time delay is had for the first edge triggered flip flop, and then second signal relative first signal is delayed a clock week
Phase, the two constitute the signal for having race condition.Then, the first signal and the second signal are input in logic gates and are carried out
Logical operation obtains pulse signal, since the first signal and the second signal are that trigger signal is obtained by synchronizing relay processing,
So the square-wave pulse in the pulse signal is generated when trigger signal generates rising edge or failing edge, and then can utilize
The pulse signal indicates the generation at trigger signal edge.Further, since optical mode microcontroller in the block is typically in passing through
The signal intensity that disconnected mode processing detection arrives is latched so being additionally provided with pulse latch cicuit in optical module by the pulse
Circuit, which does the pulse signal obtained by above-mentioned processing, maintains high level or low level state to handle, while in clear interrupt signal
Control under to microcontroller export interrupt signal, after microcontroller receives the interrupt signal, subsequent luminous power can be executed
Sampling and processing work.So the technical solution provided through the embodiment of the present invention, designs foregoing circuit knot in optical module
Structure reduces the production cost of optical module, it can be achieved that Edge check to trigger signal in OLT.
It should be understood that above general description and following detailed description is only exemplary and explanatory, not
It can the limitation present invention.
Description of the drawings
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the present invention
Example, and be used to explain the principle of the present invention together with specification.
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without having to pay creative labor, other drawings may also be obtained based on these drawings.
Fig. 1 is a kind of structural schematic diagram of optical module provided in an embodiment of the present invention；
Fig. 2 is the signal timing diagram of optical module in Fig. 1 provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another optical module provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another optical module provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another optical module provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of the optical module based on PLA provided in an embodiment of the present invention.
Specific implementation mode
In order to make those skilled in the art more fully understand the technical solution in the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
The every other embodiment that technical staff is obtained without making creative work, should all belong to protection of the present invention
Range.
In digital circuit, when digital level is from the moment meeting that low level (digital " 0 ") saltus step is high level (digital " 1 ")
Rising edge is generated, on the contrary, when digital level is from the moment that high level (digital " 1 ") saltus step is low level (digital " 0 "), then can be produced
Raw failing edge.Since the generation of rising edge and failing edge is all completed in moment, so to detect the variation at signal edge, Ke Yitong
Cross the instruction that the corresponding level change in detection signal edge is generated as signal edge.
In conjunction with above-mentioned thought, the embodiment of the present invention utilizes the phenomenon of competition and risk in logic circuit, provides a kind of optical mode
Block realizes the Edge check to trigger signal in OLT, and as shown in Fig. 1 and Fig. 2 to 5, which touches including the first edge
Send out device, the second edge triggered flip flop, logic gates and pulse latch cicuit.
Specifically, the first edge triggered flip flop, is configured as receiving the clock letter in the trigger signal and microcontroller in OLT
Number, trigger signal is then generated into the first signal under the action of clock signal；Also, it is equipped with and uses in first edge triggered flip flop
In the first input end of reception trigger signal, the second input terminal for receiving clock signal and for exporting the first signal
Output end.
Second edge triggered flip flop is configured as receiving the clock signal in the first signal and microcontroller, then by the first letter
Number generate second signal under the action of clock signal；Also, it is equipped in second edge triggered flip flop for receiving the first signal
First input end, the second input terminal for receiving clock signal and the output end for exporting second signal.Meanwhile
The first input end of second edge triggered flip flop is connect with the output end of the first edge triggered flip flop.
Using above-mentioned first edge triggered flip flop and the second edge triggered flip flop, the first signal and the second signal can be obtained.
The first signal received due to the second edge triggered flip flop is the output signal of the first edge triggered flip flop, and the second edging trigger
Device and the first edge triggered flip flop use the same clock signal, so, the second trigger has relative to the first edge triggered flip flop
Certain Time delay, so second signal relative first signal be delayed a clock cycle, both constitute have race condition
Signal.
Further, logic gates is configured as receiving the first signal and the second signal, then utilizes competition-venture
Principle carries out logical operation to the first signal and the second signal, obtains pulse signal；Also, it is equipped with and uses in the logic gates
In the first input end of the first signal of reception and the second input terminal for receiving second signal and it is used for output pulse signal
Output end.
Meanwhile the first input end of the logic gates is connect with the output end of the first edge triggered flip flop, the second input terminal
It is connect with the output end of the second edge triggered flip flop.Since the first signal and the second signal are that trigger signal is handled by synchronizing relay
It obtains, so square-wave pulse in the pulse signal is generated when trigger signal generates rising edge or failing edge, and then can be with
The generation at trigger signal edge is indicated using the pulse signal.
Pulse latch cicuit is configured as doing the pulse signal that logic gates exports maintaining high level or low level shape
State processing, while under the control of clear interrupt signal interrupt signal is exported to microcontroller.Also, it is equipped in the pulse latch cicuit
It is interrupted for the first input end of return pulse signal, the second input terminal for receiving clear interrupt signal and for exporting
The output end of signal.
Meanwhile the first input end and the output end connection of logic gates, output end and monolithic of the pulse latch cicuit
Data processing unit connection in machine.After microcontroller receives the interrupt signal, subsequent luminous power sampling and place are just executed
Science and engineering is made.
To sum up, using technical solution provided in an embodiment of the present invention, in optical module design foregoing circuit structure, it can be achieved that
To the Edge check of trigger signal, and then reduce the production cost of optical module.
Optionally, in conjunction with above-described embodiment, as shown in Figure 1, being a kind of structure of optical module provided in an embodiment of the present invention
Schematic diagram.
In the optical module, the first edge triggered flip flop 110 and the second edge triggered flip flop 120 are designed as the D that rising edge triggers
Trigger, it is, of course, also possible to select other types of trigger, such as the edge triggered flip flop that failing edge triggers, the present embodiment is not done
It is specific to limit；Logic gates 130 includes reverser 131 and the first AND gate circuit 132；Pulse latch cicuit 140 is high electricity
Flat pulse latch cicuit, including the first OR circuit 141 and the second AND gate circuit 142.
First input end, the second input terminal and output end are equipped in first edge triggered flip flop 110, wherein it is first defeated
Enter end and the second input terminal is respectively used to receive the clock signal in the trigger signal Trigger and microcontroller in OLT；Second side
First input end, the second input terminal and output end are equipped with along trigger 120, the second input terminal is also used for receiving microcontroller
In clock signal.
Meanwhile first edge triggered flip flop 110 output end respectively with the first input end of the second edge triggered flip flop 120, anti-
It is connected to the input terminal of device 131.The output end of reverser 131 is connect with the first input end of the first AND gate circuit 132, the second side
Output end along trigger 120 is connect with the second input terminal of the first AND gate circuit 132.The first of first OR circuit 141 is defeated
Enter end connect with the output end of the first AND gate circuit 132, the second input terminal connect with the output end of the second AND gate circuit 142, is defeated
Outlet is connect with the first input end of the second AND gate circuit 142.It is additionally provided in second AND gate circuit 142 and believes for receiving clear interrupt
Number second output terminal and output end for exporting interrupt signal.
As shown in Fig. 2, for the signal timing diagram of trigger signal edge sense circuit in Fig. 1.First, it is input to the first edge
Trigger signal Trigger in trigger 110 can be sampled at clock signal clk rising edge, and electricity is realized according to sampled result
Level state saltus step, the first signal X of output, and first signal X are trigger signal Trigger under clock signal clk effect
Synchronizing signal；Equally, the first signal X being input in the second edge triggered flip flop 120, can be under the action of clock signal clk
It does synchronization process, exports second signal Y, according to the characteristic of edge triggered flip flop and the connection relation of two edge triggered flip flops, the
Binary signal Y is delayed a clock cycle just compared with the first signal X.Then, the first signal X is input in reverser 131
After progress phase negates, third signal is exportedBy third signalIt is input in the first AND gate circuit 132 with second signal Y
Afterwards, logic and operation, output pulse signal J are carried out1；Due to pulse signal J1It is after being negated by the first signal X phases and the second letter
Number Y carries out what logic and operation obtained, so pulse signal J1High level generate at the failing edge moment of the first signal X,
And then pulse signal J1It is exported after the failing edge of trigger signal Trigger.So foregoing circuit structure, competing using venture-
It strives in principleCondition, the pulse signal J obtained1, trigger signal Trigger failing edges can be used to refer to
It generates, i.e., after trigger signal failing edge, a high level pulse signal can be exported.
Through the above technical solutions, when the failing edge of the trigger signal in OLT arrives, high level pulse latch cicuit meeting
The interrupt signal of a high level is sent to microcontroller, and then realizes the failing edge detection of trigger signal.
Optionally, in conjunction with above-described embodiment, as shown in figure 3, for the knot of another optical module provided in an embodiment of the present invention
Structure schematic diagram.
Detection circuit structure in the present embodiment, compared with the optical module in Fig. 1, difference lies in logic gates 130
Include reverser 133 and the first AND gate circuit 134.The output end of the input terminal of reverser 133 and the second edge triggered flip flop 120
Connection, output end are connect with the first input end of the first AND gate circuit 134；Second input terminal of the first AND gate circuit 134 and
The output end of one edge triggered flip flop 110 connects, the output end of the first AND gate circuit 134 and in high level pulse latch cicuit first
The first input end of OR circuit 141.
Specifically, reverser 133 receives the second signal Y of the second edge triggered flip flop 120 output, to the phase of second signal Y
Position, which negates, generates third signalThen third signal is exported to the first AND gate circuit 134First AND gate circuit 134 receives the
One signal X and third signalTo the first signal X and third signalIt executes and generates pulse signal J with operation2, then to high electricity
Flat pulse latch cicuit output pulse signal J2。
In the present embodiment, due to pulse signal J2It is after being negated by second signal Y phases and the first signal X progress logics
It is obtained with operation, so pulse signal J2High level generate the first signal X rising edge time, and then the pulse believe
Number J2It is exported after the rising edge of trigger signal Trigger.Then, pass through the first OR circuit in high level pulse latch cicuit
141 and second AND gate circuit 142 high level latch operation, finally under the control of clear interrupt signal C, to microcontroller export in
Break signal Q2。
Through the above technical solutions, when the rising edge of the trigger signal in OLT arrives, high level pulse latch cicuit meeting
The interrupt signal of a high level is sent to microcontroller, and then realizes the rising edge detection of trigger signal, in addition, in the present embodiment
Part same as the previously described embodiments can refer to above-described embodiment, and details are not described herein.
Optionally, in conjunction with above-described embodiment, as shown in figure 4, being another trigger signal side provided in an embodiment of the present invention
Along the structural schematic diagram of detection circuit.
Detection circuit structure in the present embodiment, compared with the detection circuit in Fig. 1, difference lies in logic gates
130 include reverser 135 and the first OR circuit 136, and pulse latch cicuit 140 is low level pulse latch cicuit, including the
One AND gate circuit 143 and the second OR circuit 144.
The input terminal of reverser 135 connect with the output end of the first edge triggered flip flop 110, output end and the first OR circuit
136 first input end connection；The output end of second input terminal of the first OR circuit 136 and the second edge triggered flip flop 120 connects
It connects；The first input end of first AND gate circuit 143 connect with the output end of the first OR circuit 136, the second input terminal and second
The output end connection of OR circuit 144, output end are connect with the first input end of the second OR circuit 144；Second OR circuit
The second input terminal for receiving clear interrupt signal and the output end for exporting interrupt signal are additionally provided in 144.
Specifically, reverser 135 receives the first signal X of the first edge triggered flip flop 110 output, to the phase of the first signal X
Position, which negates, generates third signalThen third signal is exported to the first OR circuit 136First OR circuit 136 receives
Third signalThe second signal Y exported with the second edge triggered flip flop 120, to third signalIt executes or transports with second signal Y
It calculates and generates pulse signal J3, then to low level pulse latch cicuit output pulse signal J3.So foregoing circuit structure, utilizes
In venture-competition principleCondition, the pulse signal J obtained3, trigger signal Trigger can be used to refer to
The generation of rising edge can export a low level pulse signal that is, after trigger signal rising edge.Further, in low level
In pulse latch cicuit, 143 return pulse signal J of the first AND gate circuit3With the interrupt signal Q of the second OR circuit 144 output3,
To pulse signal J3With interrupt signal Q3It executes to generate with operation and is used as interrupt notification signal, it is then defeated to the second OR circuit 144
Go out the interrupt notification signal；Second OR circuit 144 receives clear interrupt signal C and interrupt notification signal, to clear interrupt signal C
It is executed with interrupt notification signal or operation generates interrupt signal Q3, interrupted respectively to microcontroller and the output of the first AND gate circuit 143
Signal Q3。
In the present embodiment, due to pulse signal J3It is after being negated by the first signal X phases and second signal Y progress logics
Or operation obtains, so pulse signal J3Low level generate the rising edge time in the first signal X, and then the pulse signal
J3Low level exported after the rising edge of trigger signal Trigger.Then, in low level pulse latch cicuit, first with
143 return pulse signal J of gate circuit3With interrupt signal Q3, according to the principle of logic and operation, which can latch and touch
Signalling J3In low level signal, and using the low level signal as interrupt notification signal be input to the second OR circuit
In 144, the second OR circuit 144 is under the control of clear interrupt signal C to microcontroller output interrupt signal Q3, for example, in clear
When break signal C is low level, as long as pulse signal J3There is low level, the interrupt signal Q of output3Low level can be always maintained at
State, when clear interrupt signal C becomes high level, interrupt signal Q3High level can just be become.
Through the above technical solutions, when the rising edge of the trigger signal in OLT arrives, low level pulse latch cicuit meeting
A low level interrupt signal is sent to microcontroller, and then realizes the rising edge detection of trigger signal, in addition, in the present embodiment
Part same as the previously described embodiments can refer to above-described embodiment, and details are not described herein.
Optionally, in conjunction with above-described embodiment, as shown in figure 5, for the knot of another optical module provided in an embodiment of the present invention
Structure schematic diagram.
Detection circuit structure in the present embodiment, compared with the detection circuit in Fig. 4, difference lies in logic gates
130 include reverser 137 and the first OR circuit 138, the output of the input terminal of reverser 137 and the second edge triggered flip flop 120
End connection, output end connect with the first input end of the first OR circuit 138, the second input terminal of the first OR circuit 138 and
The of first AND gate circuit 143 in the output end connection of first edge triggered flip flop 110, output end and low level pulse latch cicuit
One input terminal connects.
Specifically, reverser 137 receives the second signal Y of the second edge triggered flip flop 120 output, to the phase of second signal Y
Position, which negates, generates third signalThen third signal is exported to the first OR circuit 138First OR circuit 138 receives the
The the first signal X and third signal of one edge triggered flip flop 110 outputTo the first signal X and third signalIt executes or operation is given birth to
At pulse signal, then to 140 output pulse signal J of pulse latch cicuit4。
In the present embodiment, due to pulse signal J4It is after being negated by second signal Y phases and the first signal X progress logics
Or operation obtains, so pulse signal J4Low level generate at the failing edge moment of the first signal X, and then the pulse is believed
Number J4Low level exported after the failing edge of trigger signal Trigger.Then, pass through in low level pulse latch cicuit first
AND gate circuit 143 and the low level of the second OR circuit 144 latch operation, finally under the control of clear interrupt signal C, to monolithic
Machine exports interrupt signal Q4。
Through the above technical solutions, when the failing edge of the trigger signal in OLT arrives, low level pulse latch cicuit meeting
A low level interrupt signal is sent to microcontroller, and then realizes the failing edge detection of trigger signal, wherein in the present embodiment
Part same as the previously described embodiments can refer to above-described embodiment, and details are not described herein.
Structure based on PLA (Programmable Logic Arrays, programmable logic array) unit inside microcontroller
Feature, the present embodiment is additionally provided builds Fig. 1 and Fig. 3 to the circuit structure in the block of optical mode in 5 using microcontroller PLA units,
The mutual connection of selected PLA units is realized especially by the register of configuration microcontroller, and passes through configuration register
Make each PLA units that can realize different logic functions alone.As shown in fig. 6, for it is provided in this embodiment it is corresponding with Fig. 1,
Based on the trigger signal failing edge detection circuit that PLA is built, 5 PLA units are equipped in the detection circuit, wherein the first PLA
Unit 210 and the 2nd PLA units 220 are respectively used to realize the letter of the first edge triggered flip flop 110 and the second edge triggered flip flop 120
Number synchronizing relay processing function；3rd PLA units 230, the signal phase for realizing logic gates 130 negates and logical AND
The function of operation；4th PLA units 240 and the 5th PLA units 250 are respectively used to realize first or door in pulse latch cicuit
The function of the logic and operation of the logic of circuit 141 or operation and the second AND gate circuit 142.
In the present embodiment, PLA units are combined by configuring microcontroller register, the trigger signal detection circuit built,
It realizes to the Edge check of trigger signal, new component need not be configured in microcontroller, and then optical mode can be further decreased
Block production cost.
Further, trigger signal receiving unit, microcontroller crystal oscillator and clear are additionally provided in the optical module in above-described embodiment
Interrupt signal transmission unit, wherein：
Trigger signal receiving unit is connect with the first input end of the first edge triggered flip flop, is received by the trigger signal single
Trigger signal in the OLT received is sent to the first edge triggered flip flop by member；Microcontroller crystal oscillator respectively with the first edging trigger
The second input terminal connection of the second input terminal and the second edge triggered flip flop of device, is touched by the microcontroller crystal oscillator for the first edge
It sends out device and the second edge triggered flip flop provides clock signal；Second input terminal of clear interrupt signal transmission unit and pulse latch cicuit
Connection, clear interrupt signal is provided by the clear interrupt signal transmission unit under the control of microcontroller for pulse latch cicuit.
Those skilled in the art will readily occur to its of the present invention after considering specification and putting into practice the invention invented here
Its embodiment.This application is intended to cover the present invention any variations, uses, or adaptations, these modifications, purposes or
Person's adaptive change follows the general principle of the present invention and includes the common knowledge in the art that the present invention does not invent
Or conventional techniques.The description and examples are only to be considered as illustrative, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be understood that the invention is not limited in the precision architectures for being described above and being shown in the accompanying drawings, and
And various modifications and changes may be made without departing from the scope thereof.The scope of the present invention is limited only by the attached claims.
Claims (10)
1. a kind of optical module, which is characterized in that including the first edge triggered flip flop, the second edge triggered flip flop, logic gates and arteries and veins
Latch cicuit is rushed, wherein：
The first input end for receiving trigger signal, for receiving clock signal are equipped in first edge triggered flip flop
Two input terminals and output end for exporting the first signal, first signal are that the trigger signal is believed in the clock
It is generated under the action of number；
It is equipped with for receiving the first input end of first signal, for receiving the clock in second edge triggered flip flop
Second input terminal of signal and the output end for exporting second signal, the second signal are first signal in institute
It states and generates under the action of clock signal, the first input end of second edge triggered flip flop and first edge triggered flip flop
Output end connects；
The first input end for receiving first signal is equipped in the logic gates and for receiving second letter
Number the second input terminal and output end for output pulse signal, the pulse signal be first signal and described
Second signal by logical operation, generate rising edge in the trigger signal or when failing edge generates, the logic gates
First input end connect with the output end of first edge triggered flip flop, the second input terminal and second edge triggered flip flop
Output end connects；
It is equipped with for receiving the first input end of the pulse signal, for receiving clear interrupt signal in the pulse latch cicuit
The second input terminal and output end for exporting interrupt signal, the interrupt signal be to be maintained to the pulse signal
It after high level or low level state processing, is generated under the control of the clear interrupt signal, the of the pulse latch cicuit
One input terminal is connect with the output end of the logic gates.
2. optical module according to claim 1, which is characterized in that the logic gates includes reverser and first and door
Circuit, the pulse latch cicuit are high level pulse latch cicuit, wherein：
The input terminal of the reverser is connect with the output end of first edge triggered flip flop, output end and described first and door are electric
The first input end on road connects；
Second input terminal of first AND gate circuit is connect with the output end of second edge triggered flip flop, and described first and door
The output end of circuit is connect with the first input end of the high level latch cicuit.
3. optical module according to claim 1, which is characterized in that the logic gates includes reverser and first and door
Circuit, the pulse latch cicuit are high level pulse latch cicuit, wherein：
The input terminal of the reverser is connect with the output end of second edge triggered flip flop, output end and described first and door are electric
The first input end on road connects；
Second input terminal of first AND gate circuit is connect with the output end of first edge triggered flip flop, and described first and door
The output end of circuit is connect with the first input end of the high level latch cicuit.
4. optical module according to claim 2 or 3, which is characterized in that the high level pulse latch cicuit includes first
OR circuit and the second AND gate circuit, wherein：
The first input end of first OR circuit connect with the output end of first AND gate circuit, the second input terminal and institute
State the output end connection of the second AND gate circuit, output end is connect with the first input end of second AND gate circuit；
Second output terminal for receiving clear interrupt signal is additionally provided in second AND gate circuit and for exporting interrupt signal
Output end.
5. optical module according to claim 1, which is characterized in that the logic gates includes reverser and first or door
Circuit, the pulse latch cicuit are low level pulse latch cicuit, wherein：
The input terminal of the reverser is connect with the output end of first edge triggered flip flop, output end and described first or door are electric
The first input end on road connects；
Second input terminal of first OR circuit is connect with the output end of second edge triggered flip flop, and described first or door
The output end of circuit is connect with the first input end of the low-level latch circuit.
6. optical module according to claim 1, which is characterized in that the logic gates includes reverser and first or door
Circuit, the pulse latch cicuit are low level pulse latch cicuit, wherein：
The input terminal of the reverser is connect with the output end of second edge triggered flip flop, output end and described first or door are electric
The first input end on road connects；
Second input terminal of first OR circuit is connect with the output end of first edge triggered flip flop, and described first or door
The output end of circuit is connect with the first input end of the low-level latch circuit.
7. optical module according to claim 5 or 6, which is characterized in that the low level pulse latch cicuit includes first
AND gate circuit and the second OR circuit, wherein：
The first input end of first AND gate circuit connect with the output end of first OR circuit, the second input terminal and institute
State the output end connection of the second OR circuit, output end is connect with the first input end of second OR circuit；
The second input terminal for receiving clear interrupt signal is additionally provided in second OR circuit and for exporting interrupt signal
Output end.
8. optical module according to claim 1, which is characterized in that first edge triggered flip flop, the second edge triggered flip flop,
Logic gates and pulse latch cicuit are realized by the PLA units configured in microcontroller.
9. optical module according to claim 1, which is characterized in that the optical module further include trigger signal receiving unit,
Microcontroller crystal oscillator and clear interrupt signal transmission unit, wherein：
The trigger signal receiving unit is connect with the first input end of first edge triggered flip flop；
The monolithic crystal oscillator respectively with the second input terminal of first edge triggered flip flop and second edge triggered flip flop
Second input terminal connects；
The clear interrupt signal transmission unit is connect with the second input terminal of the pulse latch cicuit.
10. optical module according to claim 1, which is characterized in that first edge triggered flip flop and second edge
Trigger is rising edge d type flip flop.
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| US5410528A (en) * | 1992-02-14 | 1995-04-25 | Fujitsu Limited | Servo tracking circuit of an optically writable/readable/erasable disk |
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| CN103384165A (en) * | 2012-11-15 | 2013-11-06 | 上海斐讯数据通信技术有限公司 | Long-time light-emitting detection circuit |
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| CN104917497A (en) * | 2015-07-15 | 2015-09-16 | 中国工程物理研究院流体物理研究所 | Logic delay locking based anti-interference circuit and method |
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|---|---|---|---|---|
| US5410528A (en) * | 1992-02-14 | 1995-04-25 | Fujitsu Limited | Servo tracking circuit of an optically writable/readable/erasable disk |
| KR20090058388A (en) * | 2007-12-04 | 2009-06-09 | 주식회사 케이티 | The optical network unit with malfunction detecting ability in a tdm passive optical network and the malfuncion detecting method |
| CN103384165A (en) * | 2012-11-15 | 2013-11-06 | 上海斐讯数据通信技术有限公司 | Long-time light-emitting detection circuit |
| CN103645794A (en) * | 2013-11-15 | 2014-03-19 | 北京兆易创新科技股份有限公司 | Chip and method for achieving sleep mode wake-up through edge detection circuit |
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